Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100785228	1			T2	36732		T4	455		T5	3
all_pins[1]	100785228	1			T2	36732		T4	455		T5	3
all_pins[2]	100785228	1			T2	36732		T4	455		T5	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301498266	1			T2	109740		T4	1360		T5	9
values[0x1]	857418	1			T2	456		T4	5		T14	580
transitions[0x0=>0x1]	855230	1			T2	456		T4	5		T14	580
transitions[0x1=>0x0]	855256	1			T2	456		T4	5		T14	580

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100277657	1			T2	36276		T4	450		T5	3
all_pins[0]	values[0x1]	507571	1			T2	456		T4	5		T14	580
all_pins[0]	transitions[0x0=>0x1]	507558	1			T2	456		T4	5		T14	580
all_pins[0]	transitions[0x1=>0x0]	50	1			T111	2		T174	6		T118	3
all_pins[1]	values[0x0]	100785165	1			T2	36732		T4	455		T5	3
all_pins[1]	values[0x1]	63	1			T111	2		T174	6		T118	3
all_pins[1]	transitions[0x0=>0x1]	49	1			T111	2		T174	6		T118	3
all_pins[1]	transitions[0x1=>0x0]	349770	1			T24	3682		T25	2553		T26	2464
all_pins[2]	values[0x0]	100435444	1			T2	36732		T4	455		T5	3
all_pins[2]	values[0x1]	349784	1			T24	3682		T25	2553		T26	2464
all_pins[2]	transitions[0x0=>0x1]	347623	1			T24	3657		T25	2541		T26	2450
all_pins[2]	transitions[0x1=>0x0]	505436	1			T2	456		T4	5		T14	580