Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	675	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5509	1			T2	38		T15	22		T19	22
len_601_800	12271	1			T2	70		T4	1		T15	65
len_401_600	8283	1			T2	59		T15	48		T19	27
len_201_400	16282	1			T2	21		T4	1		T15	16
len_65_200	73978	1			T2	33		T15	15		T17	685
len_min_for_xof_require_squeeze	991	1			T2	1		T15	2		T17	9
len_keccak_block_sizes[72]	766	1			T17	9		T82	5		T78	1
len_keccak_block_sizes[104]	745	1			T17	9		T42	1		T82	5
len_keccak_block_sizes[136]	740	1			T17	9		T82	5		T178	9
len_keccak_block_sizes[144]	285	1			T82	5		T25	1		T179	5
len_keccak_block_sizes[168]	284	1			T82	5		T179	5		T180	5
len_datapath_width	14134	1			T2	23		T15	2		T16	3
len_2_63	214420	1			T2	104		T4	3		T14	390
len_1	51	1			T181	2		T182	1		T75	1