Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100926367	1			T1	208148		T2	158924		T3	218885
all_values[1]	100926367	1			T1	208148		T2	158924		T3	218885
all_values[2]	100926367	1			T1	208148		T2	158924		T3	218885

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616090

1

T1

18

T2

16

T3

9

auto[1]

302163011

1

T1

624426

T2

476756

T3

656646

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301240110

1

T1

622782

T2

475356

T3

654891

auto[1]

1538991

1

T1

1662

T2

1416

T3

1764

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	237315	1			T1	3		T2	8		T3	1
all_values[0]	auto[0]	auto[1]	2099	1			T1	4		T2	8		T3	2
all_values[0]	auto[1]	auto[0]	100176055	1			T1	207591		T2	158444		T3	218296
all_values[0]	auto[1]	auto[1]	510898	1			T1	550		T2	464		T3	586
all_values[1]	auto[0]	auto[0]	178905	1			T3	1		T14	8		T15	32
all_values[1]	auto[0]	auto[1]	1567	1			T3	2		T14	3		T15	4
all_values[1]	auto[1]	auto[0]	100234465	1			T1	207594		T2	158452		T3	218296
all_values[1]	auto[1]	auto[1]	511430	1			T1	554		T2	472		T3	586
all_values[2]	auto[0]	auto[0]	194603	1			T1	6		T3	1		T14	8
all_values[2]	auto[0]	auto[1]	1601	1			T1	5		T3	2		T14	3
all_values[2]	auto[1]	auto[0]	100218767	1			T1	207588		T2	158452		T3	218296
all_values[2]	auto[1]	auto[1]	511396	1			T1	549		T2	472		T3	586