Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
328036 |
1 |
|
|
T1 |
2 |
|
T2 |
620 |
|
T3 |
780 |
auto[1] |
369290 |
1 |
|
|
T1 |
746 |
|
T13 |
778 |
|
T43 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175553 |
1 |
|
|
T1 |
182 |
|
T2 |
180 |
|
T3 |
180 |
lower_val |
172257 |
1 |
|
|
T1 |
180 |
|
T2 |
132 |
|
T3 |
177 |
zero_val |
1833 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
349494 |
1 |
|
|
T1 |
384 |
|
T2 |
326 |
|
T3 |
386 |
lower_val |
347822 |
1 |
|
|
T1 |
364 |
|
T2 |
294 |
|
T3 |
394 |
zero_val |
10 |
1 |
|
|
T183 |
2 |
|
T184 |
2 |
|
T185 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41538 |
1 |
|
|
T2 |
99 |
|
T3 |
90 |
|
T14 |
103 |
higher_val |
higher_val |
auto[1] |
46720 |
1 |
|
|
T1 |
90 |
|
T13 |
114 |
|
T46 |
26 |
higher_val |
lower_val |
auto[0] |
40779 |
1 |
|
|
T1 |
1 |
|
T2 |
81 |
|
T3 |
90 |
higher_val |
lower_val |
auto[1] |
46513 |
1 |
|
|
T1 |
91 |
|
T13 |
81 |
|
T46 |
41 |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T186 |
2 |
|
T187 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
40598 |
1 |
|
|
T2 |
63 |
|
T3 |
92 |
|
T14 |
85 |
lower_val |
higher_val |
auto[1] |
45679 |
1 |
|
|
T1 |
103 |
|
T13 |
122 |
|
T46 |
26 |
lower_val |
lower_val |
auto[0] |
40214 |
1 |
|
|
T2 |
69 |
|
T3 |
85 |
|
T14 |
101 |
lower_val |
lower_val |
auto[1] |
45764 |
1 |
|
|
T1 |
77 |
|
T13 |
78 |
|
T43 |
2 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T185 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T184 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
626 |
1 |
|
|
T13 |
1 |
|
T14 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
242 |
1 |
|
|
T1 |
2 |
|
T48 |
2 |
|
T94 |
1 |
zero_val |
lower_val |
auto[0] |
674 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
291 |
1 |
|
|
T132 |
2 |
|
T94 |
1 |
|
T129 |
2 |