Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100926367	1			T1	208148		T2	158924		T3	218885
all_pins[1]	100926367	1			T1	208148		T2	158924		T3	218885
all_pins[2]	100926367	1			T1	208148		T2	158924		T3	218885

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301958958	1			T1	623894		T2	476308		T3	656069
values[0x1]	820143	1			T1	550		T2	464		T3	586
transitions[0x0=>0x1]	818257	1			T1	550		T2	464		T3	586
transitions[0x1=>0x0]	818286	1			T1	550		T2	464		T3	586

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100415469	1			T1	207598		T2	158460		T3	218299
all_pins[0]	values[0x1]	510898	1			T1	550		T2	464		T3	586
all_pins[0]	transitions[0x0=>0x1]	510881	1			T1	550		T2	464		T3	586
all_pins[0]	transitions[0x1=>0x0]	60	1			T51	3		T199	3		T200	3
all_pins[1]	values[0x0]	100926290	1			T1	208148		T2	158924		T3	218885
all_pins[1]	values[0x1]	77	1			T51	3		T199	3		T200	3
all_pins[1]	transitions[0x0=>0x1]	64	1			T51	3		T199	3		T200	3
all_pins[1]	transitions[0x1=>0x0]	309155	1			T22	787		T34	244		T35	1371
all_pins[2]	values[0x0]	100617199	1			T1	208148		T2	158924		T3	218885
all_pins[2]	values[0x1]	309168	1			T22	787		T34	244		T35	1371
all_pins[2]	transitions[0x0=>0x1]	307312	1			T22	787		T34	244		T35	1371
all_pins[2]	transitions[0x1=>0x0]	509071	1			T1	550		T2	464		T3	586