Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	672	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5725	1			T15	10		T4	2		T45	22
len_601_800	13001	1			T15	12		T4	1		T18	5
len_401_600	8509	1			T15	12		T18	2		T45	46
len_201_400	16627	1			T15	5		T18	1		T45	16
len_65_200	74077	1			T15	4		T4	1		T18	2
len_min_for_xof_require_squeeze	993	1			T104	2		T96	10		T123	9
len_keccak_block_sizes[72]	735	1			T104	1		T96	5		T123	9
len_keccak_block_sizes[104]	745	1			T104	2		T96	5		T122	1
len_keccak_block_sizes[136]	761	1			T46	2		T104	1		T96	5
len_keccak_block_sizes[144]	283	1			T94	1		T104	1		T96	5
len_keccak_block_sizes[168]	290	1			T104	2		T96	5		T129	5
len_datapath_width	14090	1			T17	246		T43	6		T48	246
len_2_63	214768	1			T1	374		T2	310		T3	390
len_1	56	1			T104	1		T30	1		T28	1