Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
10945137 | 
1 | 
 | 
 | 
T1 | 
2992 | 
 | 
T2 | 
3720 | 
 | 
T3 | 
2730 | 
| auto[1] | 
26032889 | 
1 | 
 | 
 | 
T1 | 
18700 | 
 | 
T2 | 
15500 | 
 | 
T3 | 
19500 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
4 | 
0 | 
4 | 
100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 
36857679 | 
1 | 
 | 
 | 
T1 | 
21692 | 
 | 
T2 | 
19220 | 
 | 
T3 | 
22230 | 
| triple_byte_access | 
40147 | 
1 | 
 | 
 | 
T15 | 
11 | 
 | 
T4 | 
2 | 
 | 
T18 | 
2 | 
| halfword_access | 
40194 | 
1 | 
 | 
 | 
T15 | 
11 | 
 | 
T4 | 
1 | 
 | 
T18 | 
3 | 
| byte_access | 
40006 | 
1 | 
 | 
 | 
T15 | 
10 | 
 | 
T18 | 
4 | 
 | 
T45 | 
37 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
8 | 
3 | 
5 | 
62.50  | 
3 | 
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
[triple_byte_access , halfword_access , byte_access] | 
-- | 
-- | 
3 | 
 | 
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
word_access | 
10824790 | 
1 | 
 | 
 | 
T1 | 
2992 | 
 | 
T2 | 
3720 | 
 | 
T3 | 
2730 | 
| auto[0] | 
triple_byte_access | 
40147 | 
1 | 
 | 
 | 
T15 | 
11 | 
 | 
T4 | 
2 | 
 | 
T18 | 
2 | 
| auto[0] | 
halfword_access | 
40194 | 
1 | 
 | 
 | 
T15 | 
11 | 
 | 
T4 | 
1 | 
 | 
T18 | 
3 | 
| auto[0] | 
byte_access | 
40006 | 
1 | 
 | 
 | 
T15 | 
10 | 
 | 
T18 | 
4 | 
 | 
T45 | 
37 | 
| auto[1] | 
word_access | 
26032889 | 
1 | 
 | 
 | 
T1 | 
18700 | 
 | 
T2 | 
15500 | 
 | 
T3 | 
19500 |