Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.31 96.18 92.38 100.00 88.64 94.52 98.84 96.60


Total test records in report: 1241
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T1058 /workspace/coverage/default/40.kmac_long_msg_and_output.3809690913 Mar 24 01:31:52 PM PDT 24 Mar 24 02:12:11 PM PDT 24 79671832452 ps
T1059 /workspace/coverage/default/47.kmac_alert_test.879643721 Mar 24 01:33:59 PM PDT 24 Mar 24 01:33:59 PM PDT 24 60602150 ps
T1060 /workspace/coverage/default/42.kmac_app.80585922 Mar 24 01:32:32 PM PDT 24 Mar 24 01:33:10 PM PDT 24 1893701500 ps
T1061 /workspace/coverage/default/10.kmac_edn_timeout_error.2029544817 Mar 24 01:26:26 PM PDT 24 Mar 24 01:26:33 PM PDT 24 339636348 ps
T1062 /workspace/coverage/default/45.kmac_entropy_refresh.2881183907 Mar 24 01:33:30 PM PDT 24 Mar 24 01:34:31 PM PDT 24 9806316228 ps
T1063 /workspace/coverage/default/44.kmac_alert_test.3925908950 Mar 24 01:33:14 PM PDT 24 Mar 24 01:33:16 PM PDT 24 54257324 ps
T1064 /workspace/coverage/default/46.kmac_app.3135788571 Mar 24 01:33:44 PM PDT 24 Mar 24 01:38:28 PM PDT 24 61231626917 ps
T1065 /workspace/coverage/default/32.kmac_key_error.3097074039 Mar 24 01:29:52 PM PDT 24 Mar 24 01:29:54 PM PDT 24 1259827552 ps
T1066 /workspace/coverage/default/1.kmac_lc_escalation.802554247 Mar 24 01:25:18 PM PDT 24 Mar 24 01:25:20 PM PDT 24 76585181 ps
T1067 /workspace/coverage/default/38.kmac_key_error.72926288 Mar 24 01:31:33 PM PDT 24 Mar 24 01:31:40 PM PDT 24 6633565197 ps
T1068 /workspace/coverage/default/29.kmac_key_error.70846325 Mar 24 01:29:19 PM PDT 24 Mar 24 01:29:22 PM PDT 24 1095397945 ps
T1069 /workspace/coverage/default/49.kmac_key_error.271965822 Mar 24 01:34:32 PM PDT 24 Mar 24 01:34:34 PM PDT 24 955642966 ps
T1070 /workspace/coverage/default/22.kmac_error.3921406855 Mar 24 01:28:01 PM PDT 24 Mar 24 01:31:02 PM PDT 24 14900728330 ps
T1071 /workspace/coverage/default/0.kmac_test_vectors_shake_256.2062622036 Mar 24 01:25:05 PM PDT 24 Mar 24 02:27:46 PM PDT 24 408631742551 ps
T1072 /workspace/coverage/default/18.kmac_burst_write.1375050539 Mar 24 01:27:25 PM PDT 24 Mar 24 01:38:47 PM PDT 24 94038469265 ps
T1073 /workspace/coverage/default/45.kmac_alert_test.163822159 Mar 24 01:33:32 PM PDT 24 Mar 24 01:33:33 PM PDT 24 45455986 ps
T1074 /workspace/coverage/default/48.kmac_app.2047703913 Mar 24 01:34:07 PM PDT 24 Mar 24 01:37:02 PM PDT 24 2972700429 ps
T1075 /workspace/coverage/default/41.kmac_entropy_refresh.2300963215 Mar 24 01:32:17 PM PDT 24 Mar 24 01:36:25 PM PDT 24 130085301064 ps
T1076 /workspace/coverage/default/41.kmac_test_vectors_sha3_256.319901920 Mar 24 01:32:17 PM PDT 24 Mar 24 02:01:22 PM PDT 24 61547761193 ps
T1077 /workspace/coverage/default/9.kmac_error.1954029086 Mar 24 01:26:16 PM PDT 24 Mar 24 01:30:12 PM PDT 24 79203605927 ps
T1078 /workspace/coverage/default/9.kmac_burst_write.1140429191 Mar 24 01:26:12 PM PDT 24 Mar 24 01:35:11 PM PDT 24 36566526219 ps
T187 /workspace/coverage/default/42.kmac_test_vectors_shake_128.59511995 Mar 24 01:32:28 PM PDT 24 Mar 24 02:52:50 PM PDT 24 2160243095513 ps
T1079 /workspace/coverage/default/40.kmac_test_vectors_sha3_224.871025361 Mar 24 01:31:52 PM PDT 24 Mar 24 02:04:11 PM PDT 24 68273837660 ps
T1080 /workspace/coverage/default/39.kmac_smoke.1691570075 Mar 24 01:31:35 PM PDT 24 Mar 24 01:31:40 PM PDT 24 507212184 ps
T1081 /workspace/coverage/default/38.kmac_burst_write.453506862 Mar 24 01:31:19 PM PDT 24 Mar 24 01:42:58 PM PDT 24 43633067109 ps
T1082 /workspace/coverage/default/49.kmac_burst_write.979878253 Mar 24 01:34:22 PM PDT 24 Mar 24 01:44:24 PM PDT 24 27781750314 ps
T107 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3161884535 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:49 PM PDT 24 93990149 ps
T108 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.819935244 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:45 PM PDT 24 105540066 ps
T1083 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1645121543 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:01 PM PDT 24 52094534 ps
T146 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1987790099 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:07 PM PDT 24 52044014 ps
T1084 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2910190653 Mar 24 12:34:56 PM PDT 24 Mar 24 12:34:58 PM PDT 24 25955155 ps
T147 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.534084858 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:56 PM PDT 24 191185152 ps
T109 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2699367554 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:55 PM PDT 24 109380749 ps
T138 /workspace/coverage/cover_reg_top/13.kmac_intr_test.127653817 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:10 PM PDT 24 13535724 ps
T139 /workspace/coverage/cover_reg_top/11.kmac_intr_test.965280561 Mar 24 12:35:02 PM PDT 24 Mar 24 12:35:03 PM PDT 24 15437636 ps
T135 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2719265260 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:50 PM PDT 24 77657426 ps
T113 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.79110242 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:04 PM PDT 24 99024607 ps
T110 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2203294941 Mar 24 12:34:46 PM PDT 24 Mar 24 12:34:48 PM PDT 24 40977936 ps
T114 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1759827009 Mar 24 12:34:59 PM PDT 24 Mar 24 12:35:02 PM PDT 24 89697459 ps
T148 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3106869243 Mar 24 12:35:09 PM PDT 24 Mar 24 12:35:12 PM PDT 24 247269796 ps
T1085 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2379780187 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:46 PM PDT 24 138898956 ps
T158 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.88927527 Mar 24 12:34:40 PM PDT 24 Mar 24 12:34:42 PM PDT 24 20512419 ps
T140 /workspace/coverage/cover_reg_top/17.kmac_intr_test.3438630361 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:01 PM PDT 24 22625000 ps
T179 /workspace/coverage/cover_reg_top/27.kmac_intr_test.763116305 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:00 PM PDT 24 15095842 ps
T182 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.816562439 Mar 24 12:34:56 PM PDT 24 Mar 24 12:35:01 PM PDT 24 480833780 ps
T1086 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.4116717381 Mar 24 12:34:56 PM PDT 24 Mar 24 12:34:58 PM PDT 24 35426507 ps
T1087 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3921513496 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:02 PM PDT 24 43093419 ps
T136 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3421409031 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:15 PM PDT 24 179401503 ps
T197 /workspace/coverage/cover_reg_top/28.kmac_intr_test.816591235 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:02 PM PDT 24 20899051 ps
T137 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.4146532070 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:03 PM PDT 24 221651908 ps
T159 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3137453233 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:57 PM PDT 24 25321784 ps
T163 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3544481980 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:17 PM PDT 24 291673859 ps
T164 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1327742474 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:07 PM PDT 24 591885068 ps
T198 /workspace/coverage/cover_reg_top/31.kmac_intr_test.3140824456 Mar 24 12:35:12 PM PDT 24 Mar 24 12:35:13 PM PDT 24 15972561 ps
T194 /workspace/coverage/cover_reg_top/5.kmac_intr_test.1043820961 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:54 PM PDT 24 26669278 ps
T165 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3035975539 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:59 PM PDT 24 1672224610 ps
T1088 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.700857381 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:12 PM PDT 24 24892147 ps
T1089 /workspace/coverage/cover_reg_top/3.kmac_intr_test.1544397070 Mar 24 12:34:37 PM PDT 24 Mar 24 12:34:39 PM PDT 24 42260073 ps
T195 /workspace/coverage/cover_reg_top/15.kmac_intr_test.116258956 Mar 24 12:34:45 PM PDT 24 Mar 24 12:34:46 PM PDT 24 20435116 ps
T1090 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.101900864 Mar 24 12:34:45 PM PDT 24 Mar 24 12:35:02 PM PDT 24 962185835 ps
T166 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.212142904 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:56 PM PDT 24 81565658 ps
T1091 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.18983305 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:11 PM PDT 24 2887608657 ps
T180 /workspace/coverage/cover_reg_top/19.kmac_intr_test.2509096473 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:03 PM PDT 24 19100861 ps
T167 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.756573971 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:03 PM PDT 24 82019864 ps
T196 /workspace/coverage/cover_reg_top/43.kmac_intr_test.1835680510 Mar 24 12:34:56 PM PDT 24 Mar 24 12:34:57 PM PDT 24 33695240 ps
T202 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.288930143 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:08 PM PDT 24 56597334 ps
T141 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2086733898 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:48 PM PDT 24 79195524 ps
T1092 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2644290348 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:46 PM PDT 24 46469582 ps
T1093 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1433640634 Mar 24 12:34:59 PM PDT 24 Mar 24 12:35:01 PM PDT 24 26576547 ps
T168 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.2891682346 Mar 24 12:34:37 PM PDT 24 Mar 24 12:34:39 PM PDT 24 25867444 ps
T1094 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3742449791 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:05 PM PDT 24 245919122 ps
T1095 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3342601499 Mar 24 12:34:40 PM PDT 24 Mar 24 12:34:42 PM PDT 24 100448236 ps
T1096 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1854163265 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:01 PM PDT 24 17142850 ps
T1097 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1904637572 Mar 24 12:34:45 PM PDT 24 Mar 24 12:34:46 PM PDT 24 11509030 ps
T1098 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3174462356 Mar 24 12:34:52 PM PDT 24 Mar 24 12:34:55 PM PDT 24 90854090 ps
T169 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4268435714 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:50 PM PDT 24 252103817 ps
T1099 /workspace/coverage/cover_reg_top/26.kmac_intr_test.2601959072 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:06 PM PDT 24 15291786 ps
T1100 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1874710987 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:07 PM PDT 24 78675425 ps
T1101 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.839819359 Mar 24 12:35:09 PM PDT 24 Mar 24 12:35:12 PM PDT 24 273318224 ps
T1102 /workspace/coverage/cover_reg_top/6.kmac_intr_test.2660737505 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:07 PM PDT 24 36021404 ps
T1103 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.4037958963 Mar 24 12:34:38 PM PDT 24 Mar 24 12:34:39 PM PDT 24 22791679 ps
T118 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.528947707 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:02 PM PDT 24 23077049 ps
T1104 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1725938692 Mar 24 12:34:46 PM PDT 24 Mar 24 12:34:47 PM PDT 24 52213291 ps
T181 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3878254953 Mar 24 12:34:59 PM PDT 24 Mar 24 12:35:03 PM PDT 24 111481547 ps
T1105 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1501761333 Mar 24 12:34:46 PM PDT 24 Mar 24 12:34:49 PM PDT 24 279758354 ps
T1106 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2324402747 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:05 PM PDT 24 20612132 ps
T1107 /workspace/coverage/cover_reg_top/36.kmac_intr_test.609258536 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:02 PM PDT 24 31524237 ps
T133 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.861756722 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:00 PM PDT 24 939809862 ps
T1108 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3144940411 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:55 PM PDT 24 47804277 ps
T1109 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2232321895 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:54 PM PDT 24 1997649224 ps
T1110 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3578507479 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:07 PM PDT 24 75965761 ps
T1111 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3181496584 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:05 PM PDT 24 370575454 ps
T1112 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3139883647 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:46 PM PDT 24 129066110 ps
T1113 /workspace/coverage/cover_reg_top/21.kmac_intr_test.3066366031 Mar 24 12:35:12 PM PDT 24 Mar 24 12:35:23 PM PDT 24 15339230 ps
T1114 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2963788206 Mar 24 12:34:51 PM PDT 24 Mar 24 12:34:59 PM PDT 24 1433366396 ps
T1115 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1037795669 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:55 PM PDT 24 28790301 ps
T1116 /workspace/coverage/cover_reg_top/46.kmac_intr_test.3918890246 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:59 PM PDT 24 43642366 ps
T134 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3839889716 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:56 PM PDT 24 83549963 ps
T1117 /workspace/coverage/cover_reg_top/23.kmac_intr_test.2237290560 Mar 24 12:34:56 PM PDT 24 Mar 24 12:34:57 PM PDT 24 48183559 ps
T1118 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3159081385 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:02 PM PDT 24 19701476 ps
T1119 /workspace/coverage/cover_reg_top/33.kmac_intr_test.2472087739 Mar 24 12:35:07 PM PDT 24 Mar 24 12:35:10 PM PDT 24 14967414 ps
T1120 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.969903232 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:08 PM PDT 24 107726397 ps
T117 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3878702142 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:02 PM PDT 24 104767060 ps
T1121 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2538446439 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:01 PM PDT 24 33309672 ps
T1122 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3535022883 Mar 24 12:34:56 PM PDT 24 Mar 24 12:35:03 PM PDT 24 1803616412 ps
T1123 /workspace/coverage/cover_reg_top/20.kmac_intr_test.3279351024 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:45 PM PDT 24 25987618 ps
T1124 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1495093533 Mar 24 12:34:55 PM PDT 24 Mar 24 12:34:58 PM PDT 24 139963116 ps
T212 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.2159829819 Mar 24 12:34:42 PM PDT 24 Mar 24 12:34:45 PM PDT 24 131422319 ps
T1125 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2102953053 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:57 PM PDT 24 369459955 ps
T111 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1813658058 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:16 PM PDT 24 92049756 ps
T1126 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1729957424 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:06 PM PDT 24 79414676 ps
T1127 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.231577379 Mar 24 12:34:46 PM PDT 24 Mar 24 12:34:48 PM PDT 24 34299987 ps
T203 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3858002759 Mar 24 12:35:13 PM PDT 24 Mar 24 12:35:19 PM PDT 24 731895386 ps
T1128 /workspace/coverage/cover_reg_top/34.kmac_intr_test.1070854714 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:18 PM PDT 24 15673368 ps
T209 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1835362124 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:01 PM PDT 24 121923013 ps
T1129 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.1525846585 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:04 PM PDT 24 109844303 ps
T1130 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3292563875 Mar 24 12:34:51 PM PDT 24 Mar 24 12:34:54 PM PDT 24 67041537 ps
T1131 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2999816692 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:07 PM PDT 24 45204272 ps
T1132 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1709315960 Mar 24 12:35:13 PM PDT 24 Mar 24 12:35:14 PM PDT 24 42934914 ps
T1133 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3684541436 Mar 24 12:34:50 PM PDT 24 Mar 24 12:35:07 PM PDT 24 2374575786 ps
T1134 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3256602828 Mar 24 12:35:02 PM PDT 24 Mar 24 12:35:05 PM PDT 24 43654306 ps
T1135 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3643782702 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:08 PM PDT 24 151506205 ps
T206 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.144788230 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:58 PM PDT 24 240839352 ps
T1136 /workspace/coverage/cover_reg_top/18.kmac_intr_test.2336318949 Mar 24 12:35:18 PM PDT 24 Mar 24 12:35:19 PM PDT 24 37595854 ps
T1137 /workspace/coverage/cover_reg_top/14.kmac_intr_test.362268497 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:10 PM PDT 24 16140584 ps
T1138 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.904196449 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:49 PM PDT 24 106106441 ps
T112 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.566957089 Mar 24 12:35:08 PM PDT 24 Mar 24 12:35:12 PM PDT 24 125000390 ps
T115 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2551344087 Mar 24 12:35:07 PM PDT 24 Mar 24 12:35:11 PM PDT 24 49969766 ps
T1139 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.1231532143 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:02 PM PDT 24 228892568 ps
T1140 /workspace/coverage/cover_reg_top/24.kmac_intr_test.912104593 Mar 24 12:34:46 PM PDT 24 Mar 24 12:34:47 PM PDT 24 51505299 ps
T1141 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.187535029 Mar 24 12:35:07 PM PDT 24 Mar 24 12:35:10 PM PDT 24 123548983 ps
T1142 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3242470912 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:14 PM PDT 24 2083275771 ps
T205 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2359842039 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:07 PM PDT 24 736322101 ps
T1143 /workspace/coverage/cover_reg_top/37.kmac_intr_test.3546785842 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:54 PM PDT 24 15112536 ps
T1144 /workspace/coverage/cover_reg_top/35.kmac_intr_test.2284903870 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:17 PM PDT 24 14305720 ps
T1145 /workspace/coverage/cover_reg_top/2.kmac_intr_test.2541067200 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:12 PM PDT 24 33152442 ps
T1146 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.215445503 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:23 PM PDT 24 15130227 ps
T1147 /workspace/coverage/cover_reg_top/39.kmac_intr_test.173666044 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:03 PM PDT 24 44210501 ps
T160 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.32024728 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:04 PM PDT 24 238501615 ps
T208 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2092192448 Mar 24 12:34:39 PM PDT 24 Mar 24 12:34:43 PM PDT 24 98411053 ps
T1148 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.48315926 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:06 PM PDT 24 69652882 ps
T1149 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2279895944 Mar 24 12:35:13 PM PDT 24 Mar 24 12:35:15 PM PDT 24 31869187 ps
T1150 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2693990758 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:54 PM PDT 24 30931891 ps
T1151 /workspace/coverage/cover_reg_top/10.kmac_intr_test.2690274252 Mar 24 12:35:12 PM PDT 24 Mar 24 12:35:13 PM PDT 24 33621948 ps
T161 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1599395918 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:54 PM PDT 24 21558581 ps
T1152 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1399982982 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:56 PM PDT 24 172686989 ps
T210 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.4043692044 Mar 24 12:34:51 PM PDT 24 Mar 24 12:34:56 PM PDT 24 4341143921 ps
T1153 /workspace/coverage/cover_reg_top/0.kmac_intr_test.2889185180 Mar 24 12:34:39 PM PDT 24 Mar 24 12:34:40 PM PDT 24 47547340 ps
T1154 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1177316291 Mar 24 12:34:43 PM PDT 24 Mar 24 12:34:45 PM PDT 24 50959716 ps
T1155 /workspace/coverage/cover_reg_top/48.kmac_intr_test.257981545 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:10 PM PDT 24 16716270 ps
T1156 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2718702826 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:06 PM PDT 24 36699553 ps
T1157 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.984106654 Mar 24 12:34:42 PM PDT 24 Mar 24 12:34:44 PM PDT 24 61089083 ps
T1158 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.122474908 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:52 PM PDT 24 539509160 ps
T116 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3683972171 Mar 24 12:34:55 PM PDT 24 Mar 24 12:34:57 PM PDT 24 30646833 ps
T1159 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1482641385 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:10 PM PDT 24 16284171 ps
T1160 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2603394216 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:13 PM PDT 24 435627556 ps
T1161 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.874383924 Mar 24 12:34:59 PM PDT 24 Mar 24 12:35:02 PM PDT 24 33847939 ps
T1162 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2701686080 Mar 24 12:34:55 PM PDT 24 Mar 24 12:34:57 PM PDT 24 55901627 ps
T1163 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.956511927 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:03 PM PDT 24 47974752 ps
T1164 /workspace/coverage/cover_reg_top/22.kmac_intr_test.2624590256 Mar 24 12:35:02 PM PDT 24 Mar 24 12:35:03 PM PDT 24 17807371 ps
T207 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.368800714 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:04 PM PDT 24 276757646 ps
T1165 /workspace/coverage/cover_reg_top/8.kmac_intr_test.600647400 Mar 24 12:35:09 PM PDT 24 Mar 24 12:35:10 PM PDT 24 72289433 ps
T1166 /workspace/coverage/cover_reg_top/30.kmac_intr_test.4207014836 Mar 24 12:34:51 PM PDT 24 Mar 24 12:34:52 PM PDT 24 29709929 ps
T1167 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.94756787 Mar 24 12:34:38 PM PDT 24 Mar 24 12:34:40 PM PDT 24 62778799 ps
T1168 /workspace/coverage/cover_reg_top/38.kmac_intr_test.2690558428 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:19 PM PDT 24 14298094 ps
T1169 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3367364440 Mar 24 12:34:49 PM PDT 24 Mar 24 12:34:51 PM PDT 24 69562996 ps
T1170 /workspace/coverage/cover_reg_top/44.kmac_intr_test.574747278 Mar 24 12:34:55 PM PDT 24 Mar 24 12:34:57 PM PDT 24 17988014 ps
T1171 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2518466044 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:16 PM PDT 24 66387296 ps
T1172 /workspace/coverage/cover_reg_top/9.kmac_intr_test.860567504 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:18 PM PDT 24 48989492 ps
T1173 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.931291412 Mar 24 12:34:56 PM PDT 24 Mar 24 12:35:00 PM PDT 24 186583031 ps
T1174 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.535684797 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:58 PM PDT 24 566345179 ps
T1175 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2376231819 Mar 24 12:35:13 PM PDT 24 Mar 24 12:35:15 PM PDT 24 74600099 ps
T1176 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3738516594 Mar 24 12:34:56 PM PDT 24 Mar 24 12:34:58 PM PDT 24 28602411 ps
T1177 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.2934692868 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:49 PM PDT 24 22899142 ps
T1178 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.590337307 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:50 PM PDT 24 336063103 ps
T1179 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3003637424 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:23 PM PDT 24 68633516 ps
T204 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.911188436 Mar 24 12:35:08 PM PDT 24 Mar 24 12:35:13 PM PDT 24 125368096 ps
T1180 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.600090438 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:06 PM PDT 24 400246677 ps
T1181 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.3640630841 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:05 PM PDT 24 158322157 ps
T1182 /workspace/coverage/cover_reg_top/25.kmac_intr_test.4249524011 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:07 PM PDT 24 59488326 ps
T1183 /workspace/coverage/cover_reg_top/1.kmac_intr_test.3918829021 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:49 PM PDT 24 45501613 ps
T1184 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.582228598 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:00 PM PDT 24 80834473 ps
T1185 /workspace/coverage/cover_reg_top/32.kmac_intr_test.29972364 Mar 24 12:35:07 PM PDT 24 Mar 24 12:35:10 PM PDT 24 72399924 ps
T1186 /workspace/coverage/cover_reg_top/40.kmac_intr_test.1247081332 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:04 PM PDT 24 29896110 ps
T162 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2147201239 Mar 24 12:34:56 PM PDT 24 Mar 24 12:34:59 PM PDT 24 142191183 ps
T1187 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2881508670 Mar 24 12:34:47 PM PDT 24 Mar 24 12:35:02 PM PDT 24 576323528 ps
T1188 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3257760701 Mar 24 12:35:19 PM PDT 24 Mar 24 12:35:20 PM PDT 24 12970430 ps
T1189 /workspace/coverage/cover_reg_top/4.kmac_intr_test.2187553055 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:05 PM PDT 24 17514629 ps
T1190 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3327624521 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:51 PM PDT 24 373091403 ps
T1191 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1114730487 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:03 PM PDT 24 74552740 ps
T1192 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.4130444625 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:12 PM PDT 24 146328457 ps
T1193 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1200290073 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:04 PM PDT 24 82085755 ps
T1194 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3235986811 Mar 24 12:34:50 PM PDT 24 Mar 24 12:34:51 PM PDT 24 63941328 ps
T1195 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1042374996 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:49 PM PDT 24 43656432 ps
T1196 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3796444879 Mar 24 12:34:56 PM PDT 24 Mar 24 12:34:58 PM PDT 24 43678748 ps
T1197 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.337178961 Mar 24 12:35:13 PM PDT 24 Mar 24 12:35:15 PM PDT 24 25954429 ps
T1198 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3739632497 Mar 24 12:34:50 PM PDT 24 Mar 24 12:34:51 PM PDT 24 29085234 ps
T1199 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2389897842 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:04 PM PDT 24 20085182 ps
T1200 /workspace/coverage/cover_reg_top/41.kmac_intr_test.3782124747 Mar 24 12:35:08 PM PDT 24 Mar 24 12:35:10 PM PDT 24 48596680 ps
T1201 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1392540279 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:49 PM PDT 24 38778053 ps
T1202 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1086475643 Mar 24 12:35:07 PM PDT 24 Mar 24 12:35:10 PM PDT 24 86977701 ps
T211 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1565526675 Mar 24 12:35:07 PM PDT 24 Mar 24 12:35:10 PM PDT 24 305763183 ps
T1203 /workspace/coverage/cover_reg_top/16.kmac_intr_test.4286188032 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:10 PM PDT 24 11628972 ps
T1204 /workspace/coverage/cover_reg_top/29.kmac_intr_test.1993827561 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:02 PM PDT 24 30390087 ps
T1205 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1310547949 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:08 PM PDT 24 95693679 ps
T1206 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1862742163 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:48 PM PDT 24 86552359 ps
T1207 /workspace/coverage/cover_reg_top/49.kmac_intr_test.3170086828 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:12 PM PDT 24 12219325 ps
T1208 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.131786393 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:01 PM PDT 24 164951009 ps
T1209 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2279710333 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:00 PM PDT 24 38905202 ps
T1210 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.365062783 Mar 24 12:34:55 PM PDT 24 Mar 24 12:34:57 PM PDT 24 48277941 ps
T1211 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3200573002 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:05 PM PDT 24 98051282 ps
T1212 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.4041918285 Mar 24 12:34:43 PM PDT 24 Mar 24 12:34:46 PM PDT 24 2118518023 ps
T1213 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2227784686 Mar 24 12:34:50 PM PDT 24 Mar 24 12:34:53 PM PDT 24 138444041 ps
T1214 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2890366913 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:50 PM PDT 24 184423485 ps
T1215 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1478809200 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:04 PM PDT 24 40918207 ps
T1216 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2641036261 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:02 PM PDT 24 24110210 ps
T1217 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.334997403 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:04 PM PDT 24 263625732 ps
T1218 /workspace/coverage/cover_reg_top/45.kmac_intr_test.3448206728 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:12 PM PDT 24 35982060 ps
T1219 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3609772360 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:47 PM PDT 24 404559294 ps
T1220 /workspace/coverage/cover_reg_top/7.kmac_intr_test.3038227777 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:54 PM PDT 24 24326601 ps
T1221 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1764601282 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:25 PM PDT 24 97579092 ps
T1222 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.2268979640 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:13 PM PDT 24 212561733 ps
T1223 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.817738998 Mar 24 12:34:42 PM PDT 24 Mar 24 12:34:44 PM PDT 24 42149594 ps
T1224 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.720492006 Mar 24 12:34:38 PM PDT 24 Mar 24 12:34:40 PM PDT 24 195280310 ps
T1225 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.810656835 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:49 PM PDT 24 96791404 ps
T1226 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3381563508 Mar 24 12:34:56 PM PDT 24 Mar 24 12:35:00 PM PDT 24 386391932 ps
T1227 /workspace/coverage/cover_reg_top/12.kmac_intr_test.2613409054 Mar 24 12:34:57 PM PDT 24 Mar 24 12:34:59 PM PDT 24 12679210 ps
T1228 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2438539123 Mar 24 12:34:42 PM PDT 24 Mar 24 12:34:44 PM PDT 24 161190961 ps
T1229 /workspace/coverage/cover_reg_top/47.kmac_intr_test.1697570490 Mar 24 12:35:19 PM PDT 24 Mar 24 12:35:20 PM PDT 24 10825357 ps
T1230 /workspace/coverage/cover_reg_top/42.kmac_intr_test.4123412140 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:55 PM PDT 24 47958049 ps
T1231 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2387795053 Mar 24 12:35:02 PM PDT 24 Mar 24 12:35:04 PM PDT 24 197554764 ps
T1232 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1463934157 Mar 24 12:35:27 PM PDT 24 Mar 24 12:35:29 PM PDT 24 73350442 ps
T1233 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2830483378 Mar 24 12:34:56 PM PDT 24 Mar 24 12:35:00 PM PDT 24 50297984 ps
T1234 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.556984669 Mar 24 12:35:31 PM PDT 24 Mar 24 12:35:33 PM PDT 24 58361409 ps
T1235 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3781441348 Mar 24 12:34:56 PM PDT 24 Mar 24 12:34:59 PM PDT 24 615289693 ps
T1236 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2994885320 Mar 24 12:34:54 PM PDT 24 Mar 24 12:34:58 PM PDT 24 89843355 ps
T1237 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3788552751 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:06 PM PDT 24 160829124 ps
T1238 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2641721199 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:01 PM PDT 24 152950603 ps
T1239 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1262686897 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:04 PM PDT 24 157978598 ps
T1240 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3412921482 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:15 PM PDT 24 1585335717 ps
T1241 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.347020465 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:02 PM PDT 24 42519760 ps

Test location /workspace/coverage/default/41.kmac_lc_escalation.95473677
Short name T4
Test name
Test status
Simulation time 529447674 ps
CPU time 10.52 seconds
Started Mar 24 01:32:22 PM PDT 24
Finished Mar 24 01:32:32 PM PDT 24
Peak memory 224456 kb
Host smart-6f0026c7-126c-4212-bbc2-02af7341e4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95473677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.95473677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1842720984
Short name T30
Test name
Test status
Simulation time 10373256071 ps
CPU time 169.89 seconds
Started Mar 24 01:25:54 PM PDT 24
Finished Mar 24 01:28:44 PM PDT 24
Peak memory 236272 kb
Host smart-baa1ce8a-a0ec-4197-a442-b2d04a8c78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842720984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1842720984 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2719265260
Short name T135
Test name
Test status
Simulation time 77657426 ps
CPU time 2.38 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:50 PM PDT 24
Peak memory 214972 kb
Host smart-636b768e-8681-420a-8850-eafbedf7dbe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719265260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.27192
65260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/42.kmac_stress_all_with_rand_reset.1939181154
Short name T145
Test name
Test status
Simulation time 41384047335 ps
CPU time 282.76 seconds
Started Mar 24 01:32:39 PM PDT 24
Finished Mar 24 01:37:22 PM PDT 24
Peak memory 249252 kb
Host smart-d7c773b9-51fd-4135-ae31-9214fee76efb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939181154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all_with_rand_reset.1939181154 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.kmac_burst_write.3919859618
Short name T45
Test name
Test status
Simulation time 26281874658 ps
CPU time 525.36 seconds
Started Mar 24 01:30:50 PM PDT 24
Finished Mar 24 01:39:35 PM PDT 24
Peak memory 232816 kb
Host smart-ed822cdb-23ec-436e-8848-95bc85129cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919859618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3919859618 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.68757333
Short name T105
Test name
Test status
Simulation time 100407460 ps
CPU time 1.42 seconds
Started Mar 24 01:26:58 PM PDT 24
Finished Mar 24 01:26:59 PM PDT 24
Peak memory 220508 kb
Host smart-984a4ef7-6dd9-4622-bb87-27801f318055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68757333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.68757333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.3251215412
Short name T103
Test name
Test status
Simulation time 105825455 ps
CPU time 1.14 seconds
Started Mar 24 01:29:19 PM PDT 24
Finished Mar 24 01:29:20 PM PDT 24
Peak memory 216068 kb
Host smart-74e3f28a-ad53-457d-b313-2fb2a738d2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251215412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3251215412 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_error.2397064399
Short name T35
Test name
Test status
Simulation time 153297619833 ps
CPU time 209.95 seconds
Started Mar 24 01:31:45 PM PDT 24
Finished Mar 24 01:35:16 PM PDT 24
Peak memory 249096 kb
Host smart-6918a626-9997-4166-81da-00a8d065981c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397064399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2397064399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.2767316205
Short name T24
Test name
Test status
Simulation time 178223320 ps
CPU time 1.69 seconds
Started Mar 24 01:27:26 PM PDT 24
Finished Mar 24 01:27:28 PM PDT 24
Peak memory 207336 kb
Host smart-74036fbe-9cf6-4ee1-8f72-ae152b5c13c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767316205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2767316205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.1001740029
Short name T57
Test name
Test status
Simulation time 1209592820 ps
CPU time 27.94 seconds
Started Mar 24 01:25:53 PM PDT 24
Finished Mar 24 01:26:21 PM PDT 24
Peak memory 232676 kb
Host smart-de308b62-968b-443d-a4ca-a5b5966f12e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001740029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1001740029 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.566957089
Short name T112
Test name
Test status
Simulation time 125000390 ps
CPU time 2.68 seconds
Started Mar 24 12:35:08 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 215376 kb
Host smart-164c454d-8350-4bf3-94d1-9c672d99de95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566957089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac
_shadow_reg_errors_with_csr_rw.566957089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.1415079900
Short name T10
Test name
Test status
Simulation time 19668983906 ps
CPU time 58.99 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:26:10 PM PDT 24
Peak memory 247320 kb
Host smart-fbf9aacc-85eb-43bb-bed1-b7049da272af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415079900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1415079900 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1544397070
Short name T1089
Test name
Test status
Simulation time 42260073 ps
CPU time 0.8 seconds
Started Mar 24 12:34:37 PM PDT 24
Finished Mar 24 12:34:39 PM PDT 24
Peak memory 206688 kb
Host smart-ffdbf1e1-24ae-47dc-b34c-041276f37853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544397070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1544397070 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/default/35.kmac_stress_all.4046171415
Short name T80
Test name
Test status
Simulation time 47665043933 ps
CPU time 743.36 seconds
Started Mar 24 01:30:44 PM PDT 24
Finished Mar 24 01:43:07 PM PDT 24
Peak memory 332936 kb
Host smart-52005c5c-52b7-43f2-9018-7fccd3b2850c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4046171415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.4046171415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.1468388617
Short name T529
Test name
Test status
Simulation time 54938828 ps
CPU time 1.2 seconds
Started Mar 24 01:28:10 PM PDT 24
Finished Mar 24 01:28:11 PM PDT 24
Peak memory 216120 kb
Host smart-1f5364f0-0a50-4fce-8560-60c94837b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468388617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1468388617 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.3866882080
Short name T48
Test name
Test status
Simulation time 132853640545 ps
CPU time 963.32 seconds
Started Mar 24 01:30:05 PM PDT 24
Finished Mar 24 01:46:09 PM PDT 24
Peak memory 297688 kb
Host smart-5296db3f-e6be-4631-afc4-109fa24b11a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3866882080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3866882080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2203294941
Short name T110
Test name
Test status
Simulation time 40977936 ps
CPU time 1.13 seconds
Started Mar 24 12:34:46 PM PDT 24
Finished Mar 24 12:34:48 PM PDT 24
Peak memory 215480 kb
Host smart-fbbe0851-c9cc-4130-a5e5-3b80a00d8d3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203294941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.2203294941 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.kmac_alert_test.1455987380
Short name T224
Test name
Test status
Simulation time 33307328 ps
CPU time 0.76 seconds
Started Mar 24 01:27:08 PM PDT 24
Finished Mar 24 01:27:09 PM PDT 24
Peak memory 205700 kb
Host smart-133d9b6a-0229-4174-ac9b-d2553bca1d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455987380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1455987380 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.845718431
Short name T96
Test name
Test status
Simulation time 902721209924 ps
CPU time 4310.66 seconds
Started Mar 24 01:27:46 PM PDT 24
Finished Mar 24 02:39:37 PM PDT 24
Peak memory 561200 kb
Host smart-bcb23db6-89da-47a7-97a1-7d4f056ac00a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=845718431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.845718431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.32024728
Short name T160
Test name
Test status
Simulation time 238501615 ps
CPU time 1.33 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 214924 kb
Host smart-732f81c5-2c65-4128-bde9-f773816e3cb1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32024728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_
access.32024728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.911188436
Short name T204
Test name
Test status
Simulation time 125368096 ps
CPU time 4.08 seconds
Started Mar 24 12:35:08 PM PDT 24
Finished Mar 24 12:35:13 PM PDT 24
Peak memory 215008 kb
Host smart-9729336f-c76c-489c-af6e-f7eae1e132ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911188436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.91118
8436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/21.kmac_error.2712935130
Short name T150
Test name
Test status
Simulation time 17991167210 ps
CPU time 292.24 seconds
Started Mar 24 01:27:46 PM PDT 24
Finished Mar 24 01:32:39 PM PDT 24
Peak memory 257268 kb
Host smart-9f174ba9-a5cc-4313-b71d-cde4d0ba2778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712935130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2712935130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2699367554
Short name T109
Test name
Test status
Simulation time 109380749 ps
CPU time 1.31 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:55 PM PDT 24
Peak memory 215356 kb
Host smart-8eb900cf-9e37-44b1-af65-a73a2e54e12d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699367554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2699367554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.127653817
Short name T138
Test name
Test status
Simulation time 13535724 ps
CPU time 0.75 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 206572 kb
Host smart-acb64468-fee7-44cc-85e7-521e23676090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127653817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.127653817 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.4025056885
Short name T188
Test name
Test status
Simulation time 2709683643 ps
CPU time 18.71 seconds
Started Mar 24 01:25:15 PM PDT 24
Finished Mar 24 01:25:33 PM PDT 24
Peak memory 217500 kb
Host smart-f1c966c5-a850-440d-b15d-d639297df54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025056885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.4025056885 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.144788230
Short name T206
Test name
Test status
Simulation time 240839352 ps
CPU time 4.49 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 214996 kb
Host smart-c83ac76b-ec81-4183-b308-dae3e9c633f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144788230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.14478
8230 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.1783412943
Short name T185
Test name
Test status
Simulation time 495639370253 ps
CPU time 5152.11 seconds
Started Mar 24 01:26:57 PM PDT 24
Finished Mar 24 02:52:50 PM PDT 24
Peak memory 654788 kb
Host smart-84110bc0-efe8-41dc-8dec-e9099a13c072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1783412943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1783412943 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_stress_all.1730575787
Short name T82
Test name
Test status
Simulation time 43111233553 ps
CPU time 921.5 seconds
Started Mar 24 01:26:40 PM PDT 24
Finished Mar 24 01:42:02 PM PDT 24
Peak memory 355828 kb
Host smart-2001ba6b-674a-4f75-a0b1-00707f78c324
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1730575787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1730575787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.4220760269
Short name T16
Test name
Test status
Simulation time 191047031624 ps
CPU time 1371.39 seconds
Started Mar 24 01:28:16 PM PDT 24
Finished Mar 24 01:51:07 PM PDT 24
Peak memory 340516 kb
Host smart-1a28fcfb-d9ea-4785-8f77-fce80e9bc637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4220760269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.4220760269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3544481980
Short name T163
Test name
Test status
Simulation time 291673859 ps
CPU time 5.13 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:17 PM PDT 24
Peak memory 207096 kb
Host smart-93cd8e65-f233-480d-969a-836dbe560669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544481980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.35444
81980 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.362268497
Short name T1137
Test name
Test status
Simulation time 16140584 ps
CPU time 0.79 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 206572 kb
Host smart-b3bff25b-a6e7-42b3-98a9-050739efd200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362268497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.362268497 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.3842014170
Short name T186
Test name
Test status
Simulation time 178988200584 ps
CPU time 4840.29 seconds
Started Mar 24 01:27:12 PM PDT 24
Finished Mar 24 02:47:53 PM PDT 24
Peak memory 650076 kb
Host smart-7ebe519b-8ea7-4d78-911e-124900eb97b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3842014170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.3842014170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.2217524859
Short name T184
Test name
Test status
Simulation time 1970086123712 ps
CPU time 4586.7 seconds
Started Mar 24 01:28:24 PM PDT 24
Finished Mar 24 02:44:51 PM PDT 24
Peak memory 562260 kb
Host smart-2891c7e9-cb8e-4410-a5f8-5dc9fe63c1ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2217524859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.2217524859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_sideload.2851089942
Short name T254
Test name
Test status
Simulation time 12618234518 ps
CPU time 245.31 seconds
Started Mar 24 01:29:42 PM PDT 24
Finished Mar 24 01:33:48 PM PDT 24
Peak memory 239608 kb
Host smart-00ecb667-b5bf-4152-9f3a-5ce2c049e27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851089942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2851089942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_stress_all.3056337662
Short name T51
Test name
Test status
Simulation time 7186310508 ps
CPU time 338.77 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:30:50 PM PDT 24
Peak memory 274412 kb
Host smart-8c97f8b2-a76f-4ebd-abad-fb590c3926ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3056337662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3056337662 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3412921482
Short name T1240
Test name
Test status
Simulation time 1585335717 ps
CPU time 9.8 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 206780 kb
Host smart-ba24916f-4590-4379-b057-99840c7587c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412921482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3412921
482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2963788206
Short name T1114
Test name
Test status
Simulation time 1433366396 ps
CPU time 8.41 seconds
Started Mar 24 12:34:51 PM PDT 24
Finished Mar 24 12:34:59 PM PDT 24
Peak memory 206828 kb
Host smart-b13f34e3-1cef-47c2-a4d1-fd65298404b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963788206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2963788
206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2324402747
Short name T1106
Test name
Test status
Simulation time 20612132 ps
CPU time 1.05 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 206832 kb
Host smart-971f44e7-d2a3-4278-baad-13f41d6a0390
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324402747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2324402
747 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3367364440
Short name T1169
Test name
Test status
Simulation time 69562996 ps
CPU time 1.55 seconds
Started Mar 24 12:34:49 PM PDT 24
Finished Mar 24 12:34:51 PM PDT 24
Peak memory 223260 kb
Host smart-2271a79e-fb45-42a1-a989-bcc07bcd036a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367364440 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3367364440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.1525846585
Short name T1129
Test name
Test status
Simulation time 109844303 ps
CPU time 1.12 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 206804 kb
Host smart-26b10ecd-e2e4-4074-bd2d-02f17728a987
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525846585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1525846585 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2889185180
Short name T1153
Test name
Test status
Simulation time 47547340 ps
CPU time 0.71 seconds
Started Mar 24 12:34:39 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 206608 kb
Host smart-db20fe14-cb1c-4cf4-92ff-e1973716afa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889185180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2889185180 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1904637572
Short name T1097
Test name
Test status
Simulation time 11509030 ps
CPU time 0.72 seconds
Started Mar 24 12:34:45 PM PDT 24
Finished Mar 24 12:34:46 PM PDT 24
Peak memory 206624 kb
Host smart-0c8d1f48-7e2b-4e46-b685-a5b4e7a31e9f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904637572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1904637572
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3181496584
Short name T1111
Test name
Test status
Simulation time 370575454 ps
CPU time 2.46 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 215092 kb
Host smart-e1aaf1ce-81d5-4081-9509-59349611a5b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181496584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.3181496584 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3381563508
Short name T1226
Test name
Test status
Simulation time 386391932 ps
CPU time 2.58 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:35:00 PM PDT 24
Peak memory 223312 kb
Host smart-5fe77595-4ded-459d-a5cf-df50b82fd2a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381563508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.3381563508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1042374996
Short name T1195
Test name
Test status
Simulation time 43656432 ps
CPU time 1.36 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:49 PM PDT 24
Peak memory 215112 kb
Host smart-65d0f63b-06ea-4f79-9eb8-99ef4c5108c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042374996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1042374996 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3242470912
Short name T1142
Test name
Test status
Simulation time 2083275771 ps
CPU time 10.05 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:14 PM PDT 24
Peak memory 206812 kb
Host smart-90e0f094-9013-4b3c-925a-129b272843b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242470912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3242470
912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.18983305
Short name T1091
Test name
Test status
Simulation time 2887608657 ps
CPU time 8.66 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:11 PM PDT 24
Peak memory 206868 kb
Host smart-3dff8d5a-f7aa-4fa0-92ac-e44f4f449585
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18983305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.18983305
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2701686080
Short name T1162
Test name
Test status
Simulation time 55901627 ps
CPU time 0.92 seconds
Started Mar 24 12:34:55 PM PDT 24
Finished Mar 24 12:34:57 PM PDT 24
Peak memory 206604 kb
Host smart-cb8af29a-8a2b-4c20-be35-acbff6898228
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701686080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2701686
080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.347020465
Short name T1241
Test name
Test status
Simulation time 42519760 ps
CPU time 1.54 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 223268 kb
Host smart-c52146b1-849f-4cdb-8f9d-bb131c8cb1f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347020465 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.347020465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2693990758
Short name T1150
Test name
Test status
Simulation time 30931891 ps
CPU time 1.13 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 206792 kb
Host smart-005a1fa2-ce85-4a4e-a2be-03702c3eb603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693990758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2693990758 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.3918829021
Short name T1183
Test name
Test status
Simulation time 45501613 ps
CPU time 0.73 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:49 PM PDT 24
Peak memory 206568 kb
Host smart-ef4db618-872d-4c85-96f9-29902cea09c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918829021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3918829021 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3137453233
Short name T159
Test name
Test status
Simulation time 25321784 ps
CPU time 1.08 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:57 PM PDT 24
Peak memory 214952 kb
Host smart-eee0781c-5fc6-4084-b46a-0196e3d52887
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137453233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.3137453233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3921513496
Short name T1087
Test name
Test status
Simulation time 43093419 ps
CPU time 0.76 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206684 kb
Host smart-36d66776-6e3e-447c-8afc-12365170dff9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921513496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3921513496
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1645121543
Short name T1083
Test name
Test status
Simulation time 52094534 ps
CPU time 1.53 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 214980 kb
Host smart-eb2936bb-0186-44c1-aab5-9afa423ef23d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645121543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.1645121543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3683972171
Short name T116
Test name
Test status
Simulation time 30646833 ps
CPU time 0.94 seconds
Started Mar 24 12:34:55 PM PDT 24
Finished Mar 24 12:34:57 PM PDT 24
Peak memory 206620 kb
Host smart-f7e1c585-9bd9-449a-b8c7-9a0b55c780e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683972171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.3683972171 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.94756787
Short name T1167
Test name
Test status
Simulation time 62778799 ps
CPU time 1.96 seconds
Started Mar 24 12:34:38 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 215352 kb
Host smart-5cddebf5-8ed1-47c6-a54f-3ec3ec6d9652
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94756787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_s
hadow_reg_errors_with_csr_rw.94756787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.2268979640
Short name T1222
Test name
Test status
Simulation time 212561733 ps
CPU time 2.33 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:13 PM PDT 24
Peak memory 218680 kb
Host smart-674f490f-004f-4c62-af59-5f68ee6f2564
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268979640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2268979640 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2359842039
Short name T205
Test name
Test status
Simulation time 736322101 ps
CPU time 4.83 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 215048 kb
Host smart-470aa253-2282-4144-b7fb-425a7ed88e52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359842039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.23598
42039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.534084858
Short name T147
Test name
Test status
Simulation time 191185152 ps
CPU time 1.7 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:56 PM PDT 24
Peak memory 215116 kb
Host smart-909f87f8-4a1f-49b6-a28f-21176fb0596e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534084858 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.534084858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1725938692
Short name T1104
Test name
Test status
Simulation time 52213291 ps
CPU time 1.11 seconds
Started Mar 24 12:34:46 PM PDT 24
Finished Mar 24 12:34:47 PM PDT 24
Peak memory 206800 kb
Host smart-16fbb1d0-c744-4172-808b-22a7379314c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725938692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1725938692 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.2690274252
Short name T1151
Test name
Test status
Simulation time 33621948 ps
CPU time 0.73 seconds
Started Mar 24 12:35:12 PM PDT 24
Finished Mar 24 12:35:13 PM PDT 24
Peak memory 206524 kb
Host smart-21e63405-feae-4f77-aebc-380b860d3fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690274252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2690274252 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3174462356
Short name T1098
Test name
Test status
Simulation time 90854090 ps
CPU time 2.4 seconds
Started Mar 24 12:34:52 PM PDT 24
Finished Mar 24 12:34:55 PM PDT 24
Peak memory 215016 kb
Host smart-d80457f5-7fd5-4602-91ed-3386a8c7cb48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174462356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3174462356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2279710333
Short name T1209
Test name
Test status
Simulation time 38905202 ps
CPU time 1.06 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:00 PM PDT 24
Peak memory 215428 kb
Host smart-02461e29-6adf-4073-a01d-59070c562fcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279710333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.2279710333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2994885320
Short name T1236
Test name
Test status
Simulation time 89843355 ps
CPU time 1.56 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 215088 kb
Host smart-0a01ba9d-99fa-4397-8556-b5f0a4333f5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994885320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.2994885320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3256602828
Short name T1134
Test name
Test status
Simulation time 43654306 ps
CPU time 2.86 seconds
Started Mar 24 12:35:02 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 215044 kb
Host smart-295286b2-cdc7-4537-8f2b-792cd44486fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256602828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3256602828 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3035975539
Short name T165
Test name
Test status
Simulation time 1672224610 ps
CPU time 3.38 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:59 PM PDT 24
Peak memory 206832 kb
Host smart-df8a98b4-ae44-40be-b113-8fa25a9df15e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035975539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3035
975539 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.839819359
Short name T1101
Test name
Test status
Simulation time 273318224 ps
CPU time 2.33 seconds
Started Mar 24 12:35:09 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 223644 kb
Host smart-91aa3798-5cce-44b7-abc5-848b72241e06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839819359 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.839819359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3738516594
Short name T1176
Test name
Test status
Simulation time 28602411 ps
CPU time 1.02 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 206804 kb
Host smart-10c342e5-ec73-48c1-85b3-38361aac408c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738516594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3738516594 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.965280561
Short name T139
Test name
Test status
Simulation time 15437636 ps
CPU time 0.79 seconds
Started Mar 24 12:35:02 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 206628 kb
Host smart-b08688c9-7454-4fed-ba35-53d55a8175cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965280561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.965280561 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3003637424
Short name T1179
Test name
Test status
Simulation time 68633516 ps
CPU time 1.67 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:23 PM PDT 24
Peak memory 214972 kb
Host smart-cbf4090e-aab1-4347-927a-8d8a157d64c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003637424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.3003637424 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2086733898
Short name T141
Test name
Test status
Simulation time 79195524 ps
CPU time 1.03 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:48 PM PDT 24
Peak memory 215432 kb
Host smart-2be377d1-b6f7-43c9-8b72-e71743ce5d05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086733898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.2086733898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2551344087
Short name T115
Test name
Test status
Simulation time 49969766 ps
CPU time 1.84 seconds
Started Mar 24 12:35:07 PM PDT 24
Finished Mar 24 12:35:11 PM PDT 24
Peak memory 223360 kb
Host smart-08461ef8-6e2b-4971-988e-9154ed312077
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551344087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.2551344087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.904196449
Short name T1138
Test name
Test status
Simulation time 106106441 ps
CPU time 1.91 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:49 PM PDT 24
Peak memory 217036 kb
Host smart-eb25ea9d-3ee7-4ef6-9d54-9f04f53d73b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904196449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.904196449 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2603394216
Short name T1160
Test name
Test status
Simulation time 435627556 ps
CPU time 2.77 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:13 PM PDT 24
Peak memory 215408 kb
Host smart-b25822b8-9d96-4001-b1dc-5d160b6a3d95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603394216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2603
394216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2999816692
Short name T1131
Test name
Test status
Simulation time 45204272 ps
CPU time 1.59 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 223268 kb
Host smart-c75db968-a0e5-48ac-96c6-b518b9cad4f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999816692 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2999816692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3739632497
Short name T1198
Test name
Test status
Simulation time 29085234 ps
CPU time 1.13 seconds
Started Mar 24 12:34:50 PM PDT 24
Finished Mar 24 12:34:51 PM PDT 24
Peak memory 206772 kb
Host smart-b4fcc722-5c8a-4842-85ae-0a46af50c03b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739632497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3739632497 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.2613409054
Short name T1227
Test name
Test status
Simulation time 12679210 ps
CPU time 0.77 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:34:59 PM PDT 24
Peak memory 206552 kb
Host smart-b2a8c6ca-0d25-48ae-be99-fa9f60609d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613409054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2613409054 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3878254953
Short name T181
Test name
Test status
Simulation time 111481547 ps
CPU time 2.36 seconds
Started Mar 24 12:34:59 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 214980 kb
Host smart-afb40f63-854c-4889-a78a-d088e800538c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878254953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3878254953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1086475643
Short name T1202
Test name
Test status
Simulation time 86977701 ps
CPU time 1.09 seconds
Started Mar 24 12:35:07 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 215412 kb
Host smart-451b95ff-6887-4228-ba4e-67ba8ad440b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086475643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.1086475643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3839889716
Short name T134
Test name
Test status
Simulation time 83549963 ps
CPU time 1.99 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:56 PM PDT 24
Peak memory 215384 kb
Host smart-d6d0bacd-5302-4cd9-935d-49e721dcdd9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839889716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.3839889716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.131786393
Short name T1208
Test name
Test status
Simulation time 164951009 ps
CPU time 2.9 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 215020 kb
Host smart-4c4ede25-acad-4a79-ab98-3190607212de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131786393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.131786393 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2092192448
Short name T208
Test name
Test status
Simulation time 98411053 ps
CPU time 3.97 seconds
Started Mar 24 12:34:39 PM PDT 24
Finished Mar 24 12:34:43 PM PDT 24
Peak memory 215000 kb
Host smart-9e993da7-df9e-467a-abee-d5f120d36f44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092192448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2092
192448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3106869243
Short name T148
Test name
Test status
Simulation time 247269796 ps
CPU time 2.28 seconds
Started Mar 24 12:35:09 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 223232 kb
Host smart-3ce4f40f-7b1e-4ded-bceb-72b99292b515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106869243 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3106869243 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2279895944
Short name T1149
Test name
Test status
Simulation time 31869187 ps
CPU time 1.14 seconds
Started Mar 24 12:35:13 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 206804 kb
Host smart-e23b7aca-98f4-4009-93bf-0cde1fa8a625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279895944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2279895944 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.556984669
Short name T1234
Test name
Test status
Simulation time 58361409 ps
CPU time 1.67 seconds
Started Mar 24 12:35:31 PM PDT 24
Finished Mar 24 12:35:33 PM PDT 24
Peak memory 215024 kb
Host smart-32baea45-8a3f-46d8-ba3f-21e63e1b71a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556984669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr
_outstanding.556984669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1565526675
Short name T211
Test name
Test status
Simulation time 305763183 ps
CPU time 1.03 seconds
Started Mar 24 12:35:07 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 207236 kb
Host smart-f21d4764-1f7e-4fc0-9d00-ac93efbd6403
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565526675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.1565526675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2830483378
Short name T1233
Test name
Test status
Simulation time 50297984 ps
CPU time 2.41 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:35:00 PM PDT 24
Peak memory 215396 kb
Host smart-d60d1aad-5f9c-412e-97a1-a1e5c082014d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830483378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.2830483378 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3327624521
Short name T1190
Test name
Test status
Simulation time 373091403 ps
CPU time 2.51 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:51 PM PDT 24
Peak memory 214984 kb
Host smart-2d0bbc1c-484e-4896-96e4-dd10902214a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327624521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3327624521 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2718702826
Short name T1156
Test name
Test status
Simulation time 36699553 ps
CPU time 2.25 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:06 PM PDT 24
Peak memory 215136 kb
Host smart-6f2dfadc-76d7-4ff5-a3d8-4e40cc598911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718702826 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2718702826 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1709315960
Short name T1132
Test name
Test status
Simulation time 42934914 ps
CPU time 0.92 seconds
Started Mar 24 12:35:13 PM PDT 24
Finished Mar 24 12:35:14 PM PDT 24
Peak memory 214804 kb
Host smart-3e251776-4d1b-4221-8de8-96becac1f3ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709315960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1709315960 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2102953053
Short name T1125
Test name
Test status
Simulation time 369459955 ps
CPU time 2.39 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:57 PM PDT 24
Peak memory 215044 kb
Host smart-ceb1d876-86fe-42e4-9396-27afd1ca9b81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102953053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.2102953053 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1463934157
Short name T1232
Test name
Test status
Simulation time 73350442 ps
CPU time 1.32 seconds
Started Mar 24 12:35:27 PM PDT 24
Finished Mar 24 12:35:29 PM PDT 24
Peak memory 215372 kb
Host smart-1be0dab1-aa95-4916-9cea-20a5e205f658
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463934157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.1463934157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1200290073
Short name T1193
Test name
Test status
Simulation time 82085755 ps
CPU time 1.56 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 222532 kb
Host smart-55557206-8d41-4f25-a7ac-65536677f7f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200290073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.1200290073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.984106654
Short name T1157
Test name
Test status
Simulation time 61089083 ps
CPU time 1.76 seconds
Started Mar 24 12:34:42 PM PDT 24
Finished Mar 24 12:34:44 PM PDT 24
Peak memory 215016 kb
Host smart-15015f13-993b-4870-b3f1-62f197e1d7b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984106654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.984106654 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.288930143
Short name T202
Test name
Test status
Simulation time 56597334 ps
CPU time 2.27 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:08 PM PDT 24
Peak memory 214948 kb
Host smart-eb5304d8-f993-4e49-b32f-c64adb47bb83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288930143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.28893
0143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.582228598
Short name T1184
Test name
Test status
Simulation time 80834473 ps
CPU time 1.42 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:00 PM PDT 24
Peak memory 223244 kb
Host smart-f39ad6cb-268f-454e-b985-82b70e4ef3bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582228598 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.582228598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3257760701
Short name T1188
Test name
Test status
Simulation time 12970430 ps
CPU time 0.87 seconds
Started Mar 24 12:35:19 PM PDT 24
Finished Mar 24 12:35:20 PM PDT 24
Peak memory 206604 kb
Host smart-028d9675-c7bd-411c-beac-8e2488e3819f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257760701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3257760701 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.116258956
Short name T195
Test name
Test status
Simulation time 20435116 ps
CPU time 0.79 seconds
Started Mar 24 12:34:45 PM PDT 24
Finished Mar 24 12:34:46 PM PDT 24
Peak memory 206556 kb
Host smart-3a441982-a4f8-4424-993f-0f99da0a2c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116258956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.116258956 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1310547949
Short name T1205
Test name
Test status
Simulation time 95693679 ps
CPU time 2.36 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:08 PM PDT 24
Peak memory 215168 kb
Host smart-e6182111-5d91-4855-b085-b9bccde3c5dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310547949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1310547949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.337178961
Short name T1197
Test name
Test status
Simulation time 25954429 ps
CPU time 1.03 seconds
Started Mar 24 12:35:13 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 215472 kb
Host smart-a7893f49-b371-4987-b5c7-a5dd3c44e192
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337178961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_
errors.337178961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.810656835
Short name T1225
Test name
Test status
Simulation time 96791404 ps
CPU time 2.62 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:49 PM PDT 24
Peak memory 215084 kb
Host smart-4d00f35e-8b47-409c-946f-d7a0a2f3e894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810656835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.810656835 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3421409031
Short name T136
Test name
Test status
Simulation time 179401503 ps
CPU time 3.92 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 206884 kb
Host smart-adc44cf3-f91c-4142-9cec-a4572cd5f863
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421409031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3421
409031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.590337307
Short name T1178
Test name
Test status
Simulation time 336063103 ps
CPU time 1.53 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:50 PM PDT 24
Peak memory 223236 kb
Host smart-34683c48-b406-469d-be19-368ea8de50af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590337307 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.590337307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.700857381
Short name T1088
Test name
Test status
Simulation time 24892147 ps
CPU time 1.11 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 207176 kb
Host smart-a0c777e0-c68d-4bcc-86b4-be5ec36cfb3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700857381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.700857381 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.4286188032
Short name T1203
Test name
Test status
Simulation time 11628972 ps
CPU time 0.76 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 206580 kb
Host smart-40b3c700-9e4d-460a-9f17-fb3f1406ed20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286188032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.4286188032 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1495093533
Short name T1124
Test name
Test status
Simulation time 139963116 ps
CPU time 2.17 seconds
Started Mar 24 12:34:55 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 215016 kb
Host smart-8aa250d2-4890-4a40-b301-5decb436a00c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495093533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.1495093533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3796444879
Short name T1196
Test name
Test status
Simulation time 43678748 ps
CPU time 1.09 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 215424 kb
Host smart-5f5aee6c-abf2-4018-bfe6-2bc81ec81f29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796444879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.3796444879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3788552751
Short name T1237
Test name
Test status
Simulation time 160829124 ps
CPU time 2.23 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:06 PM PDT 24
Peak memory 223212 kb
Host smart-e114c20d-aa8e-4dab-b148-62a60721de55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788552751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.3788552751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.816562439
Short name T182
Test name
Test status
Simulation time 480833780 ps
CPU time 3.14 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 215048 kb
Host smart-85d46e5f-7996-45db-b1b8-820a54209e18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816562439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.816562439 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.368800714
Short name T207
Test name
Test status
Simulation time 276757646 ps
CPU time 4.71 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 214968 kb
Host smart-4ecb5981-1181-40bd-8e79-ecb6e2863881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368800714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.36880
0714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3200573002
Short name T1211
Test name
Test status
Simulation time 98051282 ps
CPU time 2.57 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 223224 kb
Host smart-c8ffd3b8-1dc4-4632-b110-e2cd46ceb781
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200573002 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.3200573002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1177316291
Short name T1154
Test name
Test status
Simulation time 50959716 ps
CPU time 0.91 seconds
Started Mar 24 12:34:43 PM PDT 24
Finished Mar 24 12:34:45 PM PDT 24
Peak memory 206988 kb
Host smart-154df7fa-229d-4b12-84a6-c72288fc628c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177316291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1177316291 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3438630361
Short name T140
Test name
Test status
Simulation time 22625000 ps
CPU time 0.76 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 206576 kb
Host smart-3d603eeb-14ac-4605-92a5-b1829b38b2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438630361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3438630361 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1399982982
Short name T1152
Test name
Test status
Simulation time 172686989 ps
CPU time 1.55 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:56 PM PDT 24
Peak memory 206816 kb
Host smart-a489e7ea-1852-4e29-af91-ec10f0033644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399982982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.1399982982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2518466044
Short name T1171
Test name
Test status
Simulation time 66387296 ps
CPU time 0.75 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 206644 kb
Host smart-447a38ca-a600-488e-8b03-e45164f8f9fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518466044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.2518466044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.861756722
Short name T133
Test name
Test status
Simulation time 939809862 ps
CPU time 1.81 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:00 PM PDT 24
Peak memory 215480 kb
Host smart-b57bd32c-580a-468e-af88-9693fe4113cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861756722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac
_shadow_reg_errors_with_csr_rw.861756722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.3640630841
Short name T1181
Test name
Test status
Simulation time 158322157 ps
CPU time 1.5 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 215056 kb
Host smart-c1263155-6d3d-469f-af06-40048cb7e19d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640630841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3640630841 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1874710987
Short name T1100
Test name
Test status
Simulation time 78675425 ps
CPU time 1.46 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 215072 kb
Host smart-4e714229-41d9-4f0e-9682-00750a1db4e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874710987 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1874710987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2389897842
Short name T1199
Test name
Test status
Simulation time 20085182 ps
CPU time 0.92 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 206584 kb
Host smart-429a3137-7fa9-40d4-b46c-037b051d7714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389897842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2389897842 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.2336318949
Short name T1136
Test name
Test status
Simulation time 37595854 ps
CPU time 0.77 seconds
Started Mar 24 12:35:18 PM PDT 24
Finished Mar 24 12:35:19 PM PDT 24
Peak memory 206572 kb
Host smart-aca66f71-1573-46ad-841c-c4455fdce260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336318949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2336318949 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1764601282
Short name T1221
Test name
Test status
Simulation time 97579092 ps
CPU time 1.52 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 215208 kb
Host smart-c5ed281e-4e3c-4900-a2b8-80c0716f4a8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764601282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.1764601282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.187535029
Short name T1141
Test name
Test status
Simulation time 123548983 ps
CPU time 1.21 seconds
Started Mar 24 12:35:07 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 215396 kb
Host smart-f18335c4-dd13-4254-b394-1171bc708e54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187535029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_
errors.187535029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2227784686
Short name T1213
Test name
Test status
Simulation time 138444041 ps
CPU time 3.1 seconds
Started Mar 24 12:34:50 PM PDT 24
Finished Mar 24 12:34:53 PM PDT 24
Peak memory 215436 kb
Host smart-4ce4f6ab-813e-4f62-8e66-04702017eb22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227784686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.2227784686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2641721199
Short name T1238
Test name
Test status
Simulation time 152950603 ps
CPU time 2.56 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 215052 kb
Host smart-52578ea0-db44-46ae-b769-082412355f59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641721199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2641721199 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3858002759
Short name T203
Test name
Test status
Simulation time 731895386 ps
CPU time 4.39 seconds
Started Mar 24 12:35:13 PM PDT 24
Finished Mar 24 12:35:19 PM PDT 24
Peak memory 206796 kb
Host smart-908caca9-d26e-4779-88f8-c5f0e70c5e03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858002759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3858
002759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3144940411
Short name T1108
Test name
Test status
Simulation time 47804277 ps
CPU time 1.53 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:55 PM PDT 24
Peak memory 223276 kb
Host smart-5c4dc778-f4fc-4cd7-b8eb-2f0c6e4c603c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144940411 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3144940411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3159081385
Short name T1118
Test name
Test status
Simulation time 19701476 ps
CPU time 0.91 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206604 kb
Host smart-7b1de015-8fb0-471e-9847-03fec42c09df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159081385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3159081385 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.2509096473
Short name T180
Test name
Test status
Simulation time 19100861 ps
CPU time 0.78 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 206540 kb
Host smart-4799ecdc-6732-4357-a30a-4cead9220b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509096473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2509096473 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.969903232
Short name T1120
Test name
Test status
Simulation time 107726397 ps
CPU time 2.43 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:08 PM PDT 24
Peak memory 215180 kb
Host smart-555d8c04-a6b6-4824-9f5c-a0e7ba5b748e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969903232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.969903232 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3235986811
Short name T1194
Test name
Test status
Simulation time 63941328 ps
CPU time 1.22 seconds
Started Mar 24 12:34:50 PM PDT 24
Finished Mar 24 12:34:51 PM PDT 24
Peak memory 215444 kb
Host smart-0e5a9781-c3d2-41b0-9103-acc982958589
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235986811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.3235986811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3742449791
Short name T1094
Test name
Test status
Simulation time 245919122 ps
CPU time 1.71 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 215456 kb
Host smart-5a54f11f-1791-4a7f-b604-1c835b3b0bd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742449791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.3742449791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.1231532143
Short name T1139
Test name
Test status
Simulation time 228892568 ps
CPU time 3.23 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 215064 kb
Host smart-1aa16da0-546b-4c52-a1fa-0278d50e1969
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231532143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1231532143 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3535022883
Short name T1122
Test name
Test status
Simulation time 1803616412 ps
CPU time 4.92 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 215016 kb
Host smart-9665603c-a61e-402f-88ab-af172e9a5692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535022883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3535
022883 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2232321895
Short name T1109
Test name
Test status
Simulation time 1997649224 ps
CPU time 9.77 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 206748 kb
Host smart-49d54eb2-6e97-4e67-96f2-ae535cde7e34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232321895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2232321
895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2881508670
Short name T1187
Test name
Test status
Simulation time 576323528 ps
CPU time 15.03 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206784 kb
Host smart-ea7b71a2-14fa-45ea-b60b-18bef37e03f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881508670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2881508
670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.4037958963
Short name T1103
Test name
Test status
Simulation time 22791679 ps
CPU time 0.91 seconds
Started Mar 24 12:34:38 PM PDT 24
Finished Mar 24 12:34:39 PM PDT 24
Peak memory 206616 kb
Host smart-89ac63b8-8874-4951-8942-12d1fb73e7e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037958963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.4037958
963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2538446439
Short name T1121
Test name
Test status
Simulation time 33309672 ps
CPU time 1.36 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 215112 kb
Host smart-8c956035-7033-4668-a0d2-712241cb1a84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538446439 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2538446439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.874383924
Short name T1161
Test name
Test status
Simulation time 33847939 ps
CPU time 0.91 seconds
Started Mar 24 12:34:59 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206584 kb
Host smart-cc329945-df55-441d-b306-36827b14cf06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874383924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.874383924 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.2541067200
Short name T1145
Test name
Test status
Simulation time 33152442 ps
CPU time 0.75 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 206572 kb
Host smart-565268ec-a14b-4c54-8610-08c34075840f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541067200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2541067200 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.88927527
Short name T158
Test name
Test status
Simulation time 20512419 ps
CPU time 1.29 seconds
Started Mar 24 12:34:40 PM PDT 24
Finished Mar 24 12:34:42 PM PDT 24
Peak memory 214988 kb
Host smart-df37d32b-8969-43a7-8756-d517fe329353
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88927527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_
access.88927527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.2934692868
Short name T1177
Test name
Test status
Simulation time 22899142 ps
CPU time 0.76 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:49 PM PDT 24
Peak memory 206588 kb
Host smart-144e722b-e8ff-4821-a817-2dbd669ba18f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934692868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2934692868
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2379780187
Short name T1085
Test name
Test status
Simulation time 138898956 ps
CPU time 2.12 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:46 PM PDT 24
Peak memory 215068 kb
Host smart-0c650512-2026-4b0a-adc3-1be354cd44f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379780187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.2379780187 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4268435714
Short name T169
Test name
Test status
Simulation time 252103817 ps
CPU time 1.96 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:50 PM PDT 24
Peak memory 222852 kb
Host smart-cb89951f-a016-467b-881f-7c43d3b211ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268435714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.4268435714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2890366913
Short name T1214
Test name
Test status
Simulation time 184423485 ps
CPU time 1.59 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:50 PM PDT 24
Peak memory 215052 kb
Host smart-375a0db4-d878-4b77-9576-802b663ba663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890366913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2890366913 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.2159829819
Short name T212
Test name
Test status
Simulation time 131422319 ps
CPU time 2.7 seconds
Started Mar 24 12:34:42 PM PDT 24
Finished Mar 24 12:34:45 PM PDT 24
Peak memory 215020 kb
Host smart-b428464e-6fc0-40dc-b2a0-21d040eb38f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159829819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.21598
29819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.3279351024
Short name T1123
Test name
Test status
Simulation time 25987618 ps
CPU time 0.72 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:45 PM PDT 24
Peak memory 206588 kb
Host smart-e9d92e20-3824-41da-ad7e-c3ea3a3425df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279351024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3279351024 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.3066366031
Short name T1113
Test name
Test status
Simulation time 15339230 ps
CPU time 0.77 seconds
Started Mar 24 12:35:12 PM PDT 24
Finished Mar 24 12:35:23 PM PDT 24
Peak memory 207044 kb
Host smart-bd53ffd2-342f-4deb-b709-780a8c6f706a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066366031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3066366031 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.2624590256
Short name T1164
Test name
Test status
Simulation time 17807371 ps
CPU time 0.76 seconds
Started Mar 24 12:35:02 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 206520 kb
Host smart-7cbdd486-0921-442a-b8cf-db1fc2159bfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624590256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2624590256 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2237290560
Short name T1117
Test name
Test status
Simulation time 48183559 ps
CPU time 0.78 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:34:57 PM PDT 24
Peak memory 206560 kb
Host smart-94be14c0-8234-46c1-a1d1-ecde44f68b82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237290560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2237290560 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.912104593
Short name T1140
Test name
Test status
Simulation time 51505299 ps
CPU time 0.73 seconds
Started Mar 24 12:34:46 PM PDT 24
Finished Mar 24 12:34:47 PM PDT 24
Peak memory 206592 kb
Host smart-583b3ef0-9560-4385-a4db-6c7b9b2005f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912104593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.912104593 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.4249524011
Short name T1182
Test name
Test status
Simulation time 59488326 ps
CPU time 0.74 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 206972 kb
Host smart-c3b9c915-a095-4586-a156-256d7e46e70a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249524011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.4249524011 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2601959072
Short name T1099
Test name
Test status
Simulation time 15291786 ps
CPU time 0.8 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:06 PM PDT 24
Peak memory 206604 kb
Host smart-87a8ce20-729e-4932-86ec-73add18978e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601959072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2601959072 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.763116305
Short name T179
Test name
Test status
Simulation time 15095842 ps
CPU time 0.8 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:00 PM PDT 24
Peak memory 206592 kb
Host smart-5fe5b629-4387-4cdf-8fac-663661528131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763116305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.763116305 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.816591235
Short name T197
Test name
Test status
Simulation time 20899051 ps
CPU time 0.77 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206568 kb
Host smart-193d00a0-554e-4fd7-90d8-dda9cad8a9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816591235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.816591235 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.1993827561
Short name T1204
Test name
Test status
Simulation time 30390087 ps
CPU time 0.79 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206592 kb
Host smart-71a824fc-0ccc-418f-94f7-23ee79315b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993827561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1993827561 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.334997403
Short name T1217
Test name
Test status
Simulation time 263625732 ps
CPU time 5.08 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 206756 kb
Host smart-e645c5e5-6d39-46a5-add7-a3331d1c67ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334997403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.33499740
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.122474908
Short name T1158
Test name
Test status
Simulation time 539509160 ps
CPU time 7.97 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:52 PM PDT 24
Peak memory 206816 kb
Host smart-8cb1f093-180f-4b51-ac1a-1519103a6336
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122474908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.12247490
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.817738998
Short name T1223
Test name
Test status
Simulation time 42149594 ps
CPU time 0.88 seconds
Started Mar 24 12:34:42 PM PDT 24
Finished Mar 24 12:34:44 PM PDT 24
Peak memory 206576 kb
Host smart-00236719-dfc2-4faa-a386-9deda45d7559
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817738998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.81773899
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1987790099
Short name T146
Test name
Test status
Simulation time 52044014 ps
CPU time 1.62 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 215128 kb
Host smart-c1a7c428-cfcc-441d-9c9b-3aa8992a851b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987790099 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1987790099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1854163265
Short name T1096
Test name
Test status
Simulation time 17142850 ps
CPU time 0.89 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 206548 kb
Host smart-04ca9989-3fb3-4f72-a926-c7fb44d49184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854163265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1854163265 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1599395918
Short name T161
Test name
Test status
Simulation time 21558581 ps
CPU time 1.4 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 215000 kb
Host smart-caf0fb57-2f98-4255-8c06-0349a93f541f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599395918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.1599395918 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2641036261
Short name T1216
Test name
Test status
Simulation time 24110210 ps
CPU time 0.7 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206572 kb
Host smart-e6787b93-e37d-4132-a18a-e5bb5d2fe12e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641036261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2641036261
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2387795053
Short name T1231
Test name
Test status
Simulation time 197554764 ps
CPU time 1.73 seconds
Started Mar 24 12:35:02 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 215064 kb
Host smart-fd65553e-ec9d-4ac0-8c4a-6d74535d102c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387795053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.2387795053 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1392540279
Short name T1201
Test name
Test status
Simulation time 38778053 ps
CPU time 0.92 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:49 PM PDT 24
Peak memory 206620 kb
Host smart-15566377-8448-45de-b225-2e3eddc3890a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392540279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.1392540279 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3342601499
Short name T1095
Test name
Test status
Simulation time 100448236 ps
CPU time 1.81 seconds
Started Mar 24 12:34:40 PM PDT 24
Finished Mar 24 12:34:42 PM PDT 24
Peak memory 215436 kb
Host smart-9a7a6dee-4388-443b-8572-8321100ff9b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342601499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.3342601499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.931291412
Short name T1173
Test name
Test status
Simulation time 186583031 ps
CPU time 1.79 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:35:00 PM PDT 24
Peak memory 215080 kb
Host smart-93d20945-e217-4cc8-a5f3-1259e0431b07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931291412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.931291412 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.600090438
Short name T1180
Test name
Test status
Simulation time 400246677 ps
CPU time 2.69 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:06 PM PDT 24
Peak memory 214992 kb
Host smart-afeec1d2-31fb-45cf-a743-c2f22d349082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600090438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.600090
438 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.4207014836
Short name T1166
Test name
Test status
Simulation time 29709929 ps
CPU time 0.73 seconds
Started Mar 24 12:34:51 PM PDT 24
Finished Mar 24 12:34:52 PM PDT 24
Peak memory 206600 kb
Host smart-89b8ba41-5a5f-400b-8dd6-a602bf55c163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207014836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.4207014836 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.3140824456
Short name T198
Test name
Test status
Simulation time 15972561 ps
CPU time 0.75 seconds
Started Mar 24 12:35:12 PM PDT 24
Finished Mar 24 12:35:13 PM PDT 24
Peak memory 206572 kb
Host smart-593b47b0-1bc1-49c1-99e7-e77f27d0086c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140824456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3140824456 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.29972364
Short name T1185
Test name
Test status
Simulation time 72399924 ps
CPU time 0.77 seconds
Started Mar 24 12:35:07 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 206608 kb
Host smart-c376e40f-5fd2-400e-b20d-273b0832e278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29972364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.29972364 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.2472087739
Short name T1119
Test name
Test status
Simulation time 14967414 ps
CPU time 0.79 seconds
Started Mar 24 12:35:07 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 206564 kb
Host smart-ba268fa7-311f-4f7a-8562-eaa713a38391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472087739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2472087739 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.1070854714
Short name T1128
Test name
Test status
Simulation time 15673368 ps
CPU time 0.76 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:18 PM PDT 24
Peak memory 206596 kb
Host smart-29052a08-1c6a-4fb3-975a-3fc2dc2c2912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070854714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1070854714 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.2284903870
Short name T1144
Test name
Test status
Simulation time 14305720 ps
CPU time 0.75 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:17 PM PDT 24
Peak memory 206556 kb
Host smart-6b8444b7-6e85-4d32-92d4-34a2328c5b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284903870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2284903870 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.609258536
Short name T1107
Test name
Test status
Simulation time 31524237 ps
CPU time 0.75 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206588 kb
Host smart-2774bd51-26e8-46e6-bbf2-45e8d5b34666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609258536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.609258536 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.3546785842
Short name T1143
Test name
Test status
Simulation time 15112536 ps
CPU time 0.8 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 206580 kb
Host smart-ddd6a64b-1a64-421d-90ad-cd2ec080be7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546785842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3546785842 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.2690558428
Short name T1168
Test name
Test status
Simulation time 14298094 ps
CPU time 0.78 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:19 PM PDT 24
Peak memory 206588 kb
Host smart-93f176ab-8fe7-4cf1-8570-6b6d2bf8de7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690558428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2690558428 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.173666044
Short name T1147
Test name
Test status
Simulation time 44210501 ps
CPU time 0.75 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 206592 kb
Host smart-6dbd6dc5-af9a-4774-b76d-bb3682212ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173666044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.173666044 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3684541436
Short name T1133
Test name
Test status
Simulation time 2374575786 ps
CPU time 5.85 seconds
Started Mar 24 12:34:50 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 206864 kb
Host smart-0246c045-ea58-4781-aa45-7b49141907d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684541436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3684541
436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.101900864
Short name T1090
Test name
Test status
Simulation time 962185835 ps
CPU time 17.7 seconds
Started Mar 24 12:34:45 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206760 kb
Host smart-45f32d68-1478-42f5-96d0-b2952ea60474
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101900864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.10190086
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.365062783
Short name T1210
Test name
Test status
Simulation time 48277941 ps
CPU time 1.16 seconds
Started Mar 24 12:34:55 PM PDT 24
Finished Mar 24 12:34:57 PM PDT 24
Peak memory 206756 kb
Host smart-94f5632a-11ea-4c10-8bf5-410d9dee400e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365062783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.36506278
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2644290348
Short name T1092
Test name
Test status
Simulation time 46469582 ps
CPU time 1.75 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:46 PM PDT 24
Peak memory 223256 kb
Host smart-2dd249cc-5649-4c1f-913c-8f86ae89a078
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644290348 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2644290348 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.2891682346
Short name T168
Test name
Test status
Simulation time 25867444 ps
CPU time 0.94 seconds
Started Mar 24 12:34:37 PM PDT 24
Finished Mar 24 12:34:39 PM PDT 24
Peak memory 206532 kb
Host smart-45b72e24-2639-4760-9621-4605131eedfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891682346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2891682346 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.2187553055
Short name T1189
Test name
Test status
Simulation time 17514629 ps
CPU time 0.81 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 206608 kb
Host smart-c71c8f0d-8d60-4d14-9830-b0eb6e66e0fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187553055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2187553055 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2147201239
Short name T162
Test name
Test status
Simulation time 142191183 ps
CPU time 1.4 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:34:59 PM PDT 24
Peak memory 214996 kb
Host smart-e225358b-a936-4a24-a252-2139554ed46b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147201239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.2147201239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1482641385
Short name T1159
Test name
Test status
Simulation time 16284171 ps
CPU time 0.75 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 206572 kb
Host smart-6780a088-a589-4456-bedd-17c5abce0151
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482641385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1482641385
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2910190653
Short name T1084
Test name
Test status
Simulation time 25955155 ps
CPU time 1.48 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 215000 kb
Host smart-d44f0b10-bf5a-4fcc-bfda-bdf54b59b3fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910190653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.2910190653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3161884535
Short name T107
Test name
Test status
Simulation time 93990149 ps
CPU time 1.14 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:49 PM PDT 24
Peak memory 215376 kb
Host smart-d1b5c5e4-7449-4457-bd8d-0b8e6c759020
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161884535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.3161884535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.79110242
Short name T113
Test name
Test status
Simulation time 99024607 ps
CPU time 1.44 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 215084 kb
Host smart-d8bb3e95-d46d-42f1-8a22-f65e05a4b525
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79110242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_s
hadow_reg_errors_with_csr_rw.79110242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3609772360
Short name T1219
Test name
Test status
Simulation time 404559294 ps
CPU time 2.86 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:47 PM PDT 24
Peak memory 215080 kb
Host smart-7b619d9e-4879-4175-8be9-18684475da82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609772360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3609772360 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.535684797
Short name T1174
Test name
Test status
Simulation time 566345179 ps
CPU time 4.06 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 214996 kb
Host smart-94cb295b-6663-4be3-897a-9fb1a07e5115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535684797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.535684
797 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.1247081332
Short name T1186
Test name
Test status
Simulation time 29896110 ps
CPU time 0.76 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 206604 kb
Host smart-72bdb87a-a1d3-4e25-b962-5f32bc21acfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247081332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1247081332 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.3782124747
Short name T1200
Test name
Test status
Simulation time 48596680 ps
CPU time 0.76 seconds
Started Mar 24 12:35:08 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 206592 kb
Host smart-0e921233-15b5-42a3-a543-46530e4ec0b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782124747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3782124747 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.4123412140
Short name T1230
Test name
Test status
Simulation time 47958049 ps
CPU time 0.73 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:55 PM PDT 24
Peak memory 206592 kb
Host smart-162e028b-e0bf-481b-8a80-b77cf5384c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123412140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.4123412140 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.1835680510
Short name T196
Test name
Test status
Simulation time 33695240 ps
CPU time 0.76 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:34:57 PM PDT 24
Peak memory 206560 kb
Host smart-18be1796-3ab3-4bd5-a7c7-2d5a2bc8762d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835680510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1835680510 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.574747278
Short name T1170
Test name
Test status
Simulation time 17988014 ps
CPU time 0.78 seconds
Started Mar 24 12:34:55 PM PDT 24
Finished Mar 24 12:34:57 PM PDT 24
Peak memory 206572 kb
Host smart-0feb14a1-0d00-4ec7-89c0-6f75fd34f56d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574747278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.574747278 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.3448206728
Short name T1218
Test name
Test status
Simulation time 35982060 ps
CPU time 0.74 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 206600 kb
Host smart-63d1d55d-963e-4990-b2cf-b58cdaf13103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448206728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3448206728 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.3918890246
Short name T1116
Test name
Test status
Simulation time 43642366 ps
CPU time 0.77 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:59 PM PDT 24
Peak memory 206548 kb
Host smart-80b80068-b86c-4778-ba31-308c126e78b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918890246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3918890246 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.1697570490
Short name T1229
Test name
Test status
Simulation time 10825357 ps
CPU time 0.75 seconds
Started Mar 24 12:35:19 PM PDT 24
Finished Mar 24 12:35:20 PM PDT 24
Peak memory 206576 kb
Host smart-c3702630-64dc-4232-b5ef-a6a94f28ac83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697570490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1697570490 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.257981545
Short name T1155
Test name
Test status
Simulation time 16716270 ps
CPU time 0.84 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 206576 kb
Host smart-13a826d2-cf9e-4d96-9633-111141d163d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257981545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.257981545 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.3170086828
Short name T1207
Test name
Test status
Simulation time 12219325 ps
CPU time 0.75 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 206596 kb
Host smart-a527545c-1f20-46a6-a648-28a704e85156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170086828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3170086828 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.48315926
Short name T1148
Test name
Test status
Simulation time 69652882 ps
CPU time 2.23 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:06 PM PDT 24
Peak memory 223232 kb
Host smart-9f925f7d-1268-4a71-a8bf-bcfc330f2a3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48315926 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.48315926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1433640634
Short name T1093
Test name
Test status
Simulation time 26576547 ps
CPU time 0.91 seconds
Started Mar 24 12:34:59 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 206560 kb
Host smart-957c2671-65de-4df2-b355-7268dbccabaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433640634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1433640634 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.1043820961
Short name T194
Test name
Test status
Simulation time 26669278 ps
CPU time 0.72 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 206604 kb
Host smart-8e40e175-41a9-4ffd-8b9c-057a9e164d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043820961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1043820961 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2376231819
Short name T1175
Test name
Test status
Simulation time 74600099 ps
CPU time 2.12 seconds
Started Mar 24 12:35:13 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 215076 kb
Host smart-e87b8864-a5c6-468a-8f2a-907f5f840459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376231819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.2376231819 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1862742163
Short name T1206
Test name
Test status
Simulation time 86552359 ps
CPU time 1.07 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:48 PM PDT 24
Peak memory 207180 kb
Host smart-9bb40908-d641-480a-a1b2-a97a5ad62611
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862742163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.1862742163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.720492006
Short name T1224
Test name
Test status
Simulation time 195280310 ps
CPU time 1.55 seconds
Started Mar 24 12:34:38 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 215124 kb
Host smart-99a14a57-1904-41cb-adf3-405c207c9b71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720492006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_
shadow_reg_errors_with_csr_rw.720492006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2438539123
Short name T1228
Test name
Test status
Simulation time 161190961 ps
CPU time 1.38 seconds
Started Mar 24 12:34:42 PM PDT 24
Finished Mar 24 12:34:44 PM PDT 24
Peak memory 215044 kb
Host smart-48b8697b-1be3-428f-8039-79562736ea59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438539123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2438539123 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.4043692044
Short name T210
Test name
Test status
Simulation time 4341143921 ps
CPU time 4.88 seconds
Started Mar 24 12:34:51 PM PDT 24
Finished Mar 24 12:34:56 PM PDT 24
Peak memory 206952 kb
Host smart-abf376ab-5173-434c-a635-adee93965cad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043692044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.40436
92044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1478809200
Short name T1215
Test name
Test status
Simulation time 40918207 ps
CPU time 1.69 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 215108 kb
Host smart-d7fd3581-7d76-446c-80c2-4347dcbec92b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478809200 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.1478809200 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.231577379
Short name T1127
Test name
Test status
Simulation time 34299987 ps
CPU time 1.09 seconds
Started Mar 24 12:34:46 PM PDT 24
Finished Mar 24 12:34:48 PM PDT 24
Peak memory 206740 kb
Host smart-5449adfa-1d21-4ab2-89f6-3f7011a4aada
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231577379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.231577379 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.2660737505
Short name T1102
Test name
Test status
Simulation time 36021404 ps
CPU time 0.77 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 206620 kb
Host smart-996984c2-702e-48df-873b-9776d6b50b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660737505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2660737505 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3643782702
Short name T1135
Test name
Test status
Simulation time 151506205 ps
CPU time 2.39 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:08 PM PDT 24
Peak memory 215096 kb
Host smart-cb939085-9201-4d8f-b8e9-4970b0d2ffa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643782702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.3643782702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1813658058
Short name T111
Test name
Test status
Simulation time 92049756 ps
CPU time 1.18 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 215780 kb
Host smart-5776b96d-7d6c-418e-a0ee-f2438515c51b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813658058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.1813658058 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1759827009
Short name T114
Test name
Test status
Simulation time 89697459 ps
CPU time 1.65 seconds
Started Mar 24 12:34:59 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 215424 kb
Host smart-7570145c-0683-45d2-9a6f-019cfcc0c130
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759827009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.1759827009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1501761333
Short name T1105
Test name
Test status
Simulation time 279758354 ps
CPU time 2.26 seconds
Started Mar 24 12:34:46 PM PDT 24
Finished Mar 24 12:34:49 PM PDT 24
Peak memory 214992 kb
Host smart-d110c8d4-5bb8-4a69-bc73-1be7c6e19222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501761333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1501761333 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1327742474
Short name T164
Test name
Test status
Simulation time 591885068 ps
CPU time 5.21 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 215032 kb
Host smart-fc508595-7a7b-4d27-b127-d808fa6e91fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327742474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.13277
42474 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.212142904
Short name T166
Test name
Test status
Simulation time 81565658 ps
CPU time 2.24 seconds
Started Mar 24 12:34:54 PM PDT 24
Finished Mar 24 12:34:56 PM PDT 24
Peak memory 215084 kb
Host smart-3a7f2352-6fe0-4c22-a9b3-85a833e9d98e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212142904 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.212142904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.4116717381
Short name T1086
Test name
Test status
Simulation time 35426507 ps
CPU time 0.87 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 206604 kb
Host smart-241270fe-018b-4ded-9ea4-9fde3dc78e76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116717381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.4116717381 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.3038227777
Short name T1220
Test name
Test status
Simulation time 24326601 ps
CPU time 0.75 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 206572 kb
Host smart-c6007b04-ccf2-466e-bcc0-2b4089ec5195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038227777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3038227777 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1037795669
Short name T1115
Test name
Test status
Simulation time 28790301 ps
CPU time 1.47 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:55 PM PDT 24
Peak memory 215048 kb
Host smart-4522cd4a-fff3-45b9-a362-257705d97c69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037795669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.1037795669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.528947707
Short name T118
Test name
Test status
Simulation time 23077049 ps
CPU time 0.84 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 206604 kb
Host smart-9cb9f79a-c9b9-4656-88cb-4a21b8879e2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528947707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_e
rrors.528947707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3878702142
Short name T117
Test name
Test status
Simulation time 104767060 ps
CPU time 2.64 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 215540 kb
Host smart-ad0d6adf-84fd-4c3c-a44f-5775ed413429
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878702142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.3878702142 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.956511927
Short name T1163
Test name
Test status
Simulation time 47974752 ps
CPU time 1.87 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 214988 kb
Host smart-676e43be-3fc1-4f10-9257-9d295321f1af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956511927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.956511927 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1835362124
Short name T209
Test name
Test status
Simulation time 121923013 ps
CPU time 2.86 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 215000 kb
Host smart-9887b384-f1d0-49bc-9885-9e19f8ec52a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835362124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.18353
62124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3292563875
Short name T1130
Test name
Test status
Simulation time 67041537 ps
CPU time 2.19 seconds
Started Mar 24 12:34:51 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 223320 kb
Host smart-035cd500-ea65-43f1-98d2-502524e93bdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292563875 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3292563875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3578507479
Short name T1110
Test name
Test status
Simulation time 75965761 ps
CPU time 0.94 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 206588 kb
Host smart-9e5469ae-e2a0-4741-b544-343ae63717cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578507479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3578507479 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.600647400
Short name T1165
Test name
Test status
Simulation time 72289433 ps
CPU time 0.82 seconds
Started Mar 24 12:35:09 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 206568 kb
Host smart-60de7619-bb5b-453d-92a7-930ea3fa3379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600647400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.600647400 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1262686897
Short name T1239
Test name
Test status
Simulation time 157978598 ps
CPU time 1.6 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 215104 kb
Host smart-a09f7577-2ef5-4296-9baf-eb77dc8538b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262686897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.1262686897 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.4130444625
Short name T1192
Test name
Test status
Simulation time 146328457 ps
CPU time 0.79 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 206636 kb
Host smart-2623d7a9-5ca1-4325-beac-f072c42826fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130444625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.4130444625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3781441348
Short name T1235
Test name
Test status
Simulation time 615289693 ps
CPU time 1.93 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:34:59 PM PDT 24
Peak memory 215392 kb
Host smart-e5b25451-ef68-4825-b363-38020b2de02b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781441348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.3781441348 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3139883647
Short name T1112
Test name
Test status
Simulation time 129066110 ps
CPU time 2.28 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:46 PM PDT 24
Peak memory 215412 kb
Host smart-e57bee0c-2331-4743-8118-534af445d878
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139883647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3139883647 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.756573971
Short name T167
Test name
Test status
Simulation time 82019864 ps
CPU time 2.32 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 223204 kb
Host smart-0288e9ad-4990-449f-8d44-6c0dcc4b9fe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756573971 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.756573971 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.215445503
Short name T1146
Test name
Test status
Simulation time 15130227 ps
CPU time 1.08 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:23 PM PDT 24
Peak memory 206752 kb
Host smart-c81d86ab-1d2c-4137-9616-fa06a3456952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215445503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.215445503 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.860567504
Short name T1172
Test name
Test status
Simulation time 48989492 ps
CPU time 0.76 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:18 PM PDT 24
Peak memory 206600 kb
Host smart-645cdcf6-d0da-4b53-9e86-b6c682b02941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860567504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.860567504 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1729957424
Short name T1126
Test name
Test status
Simulation time 79414676 ps
CPU time 2.26 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:06 PM PDT 24
Peak memory 215028 kb
Host smart-e0098559-a63b-4d05-9bf1-6f797fb30a82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729957424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.1729957424 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1114730487
Short name T1191
Test name
Test status
Simulation time 74552740 ps
CPU time 1.15 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 215412 kb
Host smart-31e75655-ae2c-4edd-b26c-a240a440a493
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114730487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.1114730487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.819935244
Short name T108
Test name
Test status
Simulation time 105540066 ps
CPU time 1.68 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:45 PM PDT 24
Peak memory 215420 kb
Host smart-598d8417-0220-43b7-9319-b168769023d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819935244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_
shadow_reg_errors_with_csr_rw.819935244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.4041918285
Short name T1212
Test name
Test status
Simulation time 2118518023 ps
CPU time 3.29 seconds
Started Mar 24 12:34:43 PM PDT 24
Finished Mar 24 12:34:46 PM PDT 24
Peak memory 217700 kb
Host smart-c312ed72-17ce-4091-80bd-97c8ec7ed465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041918285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.4041918285 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.4146532070
Short name T137
Test name
Test status
Simulation time 221651908 ps
CPU time 3.87 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 215032 kb
Host smart-9ce0ba3d-d3cd-4b67-ab41-ebc1be915896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146532070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.41465
32070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.1565551281
Short name T614
Test name
Test status
Simulation time 22173050 ps
CPU time 0.74 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:25:12 PM PDT 24
Peak memory 205664 kb
Host smart-2668aed1-05ec-4d02-ab69-5abf8072c25c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565551281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1565551281 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.4234520526
Short name T172
Test name
Test status
Simulation time 1449133237 ps
CPU time 41.88 seconds
Started Mar 24 01:25:12 PM PDT 24
Finished Mar 24 01:25:54 PM PDT 24
Peak memory 224420 kb
Host smart-7ec68a7d-2e76-452b-9feb-26d7b042b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234520526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.4234520526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.3978428452
Short name T776
Test name
Test status
Simulation time 7210228866 ps
CPU time 41.01 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:25:52 PM PDT 24
Peak memory 222532 kb
Host smart-61d82153-3ae6-4762-b5a5-edbdff243676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978428452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.3978428452 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.1460188104
Short name T15
Test name
Test status
Simulation time 24428307452 ps
CPU time 196.4 seconds
Started Mar 24 01:25:06 PM PDT 24
Finished Mar 24 01:28:23 PM PDT 24
Peak memory 224872 kb
Host smart-902c9ae3-17f2-463f-897d-fbe6511a5efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460188104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1460188104 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.1074290178
Short name T824
Test name
Test status
Simulation time 207076471 ps
CPU time 2.57 seconds
Started Mar 24 01:25:12 PM PDT 24
Finished Mar 24 01:25:15 PM PDT 24
Peak memory 224200 kb
Host smart-81da536f-fa3c-4391-bc4f-b3428c7b7184
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1074290178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1074290178 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.3383729740
Short name T582
Test name
Test status
Simulation time 302128732 ps
CPU time 21.65 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:25:33 PM PDT 24
Peak memory 224480 kb
Host smart-6dfbc76a-b8d4-4911-a7a3-b6b7f583295f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3383729740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3383729740 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.2947851286
Short name T770
Test name
Test status
Simulation time 30614016581 ps
CPU time 228.23 seconds
Started Mar 24 01:25:12 PM PDT 24
Finished Mar 24 01:29:01 PM PDT 24
Peak memory 240004 kb
Host smart-60cb6686-ccb7-4283-ae45-621d859e410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947851286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2947851286 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.1500839266
Short name T362
Test name
Test status
Simulation time 9182947096 ps
CPU time 248.91 seconds
Started Mar 24 01:25:09 PM PDT 24
Finished Mar 24 01:29:18 PM PDT 24
Peak memory 257268 kb
Host smart-5d94e1dc-316d-4fcb-ab90-a6d61c683360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500839266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1500839266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.898560784
Short name T66
Test name
Test status
Simulation time 1041848034 ps
CPU time 5.42 seconds
Started Mar 24 01:25:12 PM PDT 24
Finished Mar 24 01:25:17 PM PDT 24
Peak memory 207792 kb
Host smart-d2247cf8-b60c-4338-af24-fd5f7a4aa516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898560784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.898560784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.1331570033
Short name T717
Test name
Test status
Simulation time 33760949 ps
CPU time 1.27 seconds
Started Mar 24 01:25:12 PM PDT 24
Finished Mar 24 01:25:14 PM PDT 24
Peak memory 216140 kb
Host smart-680f060d-0249-4f51-889a-73e468a787a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331570033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1331570033 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3259557208
Short name T94
Test name
Test status
Simulation time 67561051259 ps
CPU time 1151.88 seconds
Started Mar 24 01:25:06 PM PDT 24
Finished Mar 24 01:44:18 PM PDT 24
Peak memory 343076 kb
Host smart-4386cea9-706d-456e-990e-891cc1e21b62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259557208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3259557208 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.1459466596
Short name T563
Test name
Test status
Simulation time 3687661410 ps
CPU time 113.14 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:27:05 PM PDT 24
Peak memory 233656 kb
Host smart-6b10f0d2-88d6-480d-b575-0f730a7acc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459466596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1459466596 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sideload.379685385
Short name T749
Test name
Test status
Simulation time 30749739336 ps
CPU time 451.24 seconds
Started Mar 24 01:25:06 PM PDT 24
Finished Mar 24 01:32:37 PM PDT 24
Peak memory 253136 kb
Host smart-e3d4381e-31e1-44ea-aaaa-82c01eb75e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379685385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.379685385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.618058097
Short name T299
Test name
Test status
Simulation time 11151955262 ps
CPU time 64.57 seconds
Started Mar 24 01:25:04 PM PDT 24
Finished Mar 24 01:26:08 PM PDT 24
Peak memory 222528 kb
Host smart-c99cb2f2-076a-4004-bba7-39387ce6ed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618058097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.618058097 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.284727714
Short name T675
Test name
Test status
Simulation time 484008374 ps
CPU time 4.95 seconds
Started Mar 24 01:25:06 PM PDT 24
Finished Mar 24 01:25:11 PM PDT 24
Peak memory 216320 kb
Host smart-fb32c169-af07-4bdb-8672-a2279e85830e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284727714 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.kmac_test_vectors_kmac.284727714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.743753740
Short name T780
Test name
Test status
Simulation time 172813965 ps
CPU time 4.68 seconds
Started Mar 24 01:25:15 PM PDT 24
Finished Mar 24 01:25:20 PM PDT 24
Peak memory 209324 kb
Host smart-00ae5bfb-05cc-4576-890d-555c4079d14b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743753740 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.kmac_test_vectors_kmac_xof.743753740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.550970415
Short name T994
Test name
Test status
Simulation time 933949317544 ps
CPU time 2132.35 seconds
Started Mar 24 01:25:05 PM PDT 24
Finished Mar 24 02:00:38 PM PDT 24
Peak memory 395520 kb
Host smart-5321511e-4c77-4d72-b98b-cf3a8caca19e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=550970415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.550970415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.4113979213
Short name T538
Test name
Test status
Simulation time 19109948963 ps
CPU time 1477.56 seconds
Started Mar 24 01:25:06 PM PDT 24
Finished Mar 24 01:49:44 PM PDT 24
Peak memory 390280 kb
Host smart-8c3cc68f-22c9-4580-afed-4a8aefba4408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4113979213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.4113979213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.960368328
Short name T307
Test name
Test status
Simulation time 222834670406 ps
CPU time 1446.68 seconds
Started Mar 24 01:25:08 PM PDT 24
Finished Mar 24 01:49:15 PM PDT 24
Peak memory 335032 kb
Host smart-4670db6a-1118-4f32-b385-83dd2cf1bd45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=960368328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.960368328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.1228820565
Short name T752
Test name
Test status
Simulation time 20148734291 ps
CPU time 763.35 seconds
Started Mar 24 01:25:08 PM PDT 24
Finished Mar 24 01:37:51 PM PDT 24
Peak memory 298720 kb
Host smart-9ab0db0d-9cde-4337-8920-eaae7945abe5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1228820565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1228820565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.3800415342
Short name T267
Test name
Test status
Simulation time 718813996687 ps
CPU time 4848.49 seconds
Started Mar 24 01:25:05 PM PDT 24
Finished Mar 24 02:45:54 PM PDT 24
Peak memory 653540 kb
Host smart-fbb90f41-5f3f-4841-a8a8-098f02572a2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3800415342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3800415342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.2062622036
Short name T1071
Test name
Test status
Simulation time 408631742551 ps
CPU time 3760.19 seconds
Started Mar 24 01:25:05 PM PDT 24
Finished Mar 24 02:27:46 PM PDT 24
Peak memory 549076 kb
Host smart-5659d9f3-79cf-4d52-88a0-ac3aabc4345a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2062622036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2062622036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.543837809
Short name T797
Test name
Test status
Simulation time 14929083 ps
CPU time 0.79 seconds
Started Mar 24 01:25:16 PM PDT 24
Finished Mar 24 01:25:17 PM PDT 24
Peak memory 205588 kb
Host smart-a20e7578-3a2c-4b69-987c-0ec3341b83ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543837809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.543837809 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.2066953193
Short name T932
Test name
Test status
Simulation time 6982763554 ps
CPU time 170.03 seconds
Started Mar 24 01:25:15 PM PDT 24
Finished Mar 24 01:28:05 PM PDT 24
Peak memory 236688 kb
Host smart-de31d8cd-d5bd-46ef-b2b8-310fe13306df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066953193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2066953193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.1797963194
Short name T887
Test name
Test status
Simulation time 12529255811 ps
CPU time 46.33 seconds
Started Mar 24 01:25:15 PM PDT 24
Finished Mar 24 01:26:02 PM PDT 24
Peak memory 222496 kb
Host smart-5ec004ca-aad2-4b49-a690-91a7479071bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797963194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1797963194 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.448304494
Short name T333
Test name
Test status
Simulation time 5131935906 ps
CPU time 411.62 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:32:03 PM PDT 24
Peak memory 228636 kb
Host smart-e63dc606-b75b-4954-96f7-9c5dbab7fe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448304494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.448304494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.1729939273
Short name T174
Test name
Test status
Simulation time 2781197415 ps
CPU time 16.69 seconds
Started Mar 24 01:25:19 PM PDT 24
Finished Mar 24 01:25:36 PM PDT 24
Peak memory 224376 kb
Host smart-a442f35d-2e8c-47aa-b7c5-f62e576dd5c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1729939273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1729939273 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.3593634249
Short name T637
Test name
Test status
Simulation time 920246341 ps
CPU time 12.97 seconds
Started Mar 24 01:25:16 PM PDT 24
Finished Mar 24 01:25:29 PM PDT 24
Peak memory 217144 kb
Host smart-e08cf791-ed1e-4c39-9cf4-04244bf6407d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3593634249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3593634249 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.1496723195
Short name T1047
Test name
Test status
Simulation time 4572820087 ps
CPU time 38.04 seconds
Started Mar 24 01:25:16 PM PDT 24
Finished Mar 24 01:25:54 PM PDT 24
Peak memory 217332 kb
Host smart-89721fdc-b579-4dae-b1e5-48f84339702a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496723195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1496723195 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.931805804
Short name T1052
Test name
Test status
Simulation time 2201701131 ps
CPU time 37.86 seconds
Started Mar 24 01:25:16 PM PDT 24
Finished Mar 24 01:25:54 PM PDT 24
Peak memory 221700 kb
Host smart-d060ea18-9be2-48e4-ae1b-a062b67532f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931805804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.931805804 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.1138112829
Short name T758
Test name
Test status
Simulation time 6534763475 ps
CPU time 112.94 seconds
Started Mar 24 01:25:23 PM PDT 24
Finished Mar 24 01:27:16 PM PDT 24
Peak memory 240972 kb
Host smart-07b6f777-6566-4ffa-8a0a-e98de3fef737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138112829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1138112829 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.2596954226
Short name T711
Test name
Test status
Simulation time 339988663 ps
CPU time 2.58 seconds
Started Mar 24 01:25:19 PM PDT 24
Finished Mar 24 01:25:22 PM PDT 24
Peak memory 207792 kb
Host smart-52054de1-6130-4330-a354-f5ac1ba655c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596954226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2596954226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.802554247
Short name T1066
Test name
Test status
Simulation time 76585181 ps
CPU time 1.32 seconds
Started Mar 24 01:25:18 PM PDT 24
Finished Mar 24 01:25:20 PM PDT 24
Peak memory 216180 kb
Host smart-64f14ec5-5e4a-40c9-b26a-548227c7e0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802554247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.802554247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1353503700
Short name T335
Test name
Test status
Simulation time 40629464055 ps
CPU time 647.46 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:35:59 PM PDT 24
Peak memory 280832 kb
Host smart-30bc483e-1988-46ab-9334-6ee021a3e7f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353503700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1353503700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.3634879020
Short name T176
Test name
Test status
Simulation time 11102804255 ps
CPU time 140.29 seconds
Started Mar 24 01:25:18 PM PDT 24
Finished Mar 24 01:27:38 PM PDT 24
Peak memory 235304 kb
Host smart-64eb5bd6-56c7-483b-90e8-2d6c898d6534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634879020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3634879020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.3411718312
Short name T11
Test name
Test status
Simulation time 2610747692 ps
CPU time 32.82 seconds
Started Mar 24 01:25:17 PM PDT 24
Finished Mar 24 01:25:50 PM PDT 24
Peak memory 244336 kb
Host smart-591e4788-9d46-4243-a7ff-ab8b13a5ed62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411718312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3411718312 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.419846140
Short name T271
Test name
Test status
Simulation time 17712244164 ps
CPU time 218.4 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:28:50 PM PDT 24
Peak memory 240892 kb
Host smart-d6b65806-9530-4da9-b68e-bf24975297c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419846140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.419846140 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.2112410735
Short name T332
Test name
Test status
Simulation time 4588001245 ps
CPU time 54.32 seconds
Started Mar 24 01:25:10 PM PDT 24
Finished Mar 24 01:26:05 PM PDT 24
Peak memory 217664 kb
Host smart-ae03d653-6d98-4f2c-bfd8-f155b37607a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112410735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2112410735 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1200454226
Short name T796
Test name
Test status
Simulation time 29505033154 ps
CPU time 802.75 seconds
Started Mar 24 01:25:18 PM PDT 24
Finished Mar 24 01:38:41 PM PDT 24
Peak memory 320396 kb
Host smart-54955660-c6f1-49af-a6fa-b2997e0cbfbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1200454226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1200454226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.3591928716
Short name T851
Test name
Test status
Simulation time 128274415 ps
CPU time 3.7 seconds
Started Mar 24 01:25:15 PM PDT 24
Finished Mar 24 01:25:19 PM PDT 24
Peak memory 216288 kb
Host smart-51cde510-ba0e-4ccc-93e9-d4da52dd54ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591928716 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.3591928716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.78025181
Short name T623
Test name
Test status
Simulation time 644907204 ps
CPU time 4.85 seconds
Started Mar 24 01:25:14 PM PDT 24
Finished Mar 24 01:25:19 PM PDT 24
Peak memory 216272 kb
Host smart-72d7bdae-6670-493f-a29f-a0905184a90e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78025181 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.kmac_test_vectors_kmac_xof.78025181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.133819152
Short name T407
Test name
Test status
Simulation time 503344386297 ps
CPU time 1984.49 seconds
Started Mar 24 01:25:10 PM PDT 24
Finished Mar 24 01:58:15 PM PDT 24
Peak memory 396260 kb
Host smart-838ce0f0-ea34-47c4-971c-072852da0a21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=133819152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.133819152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.2214188218
Short name T155
Test name
Test status
Simulation time 97476958227 ps
CPU time 1433.19 seconds
Started Mar 24 01:25:11 PM PDT 24
Finished Mar 24 01:49:04 PM PDT 24
Peak memory 371096 kb
Host smart-528068bb-949d-43e7-9d6d-c6501e3f43c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2214188218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2214188218 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.4020781460
Short name T1036
Test name
Test status
Simulation time 49867691459 ps
CPU time 1308.96 seconds
Started Mar 24 01:25:12 PM PDT 24
Finished Mar 24 01:47:01 PM PDT 24
Peak memory 337780 kb
Host smart-f784bf10-9a94-4c9c-ab53-4f05959884c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4020781460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.4020781460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.1826800913
Short name T246
Test name
Test status
Simulation time 50768476826 ps
CPU time 978.35 seconds
Started Mar 24 01:25:10 PM PDT 24
Finished Mar 24 01:41:29 PM PDT 24
Peak memory 295096 kb
Host smart-470691ce-085e-479a-8330-73456e03fd2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1826800913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1826800913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1020335505
Short name T522
Test name
Test status
Simulation time 51240054784 ps
CPU time 3889.49 seconds
Started Mar 24 01:25:15 PM PDT 24
Finished Mar 24 02:30:05 PM PDT 24
Peak memory 637416 kb
Host smart-ba10fa85-6e10-4d58-8dd7-602448f4ba44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1020335505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1020335505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.231359219
Short name T432
Test name
Test status
Simulation time 814812124710 ps
CPU time 4249.94 seconds
Started Mar 24 01:25:15 PM PDT 24
Finished Mar 24 02:36:06 PM PDT 24
Peak memory 574680 kb
Host smart-7a392954-6e16-4c1c-b4ab-71bb8eeaac50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=231359219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.231359219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.1307867488
Short name T399
Test name
Test status
Simulation time 46976949 ps
CPU time 0.75 seconds
Started Mar 24 01:26:26 PM PDT 24
Finished Mar 24 01:26:27 PM PDT 24
Peak memory 205696 kb
Host smart-e57a1bfe-0821-44d4-9caa-042a909af116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307867488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1307867488 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.4030957568
Short name T508
Test name
Test status
Simulation time 9794926596 ps
CPU time 244 seconds
Started Mar 24 01:26:20 PM PDT 24
Finished Mar 24 01:30:25 PM PDT 24
Peak memory 242288 kb
Host smart-e897f33b-3b65-4146-a3b3-a0cedb510434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030957568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.4030957568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.2279002999
Short name T539
Test name
Test status
Simulation time 1943093682 ps
CPU time 160.88 seconds
Started Mar 24 01:26:18 PM PDT 24
Finished Mar 24 01:28:59 PM PDT 24
Peak memory 224428 kb
Host smart-5fb4cb9c-3c27-4323-92a4-5a1e89140c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279002999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2279002999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.2029544817
Short name T1061
Test name
Test status
Simulation time 339636348 ps
CPU time 7.72 seconds
Started Mar 24 01:26:26 PM PDT 24
Finished Mar 24 01:26:33 PM PDT 24
Peak memory 217144 kb
Host smart-019c2e7f-e9a1-40a0-abd9-1d37c578d324
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2029544817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2029544817 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.2983952009
Short name T1020
Test name
Test status
Simulation time 919649580 ps
CPU time 25.71 seconds
Started Mar 24 01:26:26 PM PDT 24
Finished Mar 24 01:26:51 PM PDT 24
Peak memory 224248 kb
Host smart-3ad5dcb8-a138-41af-8696-a7f4efdbe767
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2983952009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2983952009 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.2611450317
Short name T33
Test name
Test status
Simulation time 83570154741 ps
CPU time 382.79 seconds
Started Mar 24 01:26:22 PM PDT 24
Finished Mar 24 01:32:45 PM PDT 24
Peak memory 246808 kb
Host smart-33d0aade-ba53-446a-b503-d7b717f8bafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611450317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2611450317 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.1266041846
Short name T629
Test name
Test status
Simulation time 14798228929 ps
CPU time 146.57 seconds
Started Mar 24 01:26:21 PM PDT 24
Finished Mar 24 01:28:48 PM PDT 24
Peak memory 241896 kb
Host smart-9602a2d4-3369-4850-9333-16f1d25418b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266041846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1266041846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.3300884524
Short name T885
Test name
Test status
Simulation time 1216256459 ps
CPU time 2.08 seconds
Started Mar 24 01:26:26 PM PDT 24
Finished Mar 24 01:26:28 PM PDT 24
Peak memory 207808 kb
Host smart-5c2e49c7-2bdf-43d4-a218-085222283490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300884524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3300884524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.2745432709
Short name T842
Test name
Test status
Simulation time 40944353 ps
CPU time 1.47 seconds
Started Mar 24 01:26:26 PM PDT 24
Finished Mar 24 01:26:27 PM PDT 24
Peak memory 218512 kb
Host smart-6c9a4422-c669-4024-8cd5-8df831050ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745432709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2745432709 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.361731744
Short name T1041
Test name
Test status
Simulation time 110477920319 ps
CPU time 2346.43 seconds
Started Mar 24 01:26:15 PM PDT 24
Finished Mar 24 02:05:22 PM PDT 24
Peak memory 465272 kb
Host smart-15337f75-b1dd-4be2-ba5c-fa062d4a2b9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361731744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_an
d_output.361731744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.2297970657
Short name T270
Test name
Test status
Simulation time 44883218964 ps
CPU time 324.28 seconds
Started Mar 24 01:26:17 PM PDT 24
Finished Mar 24 01:31:42 PM PDT 24
Peak memory 245676 kb
Host smart-f5bb9a3f-f19f-458d-9634-1ff25df833d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297970657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2297970657 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.480655737
Short name T357
Test name
Test status
Simulation time 1222831628 ps
CPU time 16.39 seconds
Started Mar 24 01:26:17 PM PDT 24
Finished Mar 24 01:26:33 PM PDT 24
Peak memory 224408 kb
Host smart-6d6044fd-5fd5-479b-a638-0c39cba71a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480655737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.480655737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.3595501496
Short name T506
Test name
Test status
Simulation time 16695596721 ps
CPU time 207.02 seconds
Started Mar 24 01:26:27 PM PDT 24
Finished Mar 24 01:29:54 PM PDT 24
Peak memory 250904 kb
Host smart-fa15bbc0-36ce-44b5-aacf-c32edc3d6e87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3595501496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3595501496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.1868707225
Short name T703
Test name
Test status
Simulation time 809503958 ps
CPU time 4.18 seconds
Started Mar 24 01:26:20 PM PDT 24
Finished Mar 24 01:26:25 PM PDT 24
Peak memory 216240 kb
Host smart-ff8c494f-f5b9-4f4f-b310-dfce7932dbd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868707225 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.1868707225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.3061316436
Short name T428
Test name
Test status
Simulation time 220580096 ps
CPU time 4.73 seconds
Started Mar 24 01:26:23 PM PDT 24
Finished Mar 24 01:26:27 PM PDT 24
Peak memory 216280 kb
Host smart-26b7843f-b43f-41ac-a2f7-1d0e6389a9f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061316436 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.3061316436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.3020831449
Short name T858
Test name
Test status
Simulation time 125113544695 ps
CPU time 1614.95 seconds
Started Mar 24 01:26:22 PM PDT 24
Finished Mar 24 01:53:17 PM PDT 24
Peak memory 391592 kb
Host smart-9d48b643-e285-4cb0-bf17-30c08689f8c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3020831449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3020831449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.948806528
Short name T420
Test name
Test status
Simulation time 176506497212 ps
CPU time 1444.47 seconds
Started Mar 24 01:26:20 PM PDT 24
Finished Mar 24 01:50:25 PM PDT 24
Peak memory 372764 kb
Host smart-4cecfc4d-d76e-4a96-9ab4-e81c811170a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=948806528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.948806528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.673457660
Short name T175
Test name
Test status
Simulation time 60622431410 ps
CPU time 1324.05 seconds
Started Mar 24 01:26:21 PM PDT 24
Finished Mar 24 01:48:25 PM PDT 24
Peak memory 334304 kb
Host smart-64ecf334-28a2-4a3b-b8e3-62f9f1d47326
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=673457660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.673457660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.2460357694
Short name T898
Test name
Test status
Simulation time 9865904743 ps
CPU time 768.12 seconds
Started Mar 24 01:26:22 PM PDT 24
Finished Mar 24 01:39:10 PM PDT 24
Peak memory 296876 kb
Host smart-180538ea-26c7-47b3-be0b-cc0fd4cc88bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2460357694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.2460357694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.3010144765
Short name T995
Test name
Test status
Simulation time 1886659074695 ps
CPU time 5202 seconds
Started Mar 24 01:26:22 PM PDT 24
Finished Mar 24 02:53:04 PM PDT 24
Peak memory 636860 kb
Host smart-c6bfa51a-ffcb-4e0d-8e22-a09319a7526f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3010144765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3010144765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.2711589304
Short name T679
Test name
Test status
Simulation time 83749374283 ps
CPU time 3393.84 seconds
Started Mar 24 01:26:22 PM PDT 24
Finished Mar 24 02:22:56 PM PDT 24
Peak memory 566088 kb
Host smart-667ce9fd-000c-46d1-9391-0a392a377613
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2711589304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.2711589304 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.2478377029
Short name T564
Test name
Test status
Simulation time 52887127 ps
CPU time 0.79 seconds
Started Mar 24 01:26:34 PM PDT 24
Finished Mar 24 01:26:35 PM PDT 24
Peak memory 205704 kb
Host smart-a9908e65-4369-44bf-a0a8-5a8d6a29a905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478377029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2478377029 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.2989676057
Short name T803
Test name
Test status
Simulation time 16136853503 ps
CPU time 273.26 seconds
Started Mar 24 01:26:30 PM PDT 24
Finished Mar 24 01:31:03 PM PDT 24
Peak memory 244064 kb
Host smart-bb230d2f-c70b-4f71-a19f-80c3864d73e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989676057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2989676057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.560654210
Short name T1006
Test name
Test status
Simulation time 165667993073 ps
CPU time 779.35 seconds
Started Mar 24 01:26:26 PM PDT 24
Finished Mar 24 01:39:25 PM PDT 24
Peak memory 231604 kb
Host smart-f345ae09-015b-46aa-9ea3-a64923a9023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560654210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.560654210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.1143366162
Short name T949
Test name
Test status
Simulation time 817612409 ps
CPU time 17.42 seconds
Started Mar 24 01:26:35 PM PDT 24
Finished Mar 24 01:26:52 PM PDT 24
Peak memory 224284 kb
Host smart-b22e0f44-9eda-4f0c-8dfa-ffd5c647566d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1143366162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1143366162 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.1348563630
Short name T223
Test name
Test status
Simulation time 934777746 ps
CPU time 19.28 seconds
Started Mar 24 01:26:35 PM PDT 24
Finished Mar 24 01:26:54 PM PDT 24
Peak memory 224300 kb
Host smart-815a5311-afba-40c8-b058-09b2e9b7c79f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1348563630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1348563630 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.1915279878
Short name T367
Test name
Test status
Simulation time 9298905216 ps
CPU time 222.3 seconds
Started Mar 24 01:26:30 PM PDT 24
Finished Mar 24 01:30:13 PM PDT 24
Peak memory 241828 kb
Host smart-6fec8495-6c9c-4ac4-9352-1677ea2e16f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915279878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1915279878 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.862787193
Short name T906
Test name
Test status
Simulation time 42085116825 ps
CPU time 419.67 seconds
Started Mar 24 01:26:37 PM PDT 24
Finished Mar 24 01:33:37 PM PDT 24
Peak memory 255016 kb
Host smart-3946713f-0aff-49a0-a62c-9cfb32f9d6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862787193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.862787193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.2661714099
Short name T835
Test name
Test status
Simulation time 72673911 ps
CPU time 0.93 seconds
Started Mar 24 01:26:34 PM PDT 24
Finished Mar 24 01:26:35 PM PDT 24
Peak memory 206256 kb
Host smart-a8d273bb-13a3-47d0-aa0b-54ff07e9abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661714099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2661714099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.128017268
Short name T408
Test name
Test status
Simulation time 561922158 ps
CPU time 1.39 seconds
Started Mar 24 01:26:34 PM PDT 24
Finished Mar 24 01:26:36 PM PDT 24
Peak memory 216120 kb
Host smart-bbe9e908-4c99-4c36-b34e-7ed10028c4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128017268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.128017268 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1321960027
Short name T891
Test name
Test status
Simulation time 69485309272 ps
CPU time 1531.13 seconds
Started Mar 24 01:26:26 PM PDT 24
Finished Mar 24 01:51:58 PM PDT 24
Peak memory 402040 kb
Host smart-c4d62cfe-1762-4d5d-90fa-a1f464b6b40f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321960027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1321960027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.1000140756
Short name T1023
Test name
Test status
Simulation time 2353442912 ps
CPU time 178 seconds
Started Mar 24 01:26:27 PM PDT 24
Finished Mar 24 01:29:26 PM PDT 24
Peak memory 238188 kb
Host smart-2ba36626-3879-4491-a768-77df01094bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000140756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1000140756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.1816904514
Short name T1031
Test name
Test status
Simulation time 273415527 ps
CPU time 13.19 seconds
Started Mar 24 01:26:24 PM PDT 24
Finished Mar 24 01:26:38 PM PDT 24
Peak memory 220708 kb
Host smart-f6d77fd5-1ba4-4d88-b802-fddc0b23f298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816904514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1816904514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.2967744733
Short name T475
Test name
Test status
Simulation time 275361234652 ps
CPU time 539.55 seconds
Started Mar 24 01:26:35 PM PDT 24
Finished Mar 24 01:35:34 PM PDT 24
Peak memory 306720 kb
Host smart-736948da-91c5-4d9b-8a3e-c3834dce313f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2967744733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2967744733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.720495718
Short name T310
Test name
Test status
Simulation time 2031905457 ps
CPU time 4.44 seconds
Started Mar 24 01:26:30 PM PDT 24
Finished Mar 24 01:26:35 PM PDT 24
Peak memory 216296 kb
Host smart-6f7bc4ae-7871-49d8-aa02-363ed7a0cd61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720495718 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.kmac_test_vectors_kmac.720495718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.1170934967
Short name T546
Test name
Test status
Simulation time 357883900 ps
CPU time 5.07 seconds
Started Mar 24 01:26:29 PM PDT 24
Finished Mar 24 01:26:34 PM PDT 24
Peak memory 216348 kb
Host smart-3a570f0b-d167-42a4-a1e0-298dd4daab3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170934967 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.1170934967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.1043468997
Short name T156
Test name
Test status
Simulation time 18793805565 ps
CPU time 1515.68 seconds
Started Mar 24 01:26:30 PM PDT 24
Finished Mar 24 01:51:46 PM PDT 24
Peak memory 390520 kb
Host smart-4550fb3f-7e61-4981-8e03-245b63e0e869
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1043468997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.1043468997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.3986051721
Short name T579
Test name
Test status
Simulation time 124387087419 ps
CPU time 1824.34 seconds
Started Mar 24 01:26:29 PM PDT 24
Finished Mar 24 01:56:54 PM PDT 24
Peak memory 388272 kb
Host smart-886374cf-d12c-450c-b603-6c23cf46c7a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3986051721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.3986051721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.2352127574
Short name T219
Test name
Test status
Simulation time 392607989729 ps
CPU time 1451.81 seconds
Started Mar 24 01:26:29 PM PDT 24
Finished Mar 24 01:50:41 PM PDT 24
Peak memory 337664 kb
Host smart-9a330d0d-ef17-41aa-85fd-16eaa51316bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2352127574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.2352127574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.623008689
Short name T501
Test name
Test status
Simulation time 52689830131 ps
CPU time 860.77 seconds
Started Mar 24 01:26:31 PM PDT 24
Finished Mar 24 01:40:52 PM PDT 24
Peak memory 295576 kb
Host smart-084e57de-7e10-4be6-9923-495a0485c961
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=623008689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.623008689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.2148203331
Short name T737
Test name
Test status
Simulation time 681067019688 ps
CPU time 4906.09 seconds
Started Mar 24 01:26:28 PM PDT 24
Finished Mar 24 02:48:15 PM PDT 24
Peak memory 642112 kb
Host smart-4b00b963-9644-4cd4-a157-b636e02601c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2148203331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.2148203331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.1435035524
Short name T559
Test name
Test status
Simulation time 436752086342 ps
CPU time 4220.95 seconds
Started Mar 24 01:26:33 PM PDT 24
Finished Mar 24 02:36:54 PM PDT 24
Peak memory 567736 kb
Host smart-8790c21b-2279-46ec-9a6e-113b9d01348c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1435035524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.1435035524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.2760466237
Short name T385
Test name
Test status
Simulation time 18902053 ps
CPU time 0.81 seconds
Started Mar 24 01:26:40 PM PDT 24
Finished Mar 24 01:26:41 PM PDT 24
Peak memory 205700 kb
Host smart-88acd52e-7ed2-4c31-95fb-709d5adf01d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760466237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2760466237 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.3154583891
Short name T131
Test name
Test status
Simulation time 24564428756 ps
CPU time 159.35 seconds
Started Mar 24 01:26:39 PM PDT 24
Finished Mar 24 01:29:18 PM PDT 24
Peak memory 233564 kb
Host smart-9196e3f9-78ea-4d64-8ce5-79a72dc5998e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154583891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3154583891 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.3763294733
Short name T72
Test name
Test status
Simulation time 2120890790 ps
CPU time 170.57 seconds
Started Mar 24 01:26:37 PM PDT 24
Finished Mar 24 01:29:28 PM PDT 24
Peak memory 224492 kb
Host smart-4ed30663-1a65-481d-8032-7596195353c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763294733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3763294733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.1173465283
Short name T790
Test name
Test status
Simulation time 343971417 ps
CPU time 13.39 seconds
Started Mar 24 01:26:39 PM PDT 24
Finished Mar 24 01:26:52 PM PDT 24
Peak memory 224196 kb
Host smart-2bd0a347-5cea-4953-ab6c-245a8b5244b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1173465283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1173465283 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.244292731
Short name T1045
Test name
Test status
Simulation time 80066793 ps
CPU time 2.37 seconds
Started Mar 24 01:26:39 PM PDT 24
Finished Mar 24 01:26:41 PM PDT 24
Peak memory 216060 kb
Host smart-b1754fe8-95da-4554-b0ef-d0140592c6c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=244292731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.244292731 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.1426291233
Short name T696
Test name
Test status
Simulation time 13954191909 ps
CPU time 259.99 seconds
Started Mar 24 01:26:39 PM PDT 24
Finished Mar 24 01:30:59 PM PDT 24
Peak memory 242844 kb
Host smart-619c4a7c-f2a8-4b7d-82fd-a35220734796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426291233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.1426291233 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.62655627
Short name T342
Test name
Test status
Simulation time 44711745392 ps
CPU time 310.56 seconds
Started Mar 24 01:26:39 PM PDT 24
Finished Mar 24 01:31:50 PM PDT 24
Peak memory 265552 kb
Host smart-7e6c7525-84b3-4f44-8f87-cc49d9ca0874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62655627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.62655627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.3287696999
Short name T904
Test name
Test status
Simulation time 2311271701 ps
CPU time 4.45 seconds
Started Mar 24 01:26:40 PM PDT 24
Finished Mar 24 01:26:45 PM PDT 24
Peak memory 207892 kb
Host smart-0608c001-445e-4caf-82bf-c43fc8978773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287696999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3287696999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.693890515
Short name T873
Test name
Test status
Simulation time 441284895 ps
CPU time 9.45 seconds
Started Mar 24 01:26:40 PM PDT 24
Finished Mar 24 01:26:49 PM PDT 24
Peak memory 224432 kb
Host smart-001a1bf2-c90d-4eea-89c8-2c2ae5e741fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693890515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.693890515 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.1244935967
Short name T483
Test name
Test status
Simulation time 110645567687 ps
CPU time 896.79 seconds
Started Mar 24 01:26:34 PM PDT 24
Finished Mar 24 01:41:31 PM PDT 24
Peak memory 301324 kb
Host smart-122824f4-5a72-41ab-9828-1532f20c4c6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244935967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.1244935967 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.672203409
Short name T964
Test name
Test status
Simulation time 1673634886 ps
CPU time 46.11 seconds
Started Mar 24 01:26:34 PM PDT 24
Finished Mar 24 01:27:20 PM PDT 24
Peak memory 220968 kb
Host smart-0358c65b-45bb-4dfa-8099-b6abaa053848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672203409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.672203409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.549055998
Short name T757
Test name
Test status
Simulation time 138324252 ps
CPU time 7.47 seconds
Started Mar 24 01:26:35 PM PDT 24
Finished Mar 24 01:26:42 PM PDT 24
Peak memory 219720 kb
Host smart-1f03d887-56c7-484a-a3b3-11b6ec5d47cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549055998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.549055998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.1726873590
Short name T412
Test name
Test status
Simulation time 484629548 ps
CPU time 4.85 seconds
Started Mar 24 01:26:40 PM PDT 24
Finished Mar 24 01:26:45 PM PDT 24
Peak memory 216176 kb
Host smart-cf24397c-d667-42f5-9211-ea1c171746aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726873590 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.1726873590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.839753812
Short name T554
Test name
Test status
Simulation time 265355514 ps
CPU time 3.94 seconds
Started Mar 24 01:26:39 PM PDT 24
Finished Mar 24 01:26:43 PM PDT 24
Peak memory 216200 kb
Host smart-8f1a930b-d779-4fe4-b582-aaaf5d1e7bc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839753812 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.kmac_test_vectors_kmac_xof.839753812 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.2350549462
Short name T751
Test name
Test status
Simulation time 387213362486 ps
CPU time 2032.4 seconds
Started Mar 24 01:26:36 PM PDT 24
Finished Mar 24 02:00:29 PM PDT 24
Peak memory 391220 kb
Host smart-3d94eb32-4034-44d6-a4e5-a6ef48c236e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2350549462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.2350549462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.1792668381
Short name T227
Test name
Test status
Simulation time 62776538413 ps
CPU time 1574.86 seconds
Started Mar 24 01:26:36 PM PDT 24
Finished Mar 24 01:52:52 PM PDT 24
Peak memory 371640 kb
Host smart-139372af-8c0c-4b1f-ad9d-2be3cd055191
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1792668381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.1792668381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.628910142
Short name T1010
Test name
Test status
Simulation time 206088713886 ps
CPU time 1359.02 seconds
Started Mar 24 01:26:38 PM PDT 24
Finished Mar 24 01:49:17 PM PDT 24
Peak memory 338596 kb
Host smart-a23602c4-e412-4b22-a5c8-10d53cef8016
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=628910142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.628910142 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.853277347
Short name T258
Test name
Test status
Simulation time 9876738829 ps
CPU time 731.75 seconds
Started Mar 24 01:26:39 PM PDT 24
Finished Mar 24 01:38:51 PM PDT 24
Peak memory 294148 kb
Host smart-fc49a512-2c23-46f4-aa7e-5d4bff32b10c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=853277347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.853277347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.4189229306
Short name T489
Test name
Test status
Simulation time 62453475653 ps
CPU time 4245.02 seconds
Started Mar 24 01:26:39 PM PDT 24
Finished Mar 24 02:37:25 PM PDT 24
Peak memory 657508 kb
Host smart-86db1d6a-cdd7-44be-afac-623d013bb279
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4189229306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.4189229306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.3542485416
Short name T431
Test name
Test status
Simulation time 614071474098 ps
CPU time 3728.53 seconds
Started Mar 24 01:26:40 PM PDT 24
Finished Mar 24 02:28:49 PM PDT 24
Peak memory 556788 kb
Host smart-0c850fd0-8e20-40c9-9d59-86dde7fb2946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3542485416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.3542485416 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.3335428990
Short name T649
Test name
Test status
Simulation time 86774354 ps
CPU time 0.86 seconds
Started Mar 24 01:26:48 PM PDT 24
Finished Mar 24 01:26:50 PM PDT 24
Peak memory 205696 kb
Host smart-774a8185-81dc-43ff-bfc8-18c833a70cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335428990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3335428990 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.822476483
Short name T153
Test name
Test status
Simulation time 14927234967 ps
CPU time 292.53 seconds
Started Mar 24 01:26:44 PM PDT 24
Finished Mar 24 01:31:36 PM PDT 24
Peak memory 242824 kb
Host smart-d84252f5-94d4-46d2-b24b-b8f1be4285da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822476483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.822476483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.2053330193
Short name T668
Test name
Test status
Simulation time 14629685127 ps
CPU time 368.03 seconds
Started Mar 24 01:26:45 PM PDT 24
Finished Mar 24 01:32:54 PM PDT 24
Peak memory 229376 kb
Host smart-855e1822-501a-4270-af5b-2d9d8a214b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053330193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2053330193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.3540626838
Short name T686
Test name
Test status
Simulation time 671811296 ps
CPU time 7.58 seconds
Started Mar 24 01:26:53 PM PDT 24
Finished Mar 24 01:27:01 PM PDT 24
Peak memory 219356 kb
Host smart-92fa4336-ed12-4bfe-9437-ac297503400a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3540626838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3540626838 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.1894324453
Short name T289
Test name
Test status
Simulation time 915253917 ps
CPU time 8.57 seconds
Started Mar 24 01:26:49 PM PDT 24
Finished Mar 24 01:26:59 PM PDT 24
Peak memory 219484 kb
Host smart-655fb646-e328-447b-9432-ae64eebfc549
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1894324453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1894324453 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.2634650650
Short name T908
Test name
Test status
Simulation time 19336380451 ps
CPU time 324.53 seconds
Started Mar 24 01:26:45 PM PDT 24
Finished Mar 24 01:32:10 PM PDT 24
Peak memory 247236 kb
Host smart-6414b775-108f-4de1-8d61-28b50a4bf199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634650650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2634650650 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.3296414639
Short name T571
Test name
Test status
Simulation time 24867704512 ps
CPU time 261.55 seconds
Started Mar 24 01:26:45 PM PDT 24
Finished Mar 24 01:31:06 PM PDT 24
Peak memory 249876 kb
Host smart-ceb466cb-e269-421b-a38e-b6b663019ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296414639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3296414639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.3065595662
Short name T861
Test name
Test status
Simulation time 1588898222 ps
CPU time 2.83 seconds
Started Mar 24 01:26:53 PM PDT 24
Finished Mar 24 01:26:56 PM PDT 24
Peak memory 207788 kb
Host smart-017aa73f-8a31-4356-9a7e-5e8c3ca57c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065595662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3065595662 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.1941440955
Short name T101
Test name
Test status
Simulation time 32975191 ps
CPU time 1.16 seconds
Started Mar 24 01:26:52 PM PDT 24
Finished Mar 24 01:26:53 PM PDT 24
Peak memory 216208 kb
Host smart-acd487a5-3a32-409c-8675-abc9b966f25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941440955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1941440955 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.3041109777
Short name T1030
Test name
Test status
Simulation time 62322380830 ps
CPU time 839.01 seconds
Started Mar 24 01:26:45 PM PDT 24
Finished Mar 24 01:40:44 PM PDT 24
Peak memory 305976 kb
Host smart-7c8a80fe-e98f-45bb-9ea8-93d0b898d789
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041109777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.3041109777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.79676750
Short name T1044
Test name
Test status
Simulation time 934931293 ps
CPU time 26.15 seconds
Started Mar 24 01:26:46 PM PDT 24
Finished Mar 24 01:27:12 PM PDT 24
Peak memory 232552 kb
Host smart-e6542fa0-bbea-4623-9b4f-279a2ca79b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79676750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.79676750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.3018450734
Short name T574
Test name
Test status
Simulation time 1194655857 ps
CPU time 15.11 seconds
Started Mar 24 01:26:43 PM PDT 24
Finished Mar 24 01:26:59 PM PDT 24
Peak memory 219464 kb
Host smart-5972331e-8282-44df-8c40-da347cdd8ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018450734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3018450734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.2978963324
Short name T689
Test name
Test status
Simulation time 124098028731 ps
CPU time 920.28 seconds
Started Mar 24 01:26:49 PM PDT 24
Finished Mar 24 01:42:11 PM PDT 24
Peak memory 338804 kb
Host smart-a6b8e468-cdcd-4a12-a116-bfd4390952b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2978963324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2978963324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.3160973446
Short name T451
Test name
Test status
Simulation time 68471629 ps
CPU time 3.77 seconds
Started Mar 24 01:26:43 PM PDT 24
Finished Mar 24 01:26:47 PM PDT 24
Peak memory 216212 kb
Host smart-ca8dde0c-7b54-431b-ac4b-820a182f377e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160973446 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.3160973446 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.1557298562
Short name T970
Test name
Test status
Simulation time 170463794 ps
CPU time 4.52 seconds
Started Mar 24 01:26:45 PM PDT 24
Finished Mar 24 01:26:49 PM PDT 24
Peak memory 216532 kb
Host smart-991d8ee5-1510-4a2a-86c0-da90a2c17ca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557298562 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.1557298562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.1880352404
Short name T249
Test name
Test status
Simulation time 19530234677 ps
CPU time 1554.44 seconds
Started Mar 24 01:26:44 PM PDT 24
Finished Mar 24 01:52:38 PM PDT 24
Peak memory 398384 kb
Host smart-ae76b8a8-93fa-45f1-a568-610de08adc3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1880352404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1880352404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.2232326525
Short name T386
Test name
Test status
Simulation time 247071968131 ps
CPU time 1745.94 seconds
Started Mar 24 01:26:44 PM PDT 24
Finished Mar 24 01:55:50 PM PDT 24
Peak memory 364340 kb
Host smart-2b7f3118-6538-4d59-aef7-0330ffa15104
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2232326525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2232326525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.3886658393
Short name T670
Test name
Test status
Simulation time 72500095907 ps
CPU time 1443.74 seconds
Started Mar 24 01:26:43 PM PDT 24
Finished Mar 24 01:50:47 PM PDT 24
Peak memory 333436 kb
Host smart-5335a9d4-93e9-4e56-b22b-16609fa419d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3886658393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.3886658393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.1466034525
Short name T434
Test name
Test status
Simulation time 42534185689 ps
CPU time 895.99 seconds
Started Mar 24 01:26:44 PM PDT 24
Finished Mar 24 01:41:40 PM PDT 24
Peak memory 294604 kb
Host smart-de7340b9-0f0a-4c0c-9c05-e379c6dbd894
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1466034525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.1466034525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.2768113391
Short name T439
Test name
Test status
Simulation time 110120961355 ps
CPU time 4056.22 seconds
Started Mar 24 01:26:42 PM PDT 24
Finished Mar 24 02:34:20 PM PDT 24
Peak memory 646420 kb
Host smart-d3ded3a8-fc8f-4b6d-a5f7-e015514b40f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2768113391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2768113391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.1547015564
Short name T769
Test name
Test status
Simulation time 225708348423 ps
CPU time 4333.51 seconds
Started Mar 24 01:26:46 PM PDT 24
Finished Mar 24 02:39:00 PM PDT 24
Peak memory 560720 kb
Host smart-0934fea5-8a0e-4437-b532-7ad03f92b51c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1547015564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.1547015564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.547354966
Short name T740
Test name
Test status
Simulation time 26443236 ps
CPU time 0.81 seconds
Started Mar 24 01:27:01 PM PDT 24
Finished Mar 24 01:27:02 PM PDT 24
Peak memory 205740 kb
Host smart-238fedca-c7c7-4292-bcd2-f6e415dde72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547354966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.547354966 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.2831306386
Short name T425
Test name
Test status
Simulation time 27785966845 ps
CPU time 244.79 seconds
Started Mar 24 01:26:50 PM PDT 24
Finished Mar 24 01:30:56 PM PDT 24
Peak memory 242236 kb
Host smart-08257efa-02a8-45a5-9b2a-dac6410850a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831306386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2831306386 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.2778458204
Short name T1000
Test name
Test status
Simulation time 2205776725 ps
CPU time 93.02 seconds
Started Mar 24 01:26:49 PM PDT 24
Finished Mar 24 01:28:23 PM PDT 24
Peak memory 221360 kb
Host smart-d9b90104-6372-4044-9b8e-6b615edf0b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778458204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2778458204 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.862681313
Short name T1040
Test name
Test status
Simulation time 2037680237 ps
CPU time 38.6 seconds
Started Mar 24 01:26:58 PM PDT 24
Finished Mar 24 01:27:36 PM PDT 24
Peak memory 224216 kb
Host smart-b9a1502a-0107-4006-956d-64598fff3b38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=862681313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.862681313 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.1237974131
Short name T926
Test name
Test status
Simulation time 4336749155 ps
CPU time 27.71 seconds
Started Mar 24 01:26:59 PM PDT 24
Finished Mar 24 01:27:27 PM PDT 24
Peak memory 224320 kb
Host smart-b9f1569c-70a3-4a0b-a98d-692f4d1af2b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1237974131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1237974131 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.473685841
Short name T683
Test name
Test status
Simulation time 23923485178 ps
CPU time 294.08 seconds
Started Mar 24 01:26:53 PM PDT 24
Finished Mar 24 01:31:47 PM PDT 24
Peak memory 247908 kb
Host smart-e7c2bdce-5682-4f06-b1c1-cafee10a01c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473685841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.473685841 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.145850157
Short name T879
Test name
Test status
Simulation time 21344752903 ps
CPU time 422.86 seconds
Started Mar 24 01:26:53 PM PDT 24
Finished Mar 24 01:33:56 PM PDT 24
Peak memory 251744 kb
Host smart-a2cd29ce-2089-4133-9911-a67fdd8282d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145850157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.145850157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.2790756833
Short name T816
Test name
Test status
Simulation time 3440908450 ps
CPU time 5.88 seconds
Started Mar 24 01:26:53 PM PDT 24
Finished Mar 24 01:26:59 PM PDT 24
Peak memory 208092 kb
Host smart-0aa22e90-47b9-4214-9b8b-52a209793c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790756833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2790756833 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.3638819074
Short name T256
Test name
Test status
Simulation time 264882621346 ps
CPU time 2817.5 seconds
Started Mar 24 01:26:48 PM PDT 24
Finished Mar 24 02:13:46 PM PDT 24
Peak memory 466128 kb
Host smart-e50a33ff-f149-4f79-b6a5-919aa9b4270c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638819074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.3638819074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.2307688490
Short name T244
Test name
Test status
Simulation time 19148278638 ps
CPU time 400.91 seconds
Started Mar 24 01:26:50 PM PDT 24
Finished Mar 24 01:33:31 PM PDT 24
Peak memory 252960 kb
Host smart-ca6d8602-61fc-428e-9a72-76aacb01de0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307688490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2307688490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.4239065665
Short name T997
Test name
Test status
Simulation time 3401649854 ps
CPU time 28.38 seconds
Started Mar 24 01:26:48 PM PDT 24
Finished Mar 24 01:27:17 PM PDT 24
Peak memory 219308 kb
Host smart-e2f63bd2-50c6-469c-968a-db919c6f1dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239065665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.4239065665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.2525295849
Short name T189
Test name
Test status
Simulation time 3697951283 ps
CPU time 67.03 seconds
Started Mar 24 01:26:57 PM PDT 24
Finished Mar 24 01:28:04 PM PDT 24
Peak memory 248624 kb
Host smart-08161a7b-26e7-484e-996e-983f56e40fb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2525295849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2525295849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.508400475
Short name T1027
Test name
Test status
Simulation time 152485576 ps
CPU time 4.04 seconds
Started Mar 24 01:26:53 PM PDT 24
Finished Mar 24 01:26:57 PM PDT 24
Peak memory 216244 kb
Host smart-aed7c625-effd-42c6-8395-2167b11d9136
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508400475 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.kmac_test_vectors_kmac.508400475 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.657488794
Short name T788
Test name
Test status
Simulation time 956490076 ps
CPU time 4.48 seconds
Started Mar 24 01:26:55 PM PDT 24
Finished Mar 24 01:26:59 PM PDT 24
Peak memory 216276 kb
Host smart-6ceae46a-2192-4423-9baa-4a315f37a598
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657488794 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.kmac_test_vectors_kmac_xof.657488794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.24289519
Short name T297
Test name
Test status
Simulation time 43382118916 ps
CPU time 1496.66 seconds
Started Mar 24 01:26:52 PM PDT 24
Finished Mar 24 01:51:50 PM PDT 24
Peak memory 388968 kb
Host smart-7b976f8c-f5fd-4c45-949a-4de58ac7403c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=24289519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.24289519 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.1720879551
Short name T597
Test name
Test status
Simulation time 18593211407 ps
CPU time 1455.71 seconds
Started Mar 24 01:26:47 PM PDT 24
Finished Mar 24 01:51:03 PM PDT 24
Peak memory 377212 kb
Host smart-f8d4dd0e-7af9-44dd-814f-b397207e2045
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1720879551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1720879551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.3328749875
Short name T756
Test name
Test status
Simulation time 13822659022 ps
CPU time 1164.82 seconds
Started Mar 24 01:26:53 PM PDT 24
Finished Mar 24 01:46:18 PM PDT 24
Peak memory 339384 kb
Host smart-799f0094-3af8-4264-8a94-b742f9a18c90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3328749875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.3328749875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.3361516491
Short name T17
Test name
Test status
Simulation time 16534170691 ps
CPU time 783.67 seconds
Started Mar 24 01:26:53 PM PDT 24
Finished Mar 24 01:39:57 PM PDT 24
Peak memory 294036 kb
Host smart-7422dd13-f40d-49fa-98ea-d74a01dd8b42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3361516491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.3361516491 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.3867898143
Short name T619
Test name
Test status
Simulation time 51843777977 ps
CPU time 4003.8 seconds
Started Mar 24 01:26:54 PM PDT 24
Finished Mar 24 02:33:39 PM PDT 24
Peak memory 639752 kb
Host smart-5f8e1a33-5caa-426a-a9db-113d9f92bdd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3867898143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.3867898143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.289883695
Short name T859
Test name
Test status
Simulation time 744295597054 ps
CPU time 4046.77 seconds
Started Mar 24 01:26:54 PM PDT 24
Finished Mar 24 02:34:21 PM PDT 24
Peak memory 552400 kb
Host smart-936ff8f7-a487-469a-bb2e-e4d3381c892b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=289883695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.289883695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_app.2560307775
Short name T511
Test name
Test status
Simulation time 12128864502 ps
CPU time 111.8 seconds
Started Mar 24 01:27:02 PM PDT 24
Finished Mar 24 01:28:54 PM PDT 24
Peak memory 230284 kb
Host smart-6baaf97a-9d1f-4c00-b9cc-60a0d2c2474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560307775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2560307775 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.2212805684
Short name T484
Test name
Test status
Simulation time 2939410057 ps
CPU time 250.01 seconds
Started Mar 24 01:26:57 PM PDT 24
Finished Mar 24 01:31:07 PM PDT 24
Peak memory 227520 kb
Host smart-7e9d1d33-409a-4838-8f03-df3de1432833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212805684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2212805684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.3706638154
Short name T171
Test name
Test status
Simulation time 555826554 ps
CPU time 3.26 seconds
Started Mar 24 01:27:04 PM PDT 24
Finished Mar 24 01:27:08 PM PDT 24
Peak memory 216140 kb
Host smart-e5754ce2-6ebf-462c-861e-b11129403d1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3706638154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3706638154 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.3626797491
Short name T966
Test name
Test status
Simulation time 921203613 ps
CPU time 16.73 seconds
Started Mar 24 01:27:01 PM PDT 24
Finished Mar 24 01:27:18 PM PDT 24
Peak memory 224308 kb
Host smart-6b74b53d-cbe0-4228-942c-cf6fb7b139e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3626797491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3626797491 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.1342807697
Short name T1038
Test name
Test status
Simulation time 17638912613 ps
CPU time 89.68 seconds
Started Mar 24 01:27:01 PM PDT 24
Finished Mar 24 01:28:31 PM PDT 24
Peak memory 229500 kb
Host smart-59f5968b-1ce4-4aa9-8c6f-1bfeede6ccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342807697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1342807697 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.2014913673
Short name T630
Test name
Test status
Simulation time 31483644523 ps
CPU time 240.41 seconds
Started Mar 24 01:27:03 PM PDT 24
Finished Mar 24 01:31:03 PM PDT 24
Peak memory 250676 kb
Host smart-73b4f017-931d-4377-a434-6b96b468cdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014913673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2014913673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.721255756
Short name T470
Test name
Test status
Simulation time 3534755588 ps
CPU time 5.95 seconds
Started Mar 24 01:27:04 PM PDT 24
Finished Mar 24 01:27:10 PM PDT 24
Peak memory 207928 kb
Host smart-7c96ee4e-7408-4ae5-a966-dc6ecd936ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721255756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.721255756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.1617857589
Short name T61
Test name
Test status
Simulation time 103532172 ps
CPU time 1.25 seconds
Started Mar 24 01:27:00 PM PDT 24
Finished Mar 24 01:27:02 PM PDT 24
Peak memory 216152 kb
Host smart-8cf8cfab-1d81-47db-b767-23d68c4170a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617857589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1617857589 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.8162939
Short name T415
Test name
Test status
Simulation time 114640303536 ps
CPU time 1231.83 seconds
Started Mar 24 01:26:57 PM PDT 24
Finished Mar 24 01:47:30 PM PDT 24
Peak memory 328284 kb
Host smart-34b5ef9d-ba90-4306-a253-a8609c79ab0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8162939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_
output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_
output.8162939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.2196621353
Short name T991
Test name
Test status
Simulation time 130167930 ps
CPU time 2.53 seconds
Started Mar 24 01:26:57 PM PDT 24
Finished Mar 24 01:27:00 PM PDT 24
Peak memory 224396 kb
Host smart-bbc8d78d-b65e-4891-bc99-60a1c38fe037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196621353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2196621353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.3638305442
Short name T725
Test name
Test status
Simulation time 279464090 ps
CPU time 14.7 seconds
Started Mar 24 01:26:56 PM PDT 24
Finished Mar 24 01:27:11 PM PDT 24
Peak memory 218740 kb
Host smart-0198189b-ec89-40fd-9418-daae82b3e0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638305442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3638305442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.2526467705
Short name T43
Test name
Test status
Simulation time 265088654 ps
CPU time 7.72 seconds
Started Mar 24 01:27:07 PM PDT 24
Finished Mar 24 01:27:16 PM PDT 24
Peak memory 219136 kb
Host smart-ed56e3b6-6111-4793-862e-1ed7339f6910
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2526467705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2526467705 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1253948425
Short name T772
Test name
Test status
Simulation time 133162958 ps
CPU time 3.92 seconds
Started Mar 24 01:27:02 PM PDT 24
Finished Mar 24 01:27:06 PM PDT 24
Peak memory 216304 kb
Host smart-e9a713e3-498c-4a99-a609-b45665b9dc8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253948425 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1253948425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.2148821725
Short name T455
Test name
Test status
Simulation time 1024720168 ps
CPU time 5.05 seconds
Started Mar 24 01:27:01 PM PDT 24
Finished Mar 24 01:27:06 PM PDT 24
Peak memory 209276 kb
Host smart-dccc09bf-bfdc-4330-aac6-60ca0c80c33b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148821725 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.2148821725 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.578684990
Short name T272
Test name
Test status
Simulation time 78631811724 ps
CPU time 1578.73 seconds
Started Mar 24 01:27:01 PM PDT 24
Finished Mar 24 01:53:20 PM PDT 24
Peak memory 393648 kb
Host smart-312ed3a4-32ea-4bac-a858-42156884a0b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=578684990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.578684990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.2323104368
Short name T854
Test name
Test status
Simulation time 36580203346 ps
CPU time 1474.63 seconds
Started Mar 24 01:26:59 PM PDT 24
Finished Mar 24 01:51:34 PM PDT 24
Peak memory 377668 kb
Host smart-885db5e9-ed61-4fca-952e-c3a335a7a501
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2323104368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.2323104368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.2352819943
Short name T498
Test name
Test status
Simulation time 45954780425 ps
CPU time 1286.17 seconds
Started Mar 24 01:26:58 PM PDT 24
Finished Mar 24 01:48:25 PM PDT 24
Peak memory 330084 kb
Host smart-c2ad7310-9582-4117-a852-65abf602af7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2352819943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.2352819943 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.64407479
Short name T714
Test name
Test status
Simulation time 201249598110 ps
CPU time 962.71 seconds
Started Mar 24 01:26:59 PM PDT 24
Finished Mar 24 01:43:02 PM PDT 24
Peak memory 293720 kb
Host smart-39cc9ce5-f9c9-4b9f-8236-e5c1e84d2967
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=64407479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.64407479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.934170299
Short name T721
Test name
Test status
Simulation time 628199792558 ps
CPU time 3974.34 seconds
Started Mar 24 01:26:58 PM PDT 24
Finished Mar 24 02:33:12 PM PDT 24
Peak memory 556112 kb
Host smart-2f912727-27ed-4179-9c98-78fc7a8bfa27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=934170299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.934170299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.316726778
Short name T444
Test name
Test status
Simulation time 13845558 ps
CPU time 0.75 seconds
Started Mar 24 01:27:12 PM PDT 24
Finished Mar 24 01:27:14 PM PDT 24
Peak memory 205680 kb
Host smart-89ee9dcc-9b8b-4eb4-9c88-b8fed98d8c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316726778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.316726778 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.3918992574
Short name T173
Test name
Test status
Simulation time 4794889215 ps
CPU time 209.35 seconds
Started Mar 24 01:27:11 PM PDT 24
Finished Mar 24 01:30:40 PM PDT 24
Peak memory 244168 kb
Host smart-5f0dd52e-c5a7-4463-8c60-0f35534414ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918992574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3918992574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.3865275749
Short name T868
Test name
Test status
Simulation time 4332370110 ps
CPU time 347.64 seconds
Started Mar 24 01:27:08 PM PDT 24
Finished Mar 24 01:32:56 PM PDT 24
Peak memory 228184 kb
Host smart-47cb3a79-aa4a-4191-9b80-b17b9a2a5664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865275749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3865275749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.2462289875
Short name T857
Test name
Test status
Simulation time 1637925945 ps
CPU time 30 seconds
Started Mar 24 01:27:13 PM PDT 24
Finished Mar 24 01:27:43 PM PDT 24
Peak memory 224260 kb
Host smart-1e372bab-a32b-4442-9e60-07bdff9d47df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2462289875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2462289875 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.3404759905
Short name T860
Test name
Test status
Simulation time 388781205 ps
CPU time 16.93 seconds
Started Mar 24 01:27:10 PM PDT 24
Finished Mar 24 01:27:28 PM PDT 24
Peak memory 219368 kb
Host smart-7187805a-14f0-48f9-9e16-44104c6896b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3404759905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3404759905 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.3417903432
Short name T862
Test name
Test status
Simulation time 75297096840 ps
CPU time 294.69 seconds
Started Mar 24 01:27:14 PM PDT 24
Finished Mar 24 01:32:09 PM PDT 24
Peak memory 243004 kb
Host smart-001afed9-a470-45ad-a271-343d3db5833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417903432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3417903432 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.3565862379
Short name T694
Test name
Test status
Simulation time 3508775752 ps
CPU time 276.07 seconds
Started Mar 24 01:27:14 PM PDT 24
Finished Mar 24 01:31:51 PM PDT 24
Peak memory 255108 kb
Host smart-786f61a4-c766-4d2d-86dc-103194f8be44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565862379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3565862379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.2753620293
Short name T471
Test name
Test status
Simulation time 568515701 ps
CPU time 3.14 seconds
Started Mar 24 01:27:10 PM PDT 24
Finished Mar 24 01:27:14 PM PDT 24
Peak memory 207424 kb
Host smart-520228ff-1bb1-464b-bde6-25fb7e60cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753620293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2753620293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.2832251008
Short name T59
Test name
Test status
Simulation time 156291688 ps
CPU time 1.2 seconds
Started Mar 24 01:27:14 PM PDT 24
Finished Mar 24 01:27:17 PM PDT 24
Peak memory 216376 kb
Host smart-d20c2e58-cb26-469d-8bc9-a223f2e75550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832251008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2832251008 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1580145361
Short name T95
Test name
Test status
Simulation time 21821391178 ps
CPU time 257.01 seconds
Started Mar 24 01:27:08 PM PDT 24
Finished Mar 24 01:31:25 PM PDT 24
Peak memory 237536 kb
Host smart-89d3f8c6-ddfc-4ea2-a22a-4f13d5042632
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580145361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1580145361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.3565005452
Short name T577
Test name
Test status
Simulation time 2647993927 ps
CPU time 198.33 seconds
Started Mar 24 01:27:07 PM PDT 24
Finished Mar 24 01:30:26 PM PDT 24
Peak memory 239576 kb
Host smart-227af4f7-b723-4694-90a5-7ac04bdbe667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565005452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3565005452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.2245348045
Short name T373
Test name
Test status
Simulation time 5632392059 ps
CPU time 55.58 seconds
Started Mar 24 01:27:06 PM PDT 24
Finished Mar 24 01:28:02 PM PDT 24
Peak memory 217524 kb
Host smart-90a06c79-1a2c-4486-9598-722d03e9f6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245348045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2245348045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.768338552
Short name T959
Test name
Test status
Simulation time 9825626770 ps
CPU time 206.64 seconds
Started Mar 24 01:27:12 PM PDT 24
Finished Mar 24 01:30:39 PM PDT 24
Peak memory 273460 kb
Host smart-aa55ab3c-e636-49df-b84a-2b61af8e35b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=768338552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.768338552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.2161966718
Short name T255
Test name
Test status
Simulation time 494157713 ps
CPU time 4.7 seconds
Started Mar 24 01:27:07 PM PDT 24
Finished Mar 24 01:27:12 PM PDT 24
Peak memory 209260 kb
Host smart-7c39a5ad-8ffe-4a17-8b90-24ddfa7e4fc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161966718 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.2161966718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.2625149767
Short name T685
Test name
Test status
Simulation time 288119361 ps
CPU time 3.93 seconds
Started Mar 24 01:27:11 PM PDT 24
Finished Mar 24 01:27:15 PM PDT 24
Peak memory 216220 kb
Host smart-dba1008f-8d2b-498e-a113-5807da4d1dc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625149767 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.2625149767 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.3758212571
Short name T958
Test name
Test status
Simulation time 401239347821 ps
CPU time 1957.26 seconds
Started Mar 24 01:27:09 PM PDT 24
Finished Mar 24 01:59:46 PM PDT 24
Peak memory 389076 kb
Host smart-e56f0368-dc9e-44f9-a071-f418abe085f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3758212571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3758212571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.3545769630
Short name T982
Test name
Test status
Simulation time 293563523816 ps
CPU time 1911.89 seconds
Started Mar 24 01:27:07 PM PDT 24
Finished Mar 24 01:58:59 PM PDT 24
Peak memory 374188 kb
Host smart-8afe38d9-df05-4d27-a074-4c6bc55e13b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3545769630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.3545769630 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.1832387840
Short name T983
Test name
Test status
Simulation time 55419238261 ps
CPU time 1133.64 seconds
Started Mar 24 01:27:07 PM PDT 24
Finished Mar 24 01:46:02 PM PDT 24
Peak memory 328604 kb
Host smart-617cfb17-d469-4b10-92db-acaaaea8f9dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1832387840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1832387840 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.356265312
Short name T464
Test name
Test status
Simulation time 133879488743 ps
CPU time 882.06 seconds
Started Mar 24 01:27:08 PM PDT 24
Finished Mar 24 01:41:50 PM PDT 24
Peak memory 292612 kb
Host smart-6c616c35-dce0-455f-9df6-90fc5e45977a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=356265312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.356265312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.527492767
Short name T587
Test name
Test status
Simulation time 349608996111 ps
CPU time 5004.33 seconds
Started Mar 24 01:27:09 PM PDT 24
Finished Mar 24 02:50:34 PM PDT 24
Peak memory 648404 kb
Host smart-8ecb232f-4188-42ac-942c-33709b6ed21a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=527492767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.527492767 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.1299612965
Short name T955
Test name
Test status
Simulation time 218892276460 ps
CPU time 4574.53 seconds
Started Mar 24 01:27:06 PM PDT 24
Finished Mar 24 02:43:22 PM PDT 24
Peak memory 569796 kb
Host smart-94082e16-ae75-41b0-8f3f-a825bc06f309
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1299612965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1299612965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.1017965413
Short name T852
Test name
Test status
Simulation time 15250030 ps
CPU time 0.79 seconds
Started Mar 24 01:27:21 PM PDT 24
Finished Mar 24 01:27:22 PM PDT 24
Peak memory 205728 kb
Host smart-f0a78a40-1c96-4593-89a5-ec8807c54b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017965413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1017965413 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.1030111807
Short name T834
Test name
Test status
Simulation time 2311307907 ps
CPU time 62.21 seconds
Started Mar 24 01:27:16 PM PDT 24
Finished Mar 24 01:28:20 PM PDT 24
Peak memory 225184 kb
Host smart-b48b2144-496a-4598-8fdc-9f7dc703f62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030111807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1030111807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.3863186427
Short name T720
Test name
Test status
Simulation time 707149484 ps
CPU time 20.75 seconds
Started Mar 24 01:27:13 PM PDT 24
Finished Mar 24 01:27:34 PM PDT 24
Peak memory 222472 kb
Host smart-12cdfbe4-15fe-4847-ae0c-011076f8b124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863186427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3863186427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.4183635502
Short name T712
Test name
Test status
Simulation time 4393378708 ps
CPU time 32.68 seconds
Started Mar 24 01:27:18 PM PDT 24
Finished Mar 24 01:27:51 PM PDT 24
Peak memory 224636 kb
Host smart-ccd078f4-5218-4f89-abb8-195338e27b39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4183635502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.4183635502 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.3791523636
Short name T468
Test name
Test status
Simulation time 201564351 ps
CPU time 13.98 seconds
Started Mar 24 01:27:15 PM PDT 24
Finished Mar 24 01:27:31 PM PDT 24
Peak memory 224228 kb
Host smart-0d15ef83-dd84-47d1-9da5-9d2aee2d6446
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3791523636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3791523636 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.3996705423
Short name T190
Test name
Test status
Simulation time 114851682092 ps
CPU time 231.04 seconds
Started Mar 24 01:27:20 PM PDT 24
Finished Mar 24 01:31:13 PM PDT 24
Peak memory 236636 kb
Host smart-aab6a8c6-983c-4656-a8d8-21762be56a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996705423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3996705423 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.225697084
Short name T819
Test name
Test status
Simulation time 26102040105 ps
CPU time 188.17 seconds
Started Mar 24 01:27:16 PM PDT 24
Finished Mar 24 01:30:26 PM PDT 24
Peak memory 249112 kb
Host smart-8af5cbfa-a407-4c2d-bfda-a6404bc47135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225697084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.225697084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.3189085453
Short name T627
Test name
Test status
Simulation time 2341290587 ps
CPU time 4.04 seconds
Started Mar 24 01:27:17 PM PDT 24
Finished Mar 24 01:27:22 PM PDT 24
Peak memory 207896 kb
Host smart-200339aa-6bc1-41ed-81bf-d4dd2182b7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189085453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3189085453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.3348793655
Short name T6
Test name
Test status
Simulation time 989335027 ps
CPU time 42.65 seconds
Started Mar 24 01:27:19 PM PDT 24
Finished Mar 24 01:28:02 PM PDT 24
Peak memory 232912 kb
Host smart-dd83a806-9966-4803-964a-2622ba9fb35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348793655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3348793655 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.2533412031
Short name T947
Test name
Test status
Simulation time 2918476989 ps
CPU time 67.88 seconds
Started Mar 24 01:27:14 PM PDT 24
Finished Mar 24 01:28:23 PM PDT 24
Peak memory 223392 kb
Host smart-5f31862f-53f9-4e17-8d9c-69f94114cb43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533412031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.2533412031 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.186433304
Short name T520
Test name
Test status
Simulation time 2593823966 ps
CPU time 199.13 seconds
Started Mar 24 01:27:11 PM PDT 24
Finished Mar 24 01:30:31 PM PDT 24
Peak memory 238864 kb
Host smart-e3a36d75-8277-4a2f-8094-4231e5e8366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186433304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.186433304 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.846681567
Short name T787
Test name
Test status
Simulation time 5227447344 ps
CPU time 36.97 seconds
Started Mar 24 01:27:15 PM PDT 24
Finished Mar 24 01:27:54 PM PDT 24
Peak memory 216360 kb
Host smart-a57011e5-06c2-44c4-932a-6e11d0082ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846681567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.846681567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.659066223
Short name T519
Test name
Test status
Simulation time 43832231812 ps
CPU time 1564.97 seconds
Started Mar 24 01:27:22 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 427168 kb
Host smart-9b3ff042-9342-4beb-979f-20aee0f1e192
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=659066223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.659066223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.2580343969
Short name T514
Test name
Test status
Simulation time 542776350 ps
CPU time 5.01 seconds
Started Mar 24 01:27:16 PM PDT 24
Finished Mar 24 01:27:23 PM PDT 24
Peak memory 216268 kb
Host smart-c142bd60-1e14-4093-9a3c-b442f40c7cfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580343969 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.2580343969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.303547304
Short name T618
Test name
Test status
Simulation time 1438358411 ps
CPU time 5.35 seconds
Started Mar 24 01:27:19 PM PDT 24
Finished Mar 24 01:27:25 PM PDT 24
Peak memory 209728 kb
Host smart-f8a9caef-520a-4f9f-a2d1-b062520d9343
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303547304 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.kmac_test_vectors_kmac_xof.303547304 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.4142451353
Short name T356
Test name
Test status
Simulation time 390913069970 ps
CPU time 2114.9 seconds
Started Mar 24 01:27:10 PM PDT 24
Finished Mar 24 02:02:26 PM PDT 24
Peak memory 394488 kb
Host smart-b81d26b0-5453-4666-ae4b-83583a0c50f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4142451353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.4142451353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3349210684
Short name T325
Test name
Test status
Simulation time 17397353352 ps
CPU time 1478.35 seconds
Started Mar 24 01:27:15 PM PDT 24
Finished Mar 24 01:51:56 PM PDT 24
Peak memory 364344 kb
Host smart-0f14e2b8-0293-491d-9e8a-018690321148
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3349210684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3349210684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.696041115
Short name T754
Test name
Test status
Simulation time 180199537313 ps
CPU time 1387.08 seconds
Started Mar 24 01:27:14 PM PDT 24
Finished Mar 24 01:50:22 PM PDT 24
Peak memory 335324 kb
Host smart-9accef0f-5a4e-4abf-b18e-dd73700ab9a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=696041115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.696041115 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.3081119963
Short name T1057
Test name
Test status
Simulation time 9276842945 ps
CPU time 741.73 seconds
Started Mar 24 01:27:13 PM PDT 24
Finished Mar 24 01:39:36 PM PDT 24
Peak memory 290604 kb
Host smart-85c064d3-b2d7-47cd-8358-1a0411efcfeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3081119963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.3081119963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.4059656721
Short name T753
Test name
Test status
Simulation time 626607387668 ps
CPU time 4338.63 seconds
Started Mar 24 01:27:16 PM PDT 24
Finished Mar 24 02:39:37 PM PDT 24
Peak memory 553972 kb
Host smart-6db9e0d0-1cb2-4d2a-8949-f65d5b00991b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4059656721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.4059656721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.2920879907
Short name T234
Test name
Test status
Simulation time 38680264 ps
CPU time 0.75 seconds
Started Mar 24 01:27:27 PM PDT 24
Finished Mar 24 01:27:28 PM PDT 24
Peak memory 205672 kb
Host smart-c99b2aff-9995-45f7-855a-1f8f0f6ee4f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920879907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2920879907 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.127077493
Short name T609
Test name
Test status
Simulation time 10920617858 ps
CPU time 52.08 seconds
Started Mar 24 01:27:29 PM PDT 24
Finished Mar 24 01:28:22 PM PDT 24
Peak memory 224836 kb
Host smart-bc58b7ee-3bc2-43e4-acac-bdb5091c7a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127077493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.127077493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.1375050539
Short name T1072
Test name
Test status
Simulation time 94038469265 ps
CPU time 682.2 seconds
Started Mar 24 01:27:25 PM PDT 24
Finished Mar 24 01:38:47 PM PDT 24
Peak memory 232784 kb
Host smart-337bc6da-093d-48b8-9b58-fab11f7605e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375050539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1375050539 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.1287971075
Short name T516
Test name
Test status
Simulation time 624720021 ps
CPU time 12.69 seconds
Started Mar 24 01:27:26 PM PDT 24
Finished Mar 24 01:27:39 PM PDT 24
Peak memory 219532 kb
Host smart-18b81882-2c6e-425c-b395-7303270acab8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1287971075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1287971075 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.3134587737
Short name T1025
Test name
Test status
Simulation time 468396498 ps
CPU time 31.99 seconds
Started Mar 24 01:27:26 PM PDT 24
Finished Mar 24 01:27:58 PM PDT 24
Peak memory 224232 kb
Host smart-0893871f-e8ee-4e37-b4ac-d7cc0fb64a36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3134587737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3134587737 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.939797398
Short name T952
Test name
Test status
Simulation time 3907626793 ps
CPU time 121.53 seconds
Started Mar 24 01:27:28 PM PDT 24
Finished Mar 24 01:29:29 PM PDT 24
Peak memory 235936 kb
Host smart-424eec72-1dc8-4917-b250-d01dab4a2913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939797398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.939797398 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.182799687
Short name T192
Test name
Test status
Simulation time 17333101277 ps
CPU time 350.79 seconds
Started Mar 24 01:27:26 PM PDT 24
Finished Mar 24 01:33:17 PM PDT 24
Peak memory 273596 kb
Host smart-8d715923-3e83-4dec-b164-edd4e75ab446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182799687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.182799687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.2208107870
Short name T733
Test name
Test status
Simulation time 147779490 ps
CPU time 1.31 seconds
Started Mar 24 01:27:28 PM PDT 24
Finished Mar 24 01:27:29 PM PDT 24
Peak memory 216224 kb
Host smart-1b45c63c-ee9b-4822-aa47-088979153bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208107870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2208107870 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.1501894079
Short name T946
Test name
Test status
Simulation time 36374183013 ps
CPU time 1051.4 seconds
Started Mar 24 01:27:24 PM PDT 24
Finished Mar 24 01:44:56 PM PDT 24
Peak memory 323072 kb
Host smart-200a1ded-bdd2-4124-9244-3f07be7bf181
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501894079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.1501894079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.2496513702
Short name T936
Test name
Test status
Simulation time 58083925785 ps
CPU time 322.15 seconds
Started Mar 24 01:27:21 PM PDT 24
Finished Mar 24 01:32:45 PM PDT 24
Peak memory 241392 kb
Host smart-495b6e49-45bf-4e95-9bda-51c385a70f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496513702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2496513702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.2926296426
Short name T1039
Test name
Test status
Simulation time 5484826552 ps
CPU time 36.06 seconds
Started Mar 24 01:27:23 PM PDT 24
Finished Mar 24 01:27:59 PM PDT 24
Peak memory 222388 kb
Host smart-76fe0d68-4be2-45cd-9206-0ab53f2a381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926296426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2926296426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.256403462
Short name T201
Test name
Test status
Simulation time 38044827223 ps
CPU time 718.28 seconds
Started Mar 24 01:27:27 PM PDT 24
Finished Mar 24 01:39:25 PM PDT 24
Peak memory 305556 kb
Host smart-37bb61d1-2861-4cdd-9be2-cfda2e5882ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=256403462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.256403462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.1883230966
Short name T562
Test name
Test status
Simulation time 1016185124 ps
CPU time 4.86 seconds
Started Mar 24 01:27:27 PM PDT 24
Finished Mar 24 01:27:32 PM PDT 24
Peak memory 216276 kb
Host smart-0891e25b-60b4-434b-8751-ea629fb9e306
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883230966 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.1883230966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.872889042
Short name T318
Test name
Test status
Simulation time 267195193 ps
CPU time 4.89 seconds
Started Mar 24 01:27:27 PM PDT 24
Finished Mar 24 01:27:32 PM PDT 24
Peak memory 216292 kb
Host smart-8dea525b-b070-4049-a999-6b072cb16d74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872889042 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.kmac_test_vectors_kmac_xof.872889042 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.2745530372
Short name T975
Test name
Test status
Simulation time 71574205435 ps
CPU time 1488.43 seconds
Started Mar 24 01:27:25 PM PDT 24
Finished Mar 24 01:52:13 PM PDT 24
Peak memory 387448 kb
Host smart-dafc0ed6-a11f-47e7-a719-890bc6ee323e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2745530372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.2745530372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.1864112295
Short name T604
Test name
Test status
Simulation time 72069119636 ps
CPU time 1460.26 seconds
Started Mar 24 01:27:24 PM PDT 24
Finished Mar 24 01:51:45 PM PDT 24
Peak memory 387740 kb
Host smart-ceced636-3be9-4643-b99a-c163c873c285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1864112295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.1864112295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3791775861
Short name T2
Test name
Test status
Simulation time 14021997106 ps
CPU time 1083.02 seconds
Started Mar 24 01:27:22 PM PDT 24
Finished Mar 24 01:45:26 PM PDT 24
Peak memory 331716 kb
Host smart-55990c1c-6a64-443b-843d-b6efd66e3c96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3791775861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3791775861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.320844067
Short name T605
Test name
Test status
Simulation time 558593838663 ps
CPU time 1158.42 seconds
Started Mar 24 01:27:21 PM PDT 24
Finished Mar 24 01:46:40 PM PDT 24
Peak memory 300776 kb
Host smart-11d3d031-6400-4988-91e2-d2c1214ae25e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=320844067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.320844067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.943480683
Short name T388
Test name
Test status
Simulation time 711989445981 ps
CPU time 5120.7 seconds
Started Mar 24 01:27:22 PM PDT 24
Finished Mar 24 02:52:44 PM PDT 24
Peak memory 643832 kb
Host smart-f6cfd8db-f6b8-4bd4-9a94-b592ef57c5bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=943480683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.943480683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.1252001844
Short name T183
Test name
Test status
Simulation time 179729287284 ps
CPU time 3504.77 seconds
Started Mar 24 01:27:27 PM PDT 24
Finished Mar 24 02:25:52 PM PDT 24
Peak memory 558044 kb
Host smart-97d76b59-832d-4e76-bc3a-6a0ba61dab65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1252001844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.1252001844 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.1081099395
Short name T293
Test name
Test status
Simulation time 63605814 ps
CPU time 0.81 seconds
Started Mar 24 01:27:39 PM PDT 24
Finished Mar 24 01:27:39 PM PDT 24
Peak memory 205704 kb
Host smart-3342cea2-94cd-421f-91d9-b9e8a693ddc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081099395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1081099395 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3660413022
Short name T77
Test name
Test status
Simulation time 4560006440 ps
CPU time 82.04 seconds
Started Mar 24 01:27:34 PM PDT 24
Finished Mar 24 01:28:56 PM PDT 24
Peak memory 228444 kb
Host smart-4df5fab6-21c4-4e8d-b7c2-defff145128b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660413022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3660413022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2816940771
Short name T199
Test name
Test status
Simulation time 7405246355 ps
CPU time 302.91 seconds
Started Mar 24 01:27:26 PM PDT 24
Finished Mar 24 01:32:30 PM PDT 24
Peak memory 226528 kb
Host smart-40f03807-9eca-42cc-8a39-e9145b289751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816940771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2816940771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.2891118216
Short name T911
Test name
Test status
Simulation time 684396250 ps
CPU time 10.74 seconds
Started Mar 24 01:27:34 PM PDT 24
Finished Mar 24 01:27:45 PM PDT 24
Peak memory 224308 kb
Host smart-e074ad34-849b-4ee9-a91c-6e50ceb0be35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2891118216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2891118216 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.3079060372
Short name T443
Test name
Test status
Simulation time 42861214 ps
CPU time 3.22 seconds
Started Mar 24 01:27:34 PM PDT 24
Finished Mar 24 01:27:37 PM PDT 24
Peak memory 216104 kb
Host smart-8d55346c-8b50-4006-b716-550cbf0a6c5c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3079060372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3079060372 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.2390182617
Short name T547
Test name
Test status
Simulation time 17554926283 ps
CPU time 280.56 seconds
Started Mar 24 01:27:33 PM PDT 24
Finished Mar 24 01:32:14 PM PDT 24
Peak memory 243808 kb
Host smart-36e53b97-c6ca-4fc3-bb4d-74f5202061f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390182617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2390182617 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_key_error.1015658199
Short name T532
Test name
Test status
Simulation time 2581567600 ps
CPU time 6.91 seconds
Started Mar 24 01:27:32 PM PDT 24
Finished Mar 24 01:27:39 PM PDT 24
Peak memory 207900 kb
Host smart-2e72fc03-46d5-427e-baff-ef3a132082e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015658199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1015658199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.2055709457
Short name T40
Test name
Test status
Simulation time 7366063140 ps
CPU time 20.9 seconds
Started Mar 24 01:27:33 PM PDT 24
Finished Mar 24 01:27:54 PM PDT 24
Peak memory 232752 kb
Host smart-e459512a-08a5-4f72-a61a-7686d1ace834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055709457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2055709457 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.3888137711
Short name T371
Test name
Test status
Simulation time 15909412811 ps
CPU time 1235.13 seconds
Started Mar 24 01:27:27 PM PDT 24
Finished Mar 24 01:48:02 PM PDT 24
Peak memory 348928 kb
Host smart-45f20b71-0579-4018-828b-b6de4ee33190
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888137711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.3888137711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.3148873285
Short name T1004
Test name
Test status
Simulation time 12493050909 ps
CPU time 159.37 seconds
Started Mar 24 01:27:28 PM PDT 24
Finished Mar 24 01:30:08 PM PDT 24
Peak memory 236080 kb
Host smart-4f7ecb2c-82ea-4c32-bb30-0c5be9cb50e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148873285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3148873285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.597758316
Short name T476
Test name
Test status
Simulation time 1904895225 ps
CPU time 39.5 seconds
Started Mar 24 01:27:26 PM PDT 24
Finished Mar 24 01:28:06 PM PDT 24
Peak memory 219252 kb
Host smart-d975f72a-466d-49f8-95da-388f2f244b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597758316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.597758316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.2820214064
Short name T931
Test name
Test status
Simulation time 68179884234 ps
CPU time 226.88 seconds
Started Mar 24 01:27:32 PM PDT 24
Finished Mar 24 01:31:19 PM PDT 24
Peak memory 266564 kb
Host smart-f969fd01-a9a5-433a-927f-0cdef2bfed90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2820214064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.2820214064 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.1259467567
Short name T450
Test name
Test status
Simulation time 896573943 ps
CPU time 4.44 seconds
Started Mar 24 01:27:34 PM PDT 24
Finished Mar 24 01:27:38 PM PDT 24
Peak memory 216472 kb
Host smart-52ff710f-fabb-4e80-b373-c150e47cb31f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259467567 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.1259467567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3262461533
Short name T372
Test name
Test status
Simulation time 2360863970 ps
CPU time 4.8 seconds
Started Mar 24 01:27:34 PM PDT 24
Finished Mar 24 01:27:39 PM PDT 24
Peak memory 209612 kb
Host smart-90fa52a8-ca75-4d18-b9e3-f68a3a80ef33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262461533 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3262461533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.1811843366
Short name T894
Test name
Test status
Simulation time 927936621488 ps
CPU time 2124.19 seconds
Started Mar 24 01:27:27 PM PDT 24
Finished Mar 24 02:02:52 PM PDT 24
Peak memory 392360 kb
Host smart-904d77ae-7818-4423-a080-c557a4ee34a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1811843366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.1811843366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.4149416955
Short name T838
Test name
Test status
Simulation time 71172923145 ps
CPU time 1405.59 seconds
Started Mar 24 01:27:26 PM PDT 24
Finished Mar 24 01:50:52 PM PDT 24
Peak memory 375516 kb
Host smart-710caa4d-5f85-4264-96cf-515f21e00791
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4149416955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.4149416955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.2367029431
Short name T459
Test name
Test status
Simulation time 13704361244 ps
CPU time 1143.16 seconds
Started Mar 24 01:27:34 PM PDT 24
Finished Mar 24 01:46:37 PM PDT 24
Peak memory 336964 kb
Host smart-ef8748f7-4326-4375-9d9f-34ec8e495426
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2367029431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.2367029431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.4016722435
Short name T813
Test name
Test status
Simulation time 24801177044 ps
CPU time 768.1 seconds
Started Mar 24 01:27:33 PM PDT 24
Finished Mar 24 01:40:22 PM PDT 24
Peak memory 293924 kb
Host smart-56792572-3262-4681-951c-158f04a53cd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4016722435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.4016722435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.126866484
Short name T820
Test name
Test status
Simulation time 530978081784 ps
CPU time 5455.83 seconds
Started Mar 24 01:27:33 PM PDT 24
Finished Mar 24 02:58:30 PM PDT 24
Peak memory 643416 kb
Host smart-f2f92bc0-5d3a-4c0b-b69f-148f66d66868
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=126866484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.126866484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.788934061
Short name T73
Test name
Test status
Simulation time 45604250509 ps
CPU time 3461.51 seconds
Started Mar 24 01:27:33 PM PDT 24
Finished Mar 24 02:25:15 PM PDT 24
Peak memory 572248 kb
Host smart-3db94bf6-e487-459a-b72f-7921fd5453bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=788934061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.788934061 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.435982537
Short name T1037
Test name
Test status
Simulation time 29345863 ps
CPU time 0.83 seconds
Started Mar 24 01:25:27 PM PDT 24
Finished Mar 24 01:25:28 PM PDT 24
Peak memory 205724 kb
Host smart-1485a2c8-9649-4a04-a6be-93e730175a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435982537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.435982537 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.4059158166
Short name T376
Test name
Test status
Simulation time 29142127817 ps
CPU time 181.69 seconds
Started Mar 24 01:25:24 PM PDT 24
Finished Mar 24 01:28:26 PM PDT 24
Peak memory 240792 kb
Host smart-7d324ad7-4d45-43c4-8cc6-28f880d4ca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059158166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.4059158166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2924740077
Short name T927
Test name
Test status
Simulation time 2727373882 ps
CPU time 47.06 seconds
Started Mar 24 01:25:20 PM PDT 24
Finished Mar 24 01:26:08 PM PDT 24
Peak memory 222476 kb
Host smart-2d706ad7-2961-460d-bde3-715579520ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924740077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2924740077 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.675930375
Short name T613
Test name
Test status
Simulation time 12998020771 ps
CPU time 519.29 seconds
Started Mar 24 01:25:18 PM PDT 24
Finished Mar 24 01:33:57 PM PDT 24
Peak memory 231036 kb
Host smart-339ea54f-154b-43be-abff-a11a21d403aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675930375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.675930375 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.1220085130
Short name T309
Test name
Test status
Simulation time 1602482029 ps
CPU time 21.22 seconds
Started Mar 24 01:25:25 PM PDT 24
Finished Mar 24 01:25:47 PM PDT 24
Peak memory 221000 kb
Host smart-6cfd3bc1-195a-42ef-9701-c3a6f1065228
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1220085130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1220085130 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.1701948978
Short name T738
Test name
Test status
Simulation time 6952316452 ps
CPU time 33.8 seconds
Started Mar 24 01:25:19 PM PDT 24
Finished Mar 24 01:25:53 PM PDT 24
Peak memory 225376 kb
Host smart-b7a02c5a-a61c-41b0-b83f-a9bcb15fd1f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1701948978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1701948978 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.1019742415
Short name T305
Test name
Test status
Simulation time 3296003670 ps
CPU time 31.58 seconds
Started Mar 24 01:25:20 PM PDT 24
Finished Mar 24 01:25:52 PM PDT 24
Peak memory 224568 kb
Host smart-51328e41-5a34-4ce0-bfe0-c5f3b21e9baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019742415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1019742415 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.4290958239
Short name T901
Test name
Test status
Simulation time 25444675263 ps
CPU time 56.93 seconds
Started Mar 24 01:25:20 PM PDT 24
Finished Mar 24 01:26:17 PM PDT 24
Peak memory 224392 kb
Host smart-629fc620-9369-4af9-b56b-02e0df0a7772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290958239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.4290958239 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.4185466069
Short name T598
Test name
Test status
Simulation time 17486448432 ps
CPU time 94.95 seconds
Started Mar 24 01:25:23 PM PDT 24
Finished Mar 24 01:26:58 PM PDT 24
Peak memory 240924 kb
Host smart-a5b55535-3a69-4be8-81f7-226245a34547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185466069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.4185466069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.2830543236
Short name T855
Test name
Test status
Simulation time 1923585368 ps
CPU time 2.89 seconds
Started Mar 24 01:25:20 PM PDT 24
Finished Mar 24 01:25:23 PM PDT 24
Peak memory 207456 kb
Host smart-bb3915b4-9e6a-4f84-b137-c47fcaeaa764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830543236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2830543236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.1210663334
Short name T505
Test name
Test status
Simulation time 163413221 ps
CPU time 6.58 seconds
Started Mar 24 01:25:24 PM PDT 24
Finished Mar 24 01:25:31 PM PDT 24
Peak memory 220588 kb
Host smart-9cd81282-85aa-4e2b-95d3-a887faac50fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210663334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1210663334 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.1336614687
Short name T647
Test name
Test status
Simulation time 25792454341 ps
CPU time 407.93 seconds
Started Mar 24 01:25:16 PM PDT 24
Finished Mar 24 01:32:04 PM PDT 24
Peak memory 256636 kb
Host smart-ce4c0e2e-978f-462d-96e0-b5bca4918b06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336614687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.1336614687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.4053665979
Short name T29
Test name
Test status
Simulation time 11579884837 ps
CPU time 206.92 seconds
Started Mar 24 01:25:21 PM PDT 24
Finished Mar 24 01:28:48 PM PDT 24
Peak memory 239864 kb
Host smart-ee670039-b984-4766-9f56-6f55bb60eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053665979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.4053665979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.2260975643
Short name T70
Test name
Test status
Simulation time 12563877723 ps
CPU time 58.23 seconds
Started Mar 24 01:25:27 PM PDT 24
Finished Mar 24 01:26:25 PM PDT 24
Peak memory 263848 kb
Host smart-82ce2dac-936c-42fb-8d6a-7023c53930ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260975643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2260975643 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.441691267
Short name T316
Test name
Test status
Simulation time 5410898056 ps
CPU time 136.5 seconds
Started Mar 24 01:25:19 PM PDT 24
Finished Mar 24 01:27:36 PM PDT 24
Peak memory 231800 kb
Host smart-4adc90b8-6131-4e82-b680-e50a5ba36151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441691267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.441691267 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.3031358751
Short name T392
Test name
Test status
Simulation time 969074194 ps
CPU time 24.38 seconds
Started Mar 24 01:25:18 PM PDT 24
Finished Mar 24 01:25:43 PM PDT 24
Peak memory 217420 kb
Host smart-0d35be3d-d13d-4d1c-9139-12a0e0e9cad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031358751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3031358751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.368540502
Short name T667
Test name
Test status
Simulation time 4180103998 ps
CPU time 59.04 seconds
Started Mar 24 01:25:28 PM PDT 24
Finished Mar 24 01:26:27 PM PDT 24
Peak memory 236436 kb
Host smart-6f35933c-f902-4ce9-b129-8b0f7490f0ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=368540502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.368540502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.3417192658
Short name T635
Test name
Test status
Simulation time 290627680 ps
CPU time 4.23 seconds
Started Mar 24 01:25:19 PM PDT 24
Finished Mar 24 01:25:24 PM PDT 24
Peak memory 216188 kb
Host smart-2da3020b-2d7a-4b01-a938-c60162500104
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417192658 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.3417192658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.2466464070
Short name T653
Test name
Test status
Simulation time 935391772 ps
CPU time 4.97 seconds
Started Mar 24 01:25:25 PM PDT 24
Finished Mar 24 01:25:30 PM PDT 24
Peak memory 209332 kb
Host smart-df348016-fdd6-4cd9-ae79-03c15705db1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466464070 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2466464070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.2502601614
Short name T693
Test name
Test status
Simulation time 40356014299 ps
CPU time 1564.75 seconds
Started Mar 24 01:25:23 PM PDT 24
Finished Mar 24 01:51:28 PM PDT 24
Peak memory 395220 kb
Host smart-7a5bf665-a9f8-4be0-80b4-7486b2f8fe26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2502601614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2502601614 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.3198366776
Short name T615
Test name
Test status
Simulation time 18061682298 ps
CPU time 1297.09 seconds
Started Mar 24 01:25:20 PM PDT 24
Finished Mar 24 01:46:58 PM PDT 24
Peak memory 366636 kb
Host smart-3d3f0be7-a471-467d-ae85-ec78ffa308d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3198366776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3198366776 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.1636718723
Short name T648
Test name
Test status
Simulation time 14031361914 ps
CPU time 1155.69 seconds
Started Mar 24 01:25:21 PM PDT 24
Finished Mar 24 01:44:37 PM PDT 24
Peak memory 331400 kb
Host smart-8a029ed0-b9c7-495e-b150-105bd3864607
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1636718723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1636718723 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.2676480772
Short name T533
Test name
Test status
Simulation time 40149654335 ps
CPU time 838.92 seconds
Started Mar 24 01:25:20 PM PDT 24
Finished Mar 24 01:39:19 PM PDT 24
Peak memory 298484 kb
Host smart-44f84316-b142-4f38-a6a0-a3e9e10403b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2676480772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2676480772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.2963789583
Short name T435
Test name
Test status
Simulation time 257578110391 ps
CPU time 5169.44 seconds
Started Mar 24 01:25:19 PM PDT 24
Finished Mar 24 02:51:30 PM PDT 24
Peak memory 653812 kb
Host smart-0cab3c38-e433-4e04-aa6f-8e075d3dfc1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2963789583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2963789583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.908332897
Short name T78
Test name
Test status
Simulation time 43223332093 ps
CPU time 3519.18 seconds
Started Mar 24 01:25:22 PM PDT 24
Finished Mar 24 02:24:02 PM PDT 24
Peak memory 563048 kb
Host smart-6246e328-ff1d-4673-868a-94febbf621b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=908332897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.908332897 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.2155326980
Short name T457
Test name
Test status
Simulation time 74274829 ps
CPU time 0.76 seconds
Started Mar 24 01:27:44 PM PDT 24
Finished Mar 24 01:27:45 PM PDT 24
Peak memory 205732 kb
Host smart-834b6496-05f5-4e9a-8dac-ce375cc843ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155326980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2155326980 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.1293447592
Short name T691
Test name
Test status
Simulation time 1178695154 ps
CPU time 56.11 seconds
Started Mar 24 01:27:38 PM PDT 24
Finished Mar 24 01:28:34 PM PDT 24
Peak memory 225608 kb
Host smart-de62f1a8-badc-48a1-8117-2b2c9f7ceb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293447592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1293447592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.1198830161
Short name T447
Test name
Test status
Simulation time 13402634301 ps
CPU time 387.08 seconds
Started Mar 24 01:27:37 PM PDT 24
Finished Mar 24 01:34:04 PM PDT 24
Peak memory 229904 kb
Host smart-12782958-422c-4c58-b0ca-a4d4360d5cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198830161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1198830161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.2892094991
Short name T944
Test name
Test status
Simulation time 32968369319 ps
CPU time 127.02 seconds
Started Mar 24 01:27:42 PM PDT 24
Finished Mar 24 01:29:49 PM PDT 24
Peak memory 232424 kb
Host smart-000ee2a4-246b-42d8-af7b-3c32b582d5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892094991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2892094991 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.1248001294
Short name T815
Test name
Test status
Simulation time 1625357932 ps
CPU time 60.91 seconds
Started Mar 24 01:27:51 PM PDT 24
Finished Mar 24 01:28:52 PM PDT 24
Peak memory 235268 kb
Host smart-0686a222-509c-4433-a777-d5841902d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248001294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1248001294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.3591410065
Short name T853
Test name
Test status
Simulation time 1001746564 ps
CPU time 5.54 seconds
Started Mar 24 01:27:42 PM PDT 24
Finished Mar 24 01:27:48 PM PDT 24
Peak memory 207600 kb
Host smart-bc839d4c-4dec-4627-bf2d-2be0f5175157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591410065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3591410065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.2104750597
Short name T526
Test name
Test status
Simulation time 51334611 ps
CPU time 1.28 seconds
Started Mar 24 01:27:51 PM PDT 24
Finished Mar 24 01:27:53 PM PDT 24
Peak memory 216140 kb
Host smart-91be176a-ebc6-4ea3-8d6d-6463b66f585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104750597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2104750597 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.3053277357
Short name T222
Test name
Test status
Simulation time 32928637251 ps
CPU time 1468.35 seconds
Started Mar 24 01:27:36 PM PDT 24
Finished Mar 24 01:52:05 PM PDT 24
Peak memory 373880 kb
Host smart-1442efeb-3108-423a-acaa-ae5bc47f5336
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053277357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.3053277357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.1598247955
Short name T1002
Test name
Test status
Simulation time 23334493010 ps
CPU time 156.41 seconds
Started Mar 24 01:27:38 PM PDT 24
Finished Mar 24 01:30:14 PM PDT 24
Peak memory 234660 kb
Host smart-07676dc2-0b85-45f3-b795-67d3336c7db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598247955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1598247955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.447743757
Short name T245
Test name
Test status
Simulation time 5118924731 ps
CPU time 19.88 seconds
Started Mar 24 01:27:37 PM PDT 24
Finished Mar 24 01:27:57 PM PDT 24
Peak memory 219848 kb
Host smart-f06e3804-a16e-4d87-b3d8-9f6fcfe0fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447743757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.447743757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.3084431515
Short name T521
Test name
Test status
Simulation time 125981522823 ps
CPU time 614.49 seconds
Started Mar 24 01:27:44 PM PDT 24
Finished Mar 24 01:37:58 PM PDT 24
Peak memory 315928 kb
Host smart-b00e5abe-8d6c-409d-9f73-6c444bd9df80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3084431515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3084431515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.4232480513
Short name T1022
Test name
Test status
Simulation time 1174171128 ps
CPU time 4.53 seconds
Started Mar 24 01:27:39 PM PDT 24
Finished Mar 24 01:27:44 PM PDT 24
Peak memory 216276 kb
Host smart-fae044bc-f5bf-4439-8aad-90a54bddb512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232480513 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.4232480513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.335766678
Short name T641
Test name
Test status
Simulation time 241516210 ps
CPU time 4.23 seconds
Started Mar 24 01:27:38 PM PDT 24
Finished Mar 24 01:27:43 PM PDT 24
Peak memory 216528 kb
Host smart-daf79998-497d-4b5f-b0cb-803fc21cea04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335766678 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.kmac_test_vectors_kmac_xof.335766678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.1405954485
Short name T980
Test name
Test status
Simulation time 257054019489 ps
CPU time 1907.68 seconds
Started Mar 24 01:27:38 PM PDT 24
Finished Mar 24 01:59:26 PM PDT 24
Peak memory 389460 kb
Host smart-ed33a826-fabe-45d3-af09-6bfc2504ceba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1405954485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.1405954485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.1732680822
Short name T170
Test name
Test status
Simulation time 121392168340 ps
CPU time 1616.19 seconds
Started Mar 24 01:27:38 PM PDT 24
Finished Mar 24 01:54:35 PM PDT 24
Peak memory 372840 kb
Host smart-fc99f966-1cf8-4be9-acf5-635d4a920deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1732680822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.1732680822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.2323353838
Short name T728
Test name
Test status
Simulation time 24334564123 ps
CPU time 1091.01 seconds
Started Mar 24 01:27:38 PM PDT 24
Finished Mar 24 01:45:49 PM PDT 24
Peak memory 326016 kb
Host smart-77bb5a7d-2003-4f7f-b6db-577ad9bccbb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2323353838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.2323353838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.1463717302
Short name T654
Test name
Test status
Simulation time 136063634431 ps
CPU time 953.51 seconds
Started Mar 24 01:27:38 PM PDT 24
Finished Mar 24 01:43:32 PM PDT 24
Peak memory 295736 kb
Host smart-370521ce-f19e-4044-9ab9-0f1f1acfb995
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1463717302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.1463717302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.1666954476
Short name T257
Test name
Test status
Simulation time 962600661447 ps
CPU time 5491.86 seconds
Started Mar 24 01:27:37 PM PDT 24
Finished Mar 24 02:59:10 PM PDT 24
Peak memory 663060 kb
Host smart-b18e3b4b-2ed0-4796-92f2-602733df237c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1666954476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.1666954476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.2272299030
Short name T895
Test name
Test status
Simulation time 694239061997 ps
CPU time 3993.9 seconds
Started Mar 24 01:27:37 PM PDT 24
Finished Mar 24 02:34:12 PM PDT 24
Peak memory 564392 kb
Host smart-fa9bb159-8886-4875-8163-95c2df2eb1b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2272299030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.2272299030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.854282496
Short name T250
Test name
Test status
Simulation time 18393093 ps
CPU time 0.83 seconds
Started Mar 24 01:27:51 PM PDT 24
Finished Mar 24 01:27:52 PM PDT 24
Peak memory 205676 kb
Host smart-8f50f347-2409-48ed-b062-4e1e104b47ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854282496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.854282496 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.2962875617
Short name T809
Test name
Test status
Simulation time 18510373787 ps
CPU time 78.23 seconds
Started Mar 24 01:27:47 PM PDT 24
Finished Mar 24 01:29:06 PM PDT 24
Peak memory 227944 kb
Host smart-ae1483b2-a351-4962-81f3-e561f953e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962875617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2962875617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.3836810723
Short name T645
Test name
Test status
Simulation time 61072312282 ps
CPU time 741.79 seconds
Started Mar 24 01:27:41 PM PDT 24
Finished Mar 24 01:40:03 PM PDT 24
Peak memory 234916 kb
Host smart-24503ab6-c548-42fb-b7d9-6e12f4122006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836810723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3836810723 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.740343696
Short name T280
Test name
Test status
Simulation time 2061207311 ps
CPU time 36.4 seconds
Started Mar 24 01:27:46 PM PDT 24
Finished Mar 24 01:28:23 PM PDT 24
Peak memory 224464 kb
Host smart-6886cb58-2b9b-43e4-8e36-b95f70faf689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740343696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.740343696 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_key_error.1266306539
Short name T71
Test name
Test status
Simulation time 949172976 ps
CPU time 5.16 seconds
Started Mar 24 01:27:51 PM PDT 24
Finished Mar 24 01:27:56 PM PDT 24
Peak memory 207744 kb
Host smart-cb98b0a3-26c2-40c8-96d6-e4998f4a7e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266306539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1266306539 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.3687839080
Short name T643
Test name
Test status
Simulation time 190757595 ps
CPU time 1.38 seconds
Started Mar 24 01:27:51 PM PDT 24
Finished Mar 24 01:27:53 PM PDT 24
Peak memory 220768 kb
Host smart-bbe33e87-5ebd-45f6-9419-eb5fe97f01a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687839080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3687839080 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.1184283327
Short name T624
Test name
Test status
Simulation time 8027670361 ps
CPU time 666.55 seconds
Started Mar 24 01:27:43 PM PDT 24
Finished Mar 24 01:38:49 PM PDT 24
Peak memory 293520 kb
Host smart-24af67db-0b87-4792-ba1e-7ee531c940a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184283327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.1184283327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.3310102164
Short name T1029
Test name
Test status
Simulation time 16286115556 ps
CPU time 322.34 seconds
Started Mar 24 01:27:51 PM PDT 24
Finished Mar 24 01:33:13 PM PDT 24
Peak memory 243872 kb
Host smart-36ee97b2-7179-4629-8574-651ae0050bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310102164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3310102164 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.344898435
Short name T976
Test name
Test status
Simulation time 1490255711 ps
CPU time 9.26 seconds
Started Mar 24 01:27:51 PM PDT 24
Finished Mar 24 01:28:00 PM PDT 24
Peak memory 222404 kb
Host smart-e25ab6d1-d1f8-41e7-9b74-ee8db2b607ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344898435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.344898435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.3333928320
Short name T687
Test name
Test status
Simulation time 92151327938 ps
CPU time 480.86 seconds
Started Mar 24 01:27:50 PM PDT 24
Finished Mar 24 01:35:51 PM PDT 24
Peak memory 290320 kb
Host smart-a4e3c2ba-44d9-4f6a-8a2d-f19db8821180
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3333928320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3333928320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.926927439
Short name T875
Test name
Test status
Simulation time 424992415 ps
CPU time 4.08 seconds
Started Mar 24 01:27:45 PM PDT 24
Finished Mar 24 01:27:50 PM PDT 24
Peak memory 216152 kb
Host smart-c5cc658f-9be0-4eee-8956-e2de1a69c16b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926927439 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.kmac_test_vectors_kmac.926927439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.1442686349
Short name T341
Test name
Test status
Simulation time 756098859 ps
CPU time 4.41 seconds
Started Mar 24 01:27:45 PM PDT 24
Finished Mar 24 01:27:50 PM PDT 24
Peak memory 216264 kb
Host smart-80ecce7c-1d8d-4ff6-8a4e-5dd0804d759b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442686349 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.1442686349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.3795266959
Short name T231
Test name
Test status
Simulation time 33028250130 ps
CPU time 1495.88 seconds
Started Mar 24 01:27:49 PM PDT 24
Finished Mar 24 01:52:45 PM PDT 24
Peak memory 392224 kb
Host smart-fb378a91-cfac-49c8-b8ce-590ab41fdeb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3795266959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.3795266959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.3478988377
Short name T710
Test name
Test status
Simulation time 73805276732 ps
CPU time 1486.92 seconds
Started Mar 24 01:27:43 PM PDT 24
Finished Mar 24 01:52:30 PM PDT 24
Peak memory 374920 kb
Host smart-eb804cb3-8ea5-4106-94bb-f3dc024a713b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3478988377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3478988377 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.528594370
Short name T252
Test name
Test status
Simulation time 27661358230 ps
CPU time 1133.81 seconds
Started Mar 24 01:27:46 PM PDT 24
Finished Mar 24 01:46:40 PM PDT 24
Peak memory 333252 kb
Host smart-1223676d-984a-4bcc-8225-e4bb369f10a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=528594370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.528594370 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.3375495711
Short name T512
Test name
Test status
Simulation time 366576637902 ps
CPU time 1080.91 seconds
Started Mar 24 01:27:47 PM PDT 24
Finished Mar 24 01:45:49 PM PDT 24
Peak memory 297784 kb
Host smart-b7631fa7-a44e-42d8-b5b0-9319feb41e36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3375495711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3375495711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.2560497427
Short name T572
Test name
Test status
Simulation time 1225818037020 ps
CPU time 4807.55 seconds
Started Mar 24 01:27:48 PM PDT 24
Finished Mar 24 02:47:56 PM PDT 24
Peak memory 649808 kb
Host smart-5e4961e9-5223-4c51-ad27-59746da13e31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2560497427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.2560497427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_alert_test.3096423950
Short name T52
Test name
Test status
Simulation time 21279628 ps
CPU time 0.81 seconds
Started Mar 24 01:28:01 PM PDT 24
Finished Mar 24 01:28:02 PM PDT 24
Peak memory 205704 kb
Host smart-138af1bc-34e7-4317-9f6a-814f31008553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096423950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3096423950 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.1888362358
Short name T878
Test name
Test status
Simulation time 12864708848 ps
CPU time 68.58 seconds
Started Mar 24 01:27:57 PM PDT 24
Finished Mar 24 01:29:06 PM PDT 24
Peak memory 226380 kb
Host smart-b5b4340f-5d05-4bf3-a2b5-e1df9510080c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888362358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1888362358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.3367663276
Short name T804
Test name
Test status
Simulation time 8354262590 ps
CPU time 738.28 seconds
Started Mar 24 01:27:51 PM PDT 24
Finished Mar 24 01:40:10 PM PDT 24
Peak memory 232408 kb
Host smart-d129af53-dc76-447d-89c8-47dd0a0e4d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367663276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.3367663276 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.2245165579
Short name T120
Test name
Test status
Simulation time 6515044011 ps
CPU time 109.96 seconds
Started Mar 24 01:28:01 PM PDT 24
Finished Mar 24 01:29:51 PM PDT 24
Peak memory 232348 kb
Host smart-5d7a100e-8cfd-4035-9faa-ccda0f1caa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245165579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2245165579 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.3921406855
Short name T1070
Test name
Test status
Simulation time 14900728330 ps
CPU time 180.6 seconds
Started Mar 24 01:28:01 PM PDT 24
Finished Mar 24 01:31:02 PM PDT 24
Peak memory 252248 kb
Host smart-4675d04a-b3b1-4d56-bf33-09a85f5e64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921406855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3921406855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.1992784092
Short name T585
Test name
Test status
Simulation time 357640015 ps
CPU time 2.31 seconds
Started Mar 24 01:28:01 PM PDT 24
Finished Mar 24 01:28:03 PM PDT 24
Peak memory 207596 kb
Host smart-dad4722d-fd93-4632-bc74-5aae33ab9156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992784092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1992784092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.2130640885
Short name T38
Test name
Test status
Simulation time 39188705 ps
CPU time 1.11 seconds
Started Mar 24 01:28:00 PM PDT 24
Finished Mar 24 01:28:01 PM PDT 24
Peak memory 216200 kb
Host smart-d5bcbd8e-db99-4be8-bb96-72608986972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130640885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2130640885 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1472735007
Short name T383
Test name
Test status
Simulation time 44522515853 ps
CPU time 1204.2 seconds
Started Mar 24 01:27:52 PM PDT 24
Finished Mar 24 01:47:56 PM PDT 24
Peak memory 338980 kb
Host smart-6dbc3438-f332-4018-ab41-f44ca24ae0dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472735007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1472735007 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2371068036
Short name T922
Test name
Test status
Simulation time 22735729204 ps
CPU time 221.18 seconds
Started Mar 24 01:27:50 PM PDT 24
Finished Mar 24 01:31:32 PM PDT 24
Peak memory 238360 kb
Host smart-3acf13a9-1bd2-419a-91e3-4c2a42032929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371068036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2371068036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.639312915
Short name T437
Test name
Test status
Simulation time 4119989050 ps
CPU time 53.55 seconds
Started Mar 24 01:27:51 PM PDT 24
Finished Mar 24 01:28:45 PM PDT 24
Peak memory 221768 kb
Host smart-bf4e26d7-0e30-44b1-9aa9-57db1da483d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639312915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.639312915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.4146341756
Short name T460
Test name
Test status
Simulation time 38289535388 ps
CPU time 667.53 seconds
Started Mar 24 01:28:03 PM PDT 24
Finished Mar 24 01:39:10 PM PDT 24
Peak memory 314992 kb
Host smart-6ba87ca8-bcc4-4089-bdfa-eb637168c90d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4146341756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.4146341756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.1574749212
Short name T177
Test name
Test status
Simulation time 231666130 ps
CPU time 4.39 seconds
Started Mar 24 01:27:57 PM PDT 24
Finished Mar 24 01:28:01 PM PDT 24
Peak memory 216296 kb
Host smart-b50952ae-23c2-49f3-82f8-d7922c717ba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574749212 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.1574749212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.1630862861
Short name T730
Test name
Test status
Simulation time 666511367 ps
CPU time 4.69 seconds
Started Mar 24 01:27:55 PM PDT 24
Finished Mar 24 01:28:00 PM PDT 24
Peak memory 209384 kb
Host smart-5c351d7d-837b-4372-b49d-df4b42065fab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630862861 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.1630862861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.112616253
Short name T126
Test name
Test status
Simulation time 75540939164 ps
CPU time 1658.99 seconds
Started Mar 24 01:27:52 PM PDT 24
Finished Mar 24 01:55:31 PM PDT 24
Peak memory 393492 kb
Host smart-41b37a6e-71c1-4fcd-9e4d-a5d8d2e0537f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=112616253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.112616253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.1830368922
Short name T430
Test name
Test status
Simulation time 17540919318 ps
CPU time 1424.15 seconds
Started Mar 24 01:27:50 PM PDT 24
Finished Mar 24 01:51:34 PM PDT 24
Peak memory 370272 kb
Host smart-d457703d-de1c-4eed-b238-c2348fdf5fa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1830368922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.1830368922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.1327817522
Short name T298
Test name
Test status
Simulation time 51679740911 ps
CPU time 1143.67 seconds
Started Mar 24 01:27:55 PM PDT 24
Finished Mar 24 01:46:58 PM PDT 24
Peak memory 342208 kb
Host smart-4b10628f-19be-431c-b0f1-b1b5146b2942
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1327817522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.1327817522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.3560733119
Short name T599
Test name
Test status
Simulation time 34075768994 ps
CPU time 949.35 seconds
Started Mar 24 01:27:57 PM PDT 24
Finished Mar 24 01:43:46 PM PDT 24
Peak memory 296048 kb
Host smart-b5c85d60-ee31-4b3b-ac9a-946cbb83015a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3560733119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.3560733119 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.1111943057
Short name T395
Test name
Test status
Simulation time 2461132924966 ps
CPU time 4735.91 seconds
Started Mar 24 01:27:56 PM PDT 24
Finished Mar 24 02:46:53 PM PDT 24
Peak memory 654356 kb
Host smart-4dfb593e-1479-4b7f-9cca-d8adb720ab75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1111943057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1111943057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.4000963798
Short name T91
Test name
Test status
Simulation time 900727515088 ps
CPU time 4432.89 seconds
Started Mar 24 01:27:56 PM PDT 24
Finished Mar 24 02:41:49 PM PDT 24
Peak memory 560092 kb
Host smart-a915c47b-750c-4bab-b5a5-aa1793df4967
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4000963798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.4000963798 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.890930830
Short name T125
Test name
Test status
Simulation time 45033820 ps
CPU time 0.81 seconds
Started Mar 24 01:28:10 PM PDT 24
Finished Mar 24 01:28:11 PM PDT 24
Peak memory 205720 kb
Host smart-4898ccd2-228b-446c-8ac6-a03c901a83f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890930830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.890930830 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.397608241
Short name T317
Test name
Test status
Simulation time 26284301016 ps
CPU time 72.43 seconds
Started Mar 24 01:28:10 PM PDT 24
Finished Mar 24 01:29:22 PM PDT 24
Peak memory 226664 kb
Host smart-198112a9-e489-4b93-a20f-28ae7179650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397608241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.397608241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.3858085116
Short name T479
Test name
Test status
Simulation time 2084792836 ps
CPU time 56.87 seconds
Started Mar 24 01:28:05 PM PDT 24
Finished Mar 24 01:29:02 PM PDT 24
Peak memory 224484 kb
Host smart-ff51059c-d312-4ac2-8549-f1ffb739163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858085116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3858085116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_error.4106855208
Short name T912
Test name
Test status
Simulation time 26146979097 ps
CPU time 246.58 seconds
Started Mar 24 01:28:11 PM PDT 24
Finished Mar 24 01:32:18 PM PDT 24
Peak memory 253084 kb
Host smart-eedcf029-de32-49f7-a356-57b3c132328a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106855208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.4106855208 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.2479481739
Short name T63
Test name
Test status
Simulation time 2978993683 ps
CPU time 4.27 seconds
Started Mar 24 01:28:11 PM PDT 24
Finished Mar 24 01:28:15 PM PDT 24
Peak memory 207896 kb
Host smart-f1714dae-fe22-416e-abdb-04c7c09c1d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479481739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2479481739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.2391576858
Short name T998
Test name
Test status
Simulation time 66759323883 ps
CPU time 1494.78 seconds
Started Mar 24 01:28:06 PM PDT 24
Finished Mar 24 01:53:01 PM PDT 24
Peak memory 349576 kb
Host smart-2c603623-a166-4e7c-9c19-aebb30bea205
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391576858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.2391576858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.2300046333
Short name T417
Test name
Test status
Simulation time 30125716953 ps
CPU time 314.76 seconds
Started Mar 24 01:28:04 PM PDT 24
Finished Mar 24 01:33:19 PM PDT 24
Peak memory 247940 kb
Host smart-75c4cf24-a888-43e1-ba57-8fc92b9479aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300046333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2300046333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.3025142427
Short name T702
Test name
Test status
Simulation time 1663567033 ps
CPU time 19.73 seconds
Started Mar 24 01:28:00 PM PDT 24
Finished Mar 24 01:28:20 PM PDT 24
Peak memory 217460 kb
Host smart-6b48847e-0582-41e4-aa4c-240689823518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025142427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3025142427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.3207272704
Short name T806
Test name
Test status
Simulation time 40825344673 ps
CPU time 1175.05 seconds
Started Mar 24 01:28:10 PM PDT 24
Finished Mar 24 01:47:45 PM PDT 24
Peak memory 347636 kb
Host smart-721b8bc7-acf1-4df2-b229-b0a4c43e9005
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3207272704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3207272704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_stress_all_with_rand_reset.920292913
Short name T54
Test name
Test status
Simulation time 63720819399 ps
CPU time 432.9 seconds
Started Mar 24 01:28:11 PM PDT 24
Finished Mar 24 01:35:24 PM PDT 24
Peak memory 281964 kb
Host smart-3ac8c91a-6ba3-452e-9bb2-2355c7635af3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920292913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.920292913 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.1951220359
Short name T375
Test name
Test status
Simulation time 386873911 ps
CPU time 4.87 seconds
Started Mar 24 01:28:10 PM PDT 24
Finished Mar 24 01:28:15 PM PDT 24
Peak memory 209696 kb
Host smart-9c44e621-dc29-45ba-a8a4-80531bb0919f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951220359 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.1951220359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.1256747199
Short name T269
Test name
Test status
Simulation time 254938904 ps
CPU time 3.95 seconds
Started Mar 24 01:28:09 PM PDT 24
Finished Mar 24 01:28:13 PM PDT 24
Peak memory 216288 kb
Host smart-258abcab-98a8-46ba-bea8-884107042b2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256747199 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.1256747199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.2938335339
Short name T330
Test name
Test status
Simulation time 101118276307 ps
CPU time 1966.8 seconds
Started Mar 24 01:28:05 PM PDT 24
Finished Mar 24 02:00:52 PM PDT 24
Peak memory 400164 kb
Host smart-36fe8099-6a46-4aca-9bf9-ccefd318cf9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2938335339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.2938335339 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.3850101390
Short name T918
Test name
Test status
Simulation time 73344357749 ps
CPU time 1521.61 seconds
Started Mar 24 01:28:06 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 372160 kb
Host smart-f8576b9c-35a8-4197-ac52-9ca43ff7c1b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3850101390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.3850101390 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.3537863348
Short name T302
Test name
Test status
Simulation time 185026770157 ps
CPU time 1313.28 seconds
Started Mar 24 01:28:04 PM PDT 24
Finished Mar 24 01:49:58 PM PDT 24
Peak memory 331752 kb
Host smart-b386a53c-03ef-4998-8431-d6846d254b12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3537863348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.3537863348 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.624541696
Short name T1008
Test name
Test status
Simulation time 9889244133 ps
CPU time 828.01 seconds
Started Mar 24 01:28:04 PM PDT 24
Finished Mar 24 01:41:52 PM PDT 24
Peak memory 291536 kb
Host smart-73f3eee2-292c-4fd1-a438-ab8ef1e0e0f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=624541696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.624541696 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.835543688
Short name T421
Test name
Test status
Simulation time 212500271097 ps
CPU time 4047.88 seconds
Started Mar 24 01:28:09 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 653596 kb
Host smart-a60b8d00-d42d-42ed-9e45-f4331c4f4abd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=835543688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.835543688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.2691474013
Short name T406
Test name
Test status
Simulation time 434902440958 ps
CPU time 4360.76 seconds
Started Mar 24 01:28:09 PM PDT 24
Finished Mar 24 02:40:51 PM PDT 24
Peak memory 565804 kb
Host smart-9ba16846-1598-4580-bee4-3b24fded58fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2691474013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.2691474013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.1136700667
Short name T620
Test name
Test status
Simulation time 17739432 ps
CPU time 0.8 seconds
Started Mar 24 01:28:20 PM PDT 24
Finished Mar 24 01:28:21 PM PDT 24
Peak memory 205740 kb
Host smart-74be1a39-aac0-4473-9dc1-f3d23275942f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136700667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.1136700667 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.2985789219
Short name T954
Test name
Test status
Simulation time 24813098324 ps
CPU time 314.13 seconds
Started Mar 24 01:28:15 PM PDT 24
Finished Mar 24 01:33:29 PM PDT 24
Peak memory 248140 kb
Host smart-65a319e7-db18-47ed-9b5f-3ba59673907a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985789219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2985789219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.1506182872
Short name T543
Test name
Test status
Simulation time 2630059597 ps
CPU time 109.07 seconds
Started Mar 24 01:28:15 PM PDT 24
Finished Mar 24 01:30:04 PM PDT 24
Peak memory 224516 kb
Host smart-62b7cfb6-0cb1-4f73-9231-9ffd0712669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506182872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1506182872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.3027441422
Short name T391
Test name
Test status
Simulation time 5921742970 ps
CPU time 135.97 seconds
Started Mar 24 01:28:14 PM PDT 24
Finished Mar 24 01:30:30 PM PDT 24
Peak memory 237032 kb
Host smart-0d9d7763-a58a-4575-8c5a-f8fd03e5c1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027441422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3027441422 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.2569288255
Short name T515
Test name
Test status
Simulation time 760213842 ps
CPU time 16.38 seconds
Started Mar 24 01:28:20 PM PDT 24
Finished Mar 24 01:28:36 PM PDT 24
Peak memory 234496 kb
Host smart-82892683-ca2c-4a07-b82d-c29beb2583b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569288255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2569288255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.1067651353
Short name T502
Test name
Test status
Simulation time 2781397309 ps
CPU time 4.22 seconds
Started Mar 24 01:28:19 PM PDT 24
Finished Mar 24 01:28:24 PM PDT 24
Peak memory 207896 kb
Host smart-33b7050f-0718-4259-b9cb-3cddd0ff075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067651353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1067651353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.994695343
Short name T8
Test name
Test status
Simulation time 170508594 ps
CPU time 1.17 seconds
Started Mar 24 01:28:21 PM PDT 24
Finished Mar 24 01:28:22 PM PDT 24
Peak memory 216208 kb
Host smart-a9906b2c-95e9-44e3-9b42-4bc18e5553d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994695343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.994695343 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.4198703121
Short name T632
Test name
Test status
Simulation time 107110695406 ps
CPU time 2390.12 seconds
Started Mar 24 01:28:09 PM PDT 24
Finished Mar 24 02:08:00 PM PDT 24
Peak memory 468124 kb
Host smart-c194fd31-10fa-4af5-b1e3-29012fadc446
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198703121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.4198703121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.458586789
Short name T948
Test name
Test status
Simulation time 20072889542 ps
CPU time 365.61 seconds
Started Mar 24 01:28:10 PM PDT 24
Finished Mar 24 01:34:16 PM PDT 24
Peak memory 251120 kb
Host smart-a95735a6-57a7-4934-ab48-d23087e6e049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458586789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.458586789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.613654185
Short name T697
Test name
Test status
Simulation time 3569723957 ps
CPU time 19.47 seconds
Started Mar 24 01:28:12 PM PDT 24
Finished Mar 24 01:28:31 PM PDT 24
Peak memory 219648 kb
Host smart-8e06db69-0a65-4135-a406-bffd8d2f232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613654185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.613654185 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.1644263239
Short name T422
Test name
Test status
Simulation time 5977151891 ps
CPU time 471.75 seconds
Started Mar 24 01:28:19 PM PDT 24
Finished Mar 24 01:36:11 PM PDT 24
Peak memory 278672 kb
Host smart-6a451478-7e18-417f-934c-4997edb69eb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1644263239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1644263239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.3613811177
Short name T659
Test name
Test status
Simulation time 125928379 ps
CPU time 3.71 seconds
Started Mar 24 01:28:15 PM PDT 24
Finished Mar 24 01:28:19 PM PDT 24
Peak memory 209248 kb
Host smart-ea9c5c6d-a334-461f-afc7-bbb95eceec24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613811177 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.3613811177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.588943950
Short name T732
Test name
Test status
Simulation time 237273531 ps
CPU time 3.95 seconds
Started Mar 24 01:28:15 PM PDT 24
Finished Mar 24 01:28:19 PM PDT 24
Peak memory 216528 kb
Host smart-02c5369d-71af-41e8-a2fe-266ac2b2bc38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588943950 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.kmac_test_vectors_kmac_xof.588943950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.1518917439
Short name T263
Test name
Test status
Simulation time 130548442439 ps
CPU time 1851.25 seconds
Started Mar 24 01:28:15 PM PDT 24
Finished Mar 24 01:59:06 PM PDT 24
Peak memory 387500 kb
Host smart-3e631af3-6866-4879-87e2-3405e12862c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1518917439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.1518917439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.2918884136
Short name T626
Test name
Test status
Simulation time 36727270221 ps
CPU time 1464.72 seconds
Started Mar 24 01:28:15 PM PDT 24
Finished Mar 24 01:52:40 PM PDT 24
Peak memory 372968 kb
Host smart-b8f29dfe-6bf9-4fb4-88d6-0021af2dc7f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2918884136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.2918884136 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.485588526
Short name T612
Test name
Test status
Simulation time 10091773466 ps
CPU time 812.64 seconds
Started Mar 24 01:28:17 PM PDT 24
Finished Mar 24 01:41:50 PM PDT 24
Peak memory 298044 kb
Host smart-bf158e94-a22c-4bb2-a392-018e1de5b1de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=485588526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.485588526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.4205844237
Short name T953
Test name
Test status
Simulation time 202230034672 ps
CPU time 4264.08 seconds
Started Mar 24 01:28:15 PM PDT 24
Finished Mar 24 02:39:20 PM PDT 24
Peak memory 644528 kb
Host smart-cf6e77ca-714f-449d-8a01-78d9f8b6ce11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4205844237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.4205844237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.1246428026
Short name T253
Test name
Test status
Simulation time 386852625708 ps
CPU time 4110.1 seconds
Started Mar 24 01:28:13 PM PDT 24
Finished Mar 24 02:36:44 PM PDT 24
Peak memory 567948 kb
Host smart-e8007d72-c977-4c7b-8f23-3320659395d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1246428026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1246428026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.457475093
Short name T1018
Test name
Test status
Simulation time 14132562 ps
CPU time 0.76 seconds
Started Mar 24 01:28:28 PM PDT 24
Finished Mar 24 01:28:29 PM PDT 24
Peak memory 205676 kb
Host smart-2d35ac46-0d4e-4b56-8dc9-23a00b3cd918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457475093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.457475093 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_burst_write.2242973697
Short name T243
Test name
Test status
Simulation time 88367910563 ps
CPU time 607.91 seconds
Started Mar 24 01:28:25 PM PDT 24
Finished Mar 24 01:38:33 PM PDT 24
Peak memory 231412 kb
Host smart-97ce2dc6-e015-4ef5-a546-25f8551d4d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242973697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2242973697 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.367786964
Short name T747
Test name
Test status
Simulation time 52653482790 ps
CPU time 244.87 seconds
Started Mar 24 01:28:25 PM PDT 24
Finished Mar 24 01:32:31 PM PDT 24
Peak memory 242604 kb
Host smart-5d4156d0-7f27-485e-9333-98ccce42811b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367786964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.367786964 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_key_error.3492517025
Short name T64
Test name
Test status
Simulation time 6919127477 ps
CPU time 5.86 seconds
Started Mar 24 01:28:28 PM PDT 24
Finished Mar 24 01:28:34 PM PDT 24
Peak memory 207896 kb
Host smart-dabb9eb1-2b3d-4071-afd5-840f344b3517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492517025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3492517025 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.2298313465
Short name T308
Test name
Test status
Simulation time 3393896625 ps
CPU time 21.44 seconds
Started Mar 24 01:28:28 PM PDT 24
Finished Mar 24 01:28:50 PM PDT 24
Peak memory 232824 kb
Host smart-1659b548-6b08-477f-b49b-e91a117f1b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298313465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2298313465 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.3404512982
Short name T882
Test name
Test status
Simulation time 191278068936 ps
CPU time 2346.52 seconds
Started Mar 24 01:28:19 PM PDT 24
Finished Mar 24 02:07:26 PM PDT 24
Peak memory 412504 kb
Host smart-9b43e077-0963-480c-bf59-a703f1780e6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404512982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.3404512982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.1301811729
Short name T782
Test name
Test status
Simulation time 42564332868 ps
CPU time 297.71 seconds
Started Mar 24 01:28:19 PM PDT 24
Finished Mar 24 01:33:17 PM PDT 24
Peak memory 242488 kb
Host smart-76491615-a4cd-4bda-97e2-4de9a1888e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301811729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.1301811729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.3245508349
Short name T822
Test name
Test status
Simulation time 5337590396 ps
CPU time 47.75 seconds
Started Mar 24 01:28:19 PM PDT 24
Finished Mar 24 01:29:07 PM PDT 24
Peak memory 219352 kb
Host smart-72747533-49eb-43a2-94e4-fec8c167922a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245508349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3245508349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3403597935
Short name T945
Test name
Test status
Simulation time 27045006192 ps
CPU time 732.71 seconds
Started Mar 24 01:28:28 PM PDT 24
Finished Mar 24 01:40:41 PM PDT 24
Peak memory 321104 kb
Host smart-c3f6ca3e-a4ff-4e5b-a87d-c829fe3106d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3403597935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3403597935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_stress_all_with_rand_reset.4157156926
Short name T55
Test name
Test status
Simulation time 81623396572 ps
CPU time 1573.55 seconds
Started Mar 24 01:28:29 PM PDT 24
Finished Mar 24 01:54:43 PM PDT 24
Peak memory 355104 kb
Host smart-cc38b5c4-7460-4b0a-9377-68eb9bfa6bcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157156926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.4157156926 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.2082049441
Short name T846
Test name
Test status
Simulation time 1600762249 ps
CPU time 4.62 seconds
Started Mar 24 01:28:24 PM PDT 24
Finished Mar 24 01:28:28 PM PDT 24
Peak memory 216288 kb
Host smart-45c39f4b-bebb-40f6-ad01-365d2deac6f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082049441 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.2082049441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.938669585
Short name T832
Test name
Test status
Simulation time 65595655 ps
CPU time 4.04 seconds
Started Mar 24 01:28:25 PM PDT 24
Finished Mar 24 01:28:29 PM PDT 24
Peak memory 216236 kb
Host smart-498a0ca3-c31e-4b1e-a87b-ee194e62eb40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938669585 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.kmac_test_vectors_kmac_xof.938669585 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.838517737
Short name T544
Test name
Test status
Simulation time 897304960335 ps
CPU time 2070.33 seconds
Started Mar 24 01:28:23 PM PDT 24
Finished Mar 24 02:02:54 PM PDT 24
Peak memory 373016 kb
Host smart-fac29d65-49d1-4090-b5f7-c81ae75174a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=838517737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.838517737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.417456793
Short name T821
Test name
Test status
Simulation time 72754921305 ps
CPU time 1550.16 seconds
Started Mar 24 01:28:24 PM PDT 24
Finished Mar 24 01:54:14 PM PDT 24
Peak memory 390992 kb
Host smart-e25e3d99-6b60-44c9-858b-820f4a968cce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=417456793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.417456793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.1932337050
Short name T528
Test name
Test status
Simulation time 96930448733 ps
CPU time 1285.31 seconds
Started Mar 24 01:28:23 PM PDT 24
Finished Mar 24 01:49:49 PM PDT 24
Peak memory 332532 kb
Host smart-8bf0e5e5-c577-4aaf-8d67-58d4e0860f27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1932337050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.1932337050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.3829993121
Short name T473
Test name
Test status
Simulation time 203370264502 ps
CPU time 959.58 seconds
Started Mar 24 01:28:25 PM PDT 24
Finished Mar 24 01:44:24 PM PDT 24
Peak memory 295460 kb
Host smart-d961abd5-7852-40b8-88f6-5600b645cb24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3829993121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.3829993121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.923194283
Short name T474
Test name
Test status
Simulation time 210746965818 ps
CPU time 4217.17 seconds
Started Mar 24 01:28:23 PM PDT 24
Finished Mar 24 02:38:40 PM PDT 24
Peak memory 645512 kb
Host smart-f0dfd7f6-bf4e-4b21-a644-0dfad8cd9832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=923194283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.923194283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1365692525
Short name T324
Test name
Test status
Simulation time 15709973 ps
CPU time 0.79 seconds
Started Mar 24 01:28:39 PM PDT 24
Finished Mar 24 01:28:41 PM PDT 24
Peak memory 205740 kb
Host smart-8b24f938-d3cd-4fb6-af43-773afc52704e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365692525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1365692525 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.2657100562
Short name T591
Test name
Test status
Simulation time 18942474763 ps
CPU time 96.73 seconds
Started Mar 24 01:28:37 PM PDT 24
Finished Mar 24 01:30:14 PM PDT 24
Peak memory 230004 kb
Host smart-29b84f35-aa00-4a13-be20-6c3fea19a4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657100562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2657100562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.519243953
Short name T240
Test name
Test status
Simulation time 4318312020 ps
CPU time 350.61 seconds
Started Mar 24 01:28:33 PM PDT 24
Finished Mar 24 01:34:24 PM PDT 24
Peak memory 229712 kb
Host smart-bac972bc-813e-4d4e-9730-67608a230845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519243953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.519243953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.2793531653
Short name T606
Test name
Test status
Simulation time 17155637336 ps
CPU time 69.15 seconds
Started Mar 24 01:28:37 PM PDT 24
Finished Mar 24 01:29:47 PM PDT 24
Peak memory 226372 kb
Host smart-b164f721-5619-4c8b-92fd-c1413f8a2b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793531653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2793531653 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.1715692071
Short name T759
Test name
Test status
Simulation time 26941237932 ps
CPU time 389.87 seconds
Started Mar 24 01:28:41 PM PDT 24
Finished Mar 24 01:35:11 PM PDT 24
Peak memory 257232 kb
Host smart-3ebb3f88-1deb-4a9e-8a2d-d77c0ad21533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715692071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1715692071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.801766951
Short name T536
Test name
Test status
Simulation time 464373763 ps
CPU time 2.84 seconds
Started Mar 24 01:28:40 PM PDT 24
Finished Mar 24 01:28:44 PM PDT 24
Peak memory 207604 kb
Host smart-16242f40-dea8-47cf-bb2e-ee19e2e7aad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801766951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.801766951 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.2244297750
Short name T106
Test name
Test status
Simulation time 170984872 ps
CPU time 1.36 seconds
Started Mar 24 01:28:40 PM PDT 24
Finished Mar 24 01:28:42 PM PDT 24
Peak memory 216172 kb
Host smart-e310cb2e-e305-489d-aa59-ee34a0dcd3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244297750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2244297750 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.257222475
Short name T916
Test name
Test status
Simulation time 1237646782201 ps
CPU time 1808.56 seconds
Started Mar 24 01:28:38 PM PDT 24
Finished Mar 24 01:58:47 PM PDT 24
Peak memory 388212 kb
Host smart-12f92296-6f2c-49fe-8194-a3a6cb0c4072
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257222475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_an
d_output.257222475 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.2650592409
Short name T660
Test name
Test status
Simulation time 171203538836 ps
CPU time 381.99 seconds
Started Mar 24 01:28:32 PM PDT 24
Finished Mar 24 01:34:54 PM PDT 24
Peak memory 247140 kb
Host smart-465f363a-a8e9-4b56-8d90-bc5e21159fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650592409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2650592409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3755155528
Short name T789
Test name
Test status
Simulation time 3693335499 ps
CPU time 14.55 seconds
Started Mar 24 01:28:30 PM PDT 24
Finished Mar 24 01:28:44 PM PDT 24
Peak memory 224440 kb
Host smart-6fcf099d-bc6c-42d0-8b21-5ff95ef78cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755155528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3755155528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.3326874938
Short name T84
Test name
Test status
Simulation time 269992310945 ps
CPU time 1020.69 seconds
Started Mar 24 01:28:39 PM PDT 24
Finished Mar 24 01:45:41 PM PDT 24
Peak memory 338656 kb
Host smart-ac5ee649-6d25-46d1-9eef-1d81e20a543b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3326874938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3326874938 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.3688982714
Short name T542
Test name
Test status
Simulation time 254925134 ps
CPU time 4.48 seconds
Started Mar 24 01:28:33 PM PDT 24
Finished Mar 24 01:28:38 PM PDT 24
Peak memory 216256 kb
Host smart-54fc0d79-9dfa-4071-bc3e-27b2ec961223
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688982714 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.3688982714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.2852671622
Short name T497
Test name
Test status
Simulation time 67809097 ps
CPU time 4.26 seconds
Started Mar 24 01:28:40 PM PDT 24
Finished Mar 24 01:28:45 PM PDT 24
Peak memory 216296 kb
Host smart-e35010a2-7981-43a1-a7ac-4f8036ab50a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852671622 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.2852671622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.4051215778
Short name T678
Test name
Test status
Simulation time 352286134825 ps
CPU time 1901.11 seconds
Started Mar 24 01:28:36 PM PDT 24
Finished Mar 24 02:00:18 PM PDT 24
Peak memory 393992 kb
Host smart-f315ed95-d6c0-4694-a49c-6ee6fb09dbde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4051215778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.4051215778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.334215429
Short name T237
Test name
Test status
Simulation time 166217976915 ps
CPU time 1862.38 seconds
Started Mar 24 01:28:38 PM PDT 24
Finished Mar 24 01:59:41 PM PDT 24
Peak memory 375848 kb
Host smart-bd888b6d-f3eb-4c66-9899-5ae7789399a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=334215429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.334215429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.1525576666
Short name T500
Test name
Test status
Simulation time 46315327495 ps
CPU time 1294.76 seconds
Started Mar 24 01:28:32 PM PDT 24
Finished Mar 24 01:50:07 PM PDT 24
Peak memory 332016 kb
Host smart-dbe89887-6d84-43f8-8766-c4efeac86af4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1525576666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.1525576666 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.3843376364
Short name T939
Test name
Test status
Simulation time 10169309511 ps
CPU time 882.4 seconds
Started Mar 24 01:28:32 PM PDT 24
Finished Mar 24 01:43:15 PM PDT 24
Peak memory 299140 kb
Host smart-17da1b37-e150-4200-8eb0-42fffa555944
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3843376364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3843376364 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.305819256
Short name T899
Test name
Test status
Simulation time 106294476197 ps
CPU time 3986.69 seconds
Started Mar 24 01:28:33 PM PDT 24
Finished Mar 24 02:35:00 PM PDT 24
Peak memory 653880 kb
Host smart-51e0d2ac-cc4f-4b92-90dd-d1544dd09419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=305819256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.305819256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.2878611840
Short name T400
Test name
Test status
Simulation time 313273300761 ps
CPU time 3996 seconds
Started Mar 24 01:28:34 PM PDT 24
Finished Mar 24 02:35:11 PM PDT 24
Peak memory 555200 kb
Host smart-df5b5dda-c527-4f83-a00c-c53e3a6c6782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2878611840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.2878611840 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.4083865148
Short name T331
Test name
Test status
Simulation time 33553294 ps
CPU time 0.78 seconds
Started Mar 24 01:28:56 PM PDT 24
Finished Mar 24 01:28:56 PM PDT 24
Peak memory 205700 kb
Host smart-70472a8e-3a79-4414-8f7f-0b0e2ca020e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083865148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.4083865148 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3171990662
Short name T839
Test name
Test status
Simulation time 8513212576 ps
CPU time 165.24 seconds
Started Mar 24 01:28:47 PM PDT 24
Finished Mar 24 01:31:33 PM PDT 24
Peak memory 236676 kb
Host smart-6f0066ad-e852-49f2-a4c2-be705e400743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171990662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3171990662 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.4273615804
Short name T213
Test name
Test status
Simulation time 116067330895 ps
CPU time 708.62 seconds
Started Mar 24 01:28:39 PM PDT 24
Finished Mar 24 01:40:29 PM PDT 24
Peak memory 232700 kb
Host smart-f9612334-3135-4f11-938d-e5ccf467ed96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273615804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.4273615804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.1500021412
Short name T275
Test name
Test status
Simulation time 6683183782 ps
CPU time 281.61 seconds
Started Mar 24 01:28:51 PM PDT 24
Finished Mar 24 01:33:33 PM PDT 24
Peak memory 246240 kb
Host smart-89a8aeb1-7d76-4501-bfab-39d137d999bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500021412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1500021412 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3411415166
Short name T477
Test name
Test status
Simulation time 3212091442 ps
CPU time 224.77 seconds
Started Mar 24 01:28:50 PM PDT 24
Finished Mar 24 01:32:35 PM PDT 24
Peak memory 251012 kb
Host smart-eb612e0f-03d7-43a8-86ef-1b055ece10d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411415166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3411415166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.1159935778
Short name T21
Test name
Test status
Simulation time 3043709520 ps
CPU time 4.83 seconds
Started Mar 24 01:28:50 PM PDT 24
Finished Mar 24 01:28:55 PM PDT 24
Peak memory 207944 kb
Host smart-2fee72fd-bd54-4be1-89cf-8431dd0b9842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159935778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1159935778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.968160008
Short name T823
Test name
Test status
Simulation time 978426660 ps
CPU time 44.88 seconds
Started Mar 24 01:28:51 PM PDT 24
Finished Mar 24 01:29:37 PM PDT 24
Peak memory 233400 kb
Host smart-2a22bbcf-7418-467a-9087-34bc2d3946c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968160008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.968160008 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.528281364
Short name T1049
Test name
Test status
Simulation time 4462813279 ps
CPU time 381.92 seconds
Started Mar 24 01:28:41 PM PDT 24
Finished Mar 24 01:35:03 PM PDT 24
Peak memory 261924 kb
Host smart-9ffef7b6-16da-446d-bf96-01001a64191b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528281364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_an
d_output.528281364 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.3919264210
Short name T42
Test name
Test status
Simulation time 1190219705 ps
CPU time 15.79 seconds
Started Mar 24 01:28:38 PM PDT 24
Finished Mar 24 01:28:54 PM PDT 24
Peak memory 217960 kb
Host smart-ffefb9db-312a-4513-839c-0ccc44b9bfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919264210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3919264210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.310805816
Short name T925
Test name
Test status
Simulation time 2050363634 ps
CPU time 28.15 seconds
Started Mar 24 01:28:40 PM PDT 24
Finished Mar 24 01:29:09 PM PDT 24
Peak memory 224404 kb
Host smart-bf20bf11-d600-45e0-9155-32c31e443685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310805816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.310805816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.1593080748
Short name T28
Test name
Test status
Simulation time 312078152003 ps
CPU time 1871.74 seconds
Started Mar 24 01:28:51 PM PDT 24
Finished Mar 24 02:00:03 PM PDT 24
Peak memory 451240 kb
Host smart-17ff259a-4294-46ac-9428-efff47f1e78c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1593080748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1593080748 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.414124749
Short name T889
Test name
Test status
Simulation time 250049766 ps
CPU time 3.87 seconds
Started Mar 24 01:28:47 PM PDT 24
Finished Mar 24 01:28:52 PM PDT 24
Peak memory 216228 kb
Host smart-d34a4e82-7c07-4e44-aeac-f7afaca1609f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414124749 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.kmac_test_vectors_kmac.414124749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2318193995
Short name T340
Test name
Test status
Simulation time 488561192 ps
CPU time 5.1 seconds
Started Mar 24 01:28:46 PM PDT 24
Finished Mar 24 01:28:53 PM PDT 24
Peak memory 216260 kb
Host smart-40db5f7c-c87c-42ca-b4bf-bda4ec082626
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318193995 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2318193995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.2914706333
Short name T919
Test name
Test status
Simulation time 138023192908 ps
CPU time 1912.65 seconds
Started Mar 24 01:28:38 PM PDT 24
Finished Mar 24 02:00:32 PM PDT 24
Peak memory 392368 kb
Host smart-5ed94b52-1162-4a29-8115-42f974b081b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2914706333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.2914706333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.3046989114
Short name T631
Test name
Test status
Simulation time 352627356200 ps
CPU time 1922.61 seconds
Started Mar 24 01:28:42 PM PDT 24
Finished Mar 24 02:00:46 PM PDT 24
Peak memory 362056 kb
Host smart-302966d7-20c3-4e0b-ab02-7b28a618bc56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3046989114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3046989114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.524315380
Short name T456
Test name
Test status
Simulation time 63239229950 ps
CPU time 1351.76 seconds
Started Mar 24 01:28:45 PM PDT 24
Finished Mar 24 01:51:18 PM PDT 24
Peak memory 334304 kb
Host smart-e6d89596-9180-40a6-9746-f22c437f248d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=524315380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.524315380 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.878392898
Short name T837
Test name
Test status
Simulation time 20033522688 ps
CPU time 835.41 seconds
Started Mar 24 01:28:46 PM PDT 24
Finished Mar 24 01:42:43 PM PDT 24
Peak memory 293700 kb
Host smart-f35d5be3-e026-4b54-a1bd-30e9a089e57f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=878392898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.878392898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.1081715573
Short name T664
Test name
Test status
Simulation time 1752227384406 ps
CPU time 5617.92 seconds
Started Mar 24 01:28:47 PM PDT 24
Finished Mar 24 03:02:27 PM PDT 24
Peak memory 670180 kb
Host smart-8e02ebf8-2531-4ce5-8a76-6a0464707d49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1081715573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.1081715573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.3410948030
Short name T575
Test name
Test status
Simulation time 161622393501 ps
CPU time 3890.21 seconds
Started Mar 24 01:28:47 PM PDT 24
Finished Mar 24 02:33:38 PM PDT 24
Peak memory 573020 kb
Host smart-06b809f9-10b3-46b8-afa3-2e4de1c10f77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3410948030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.3410948030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.3109691745
Short name T568
Test name
Test status
Simulation time 172487345 ps
CPU time 0.86 seconds
Started Mar 24 01:29:00 PM PDT 24
Finished Mar 24 01:29:01 PM PDT 24
Peak memory 205708 kb
Host smart-b62de7e1-85bf-42bd-bd1e-479e3e4b1c6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109691745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3109691745 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.1046365298
Short name T345
Test name
Test status
Simulation time 11822486391 ps
CPU time 138.72 seconds
Started Mar 24 01:28:58 PM PDT 24
Finished Mar 24 01:31:17 PM PDT 24
Peak memory 235704 kb
Host smart-26c90cab-157a-4c81-83fb-90888f91b02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046365298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1046365298 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1789280293
Short name T541
Test name
Test status
Simulation time 885264462 ps
CPU time 25.85 seconds
Started Mar 24 01:28:56 PM PDT 24
Finished Mar 24 01:29:22 PM PDT 24
Peak memory 218836 kb
Host smart-8dd7a0b8-6c2a-4eb3-8c9a-c379c40697be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789280293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1789280293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.338703340
Short name T1026
Test name
Test status
Simulation time 27388014757 ps
CPU time 125.38 seconds
Started Mar 24 01:28:56 PM PDT 24
Finished Mar 24 01:31:01 PM PDT 24
Peak memory 231112 kb
Host smart-b420c0c1-9e87-4a26-9265-f1b86e7045d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338703340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.338703340 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.3174732760
Short name T493
Test name
Test status
Simulation time 14793742162 ps
CPU time 304.17 seconds
Started Mar 24 01:29:01 PM PDT 24
Finished Mar 24 01:34:05 PM PDT 24
Peak memory 257264 kb
Host smart-7f068563-597f-4262-8b26-3e197d21af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174732760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3174732760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.2343019703
Short name T549
Test name
Test status
Simulation time 162426764 ps
CPU time 1.68 seconds
Started Mar 24 01:29:04 PM PDT 24
Finished Mar 24 01:29:06 PM PDT 24
Peak memory 207804 kb
Host smart-cb7e0ff5-3b17-46c3-879a-e098e5e8b800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343019703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2343019703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.3126723471
Short name T750
Test name
Test status
Simulation time 83247080 ps
CPU time 1.13 seconds
Started Mar 24 01:29:04 PM PDT 24
Finished Mar 24 01:29:05 PM PDT 24
Peak memory 216176 kb
Host smart-c46f303c-ee8b-4675-b4fc-9861baa02ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126723471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3126723471 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.1214507740
Short name T276
Test name
Test status
Simulation time 10440972917 ps
CPU time 934.28 seconds
Started Mar 24 01:28:58 PM PDT 24
Finished Mar 24 01:44:32 PM PDT 24
Peak memory 313516 kb
Host smart-4cbac3f3-9f6c-4b8e-aca8-e78e8b73c1fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214507740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.1214507740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.2572005310
Short name T87
Test name
Test status
Simulation time 7642278274 ps
CPU time 307.23 seconds
Started Mar 24 01:28:54 PM PDT 24
Finished Mar 24 01:34:02 PM PDT 24
Peak memory 248628 kb
Host smart-b2855f7a-d679-4814-935b-e8c79c3762d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572005310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2572005310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.122270789
Short name T558
Test name
Test status
Simulation time 315128901 ps
CPU time 15.68 seconds
Started Mar 24 01:28:59 PM PDT 24
Finished Mar 24 01:29:15 PM PDT 24
Peak memory 218824 kb
Host smart-e1c5db83-3722-43b8-b190-156df567cb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122270789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.122270789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.771466794
Short name T805
Test name
Test status
Simulation time 195822671053 ps
CPU time 2127.28 seconds
Started Mar 24 01:29:01 PM PDT 24
Finished Mar 24 02:04:28 PM PDT 24
Peak memory 433644 kb
Host smart-ba605f52-a07e-4a43-8855-c088f9f1ae8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=771466794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.771466794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.634500108
Short name T774
Test name
Test status
Simulation time 122882279 ps
CPU time 4.39 seconds
Started Mar 24 01:28:57 PM PDT 24
Finished Mar 24 01:29:01 PM PDT 24
Peak memory 216248 kb
Host smart-89912476-e9f2-4f0f-86e9-cd6cee294099
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634500108 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.kmac_test_vectors_kmac.634500108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.683503331
Short name T323
Test name
Test status
Simulation time 692216968 ps
CPU time 4.71 seconds
Started Mar 24 01:28:55 PM PDT 24
Finished Mar 24 01:29:00 PM PDT 24
Peak memory 216504 kb
Host smart-eb6424a3-679e-46c3-88c1-b70e19208762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683503331 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.kmac_test_vectors_kmac_xof.683503331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.1620739102
Short name T848
Test name
Test status
Simulation time 67495999922 ps
CPU time 1573.29 seconds
Started Mar 24 01:28:55 PM PDT 24
Finished Mar 24 01:55:09 PM PDT 24
Peak memory 387568 kb
Host smart-f5401770-4d0f-48e1-b87a-1a959704ef6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1620739102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.1620739102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.2172626278
Short name T537
Test name
Test status
Simulation time 18818921440 ps
CPU time 1470.4 seconds
Started Mar 24 01:28:58 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 377940 kb
Host smart-b829b857-1dec-437b-aa70-861a9e0d16ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2172626278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.2172626278 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.2378322707
Short name T718
Test name
Test status
Simulation time 287312078804 ps
CPU time 1427.96 seconds
Started Mar 24 01:28:57 PM PDT 24
Finished Mar 24 01:52:45 PM PDT 24
Peak memory 330684 kb
Host smart-2e629bfe-638e-4ae2-a7c3-7268744d2d63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2378322707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2378322707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.3571710801
Short name T985
Test name
Test status
Simulation time 119139336383 ps
CPU time 907.43 seconds
Started Mar 24 01:28:55 PM PDT 24
Finished Mar 24 01:44:03 PM PDT 24
Peak memory 292672 kb
Host smart-006efed6-0b93-4242-a8bf-1afd329a0054
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3571710801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.3571710801 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.3100601008
Short name T1043
Test name
Test status
Simulation time 503001066175 ps
CPU time 4645.2 seconds
Started Mar 24 01:28:54 PM PDT 24
Finished Mar 24 02:46:20 PM PDT 24
Peak memory 646672 kb
Host smart-f9e2a11b-fb36-4c0e-92de-34b33bb62f5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3100601008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.3100601008 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.291127464
Short name T524
Test name
Test status
Simulation time 147788623956 ps
CPU time 4062.86 seconds
Started Mar 24 01:28:54 PM PDT 24
Finished Mar 24 02:36:38 PM PDT 24
Peak memory 551152 kb
Host smart-be25a9b7-14b4-4f4f-b999-9a071847e7bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=291127464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.291127464 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.3566091375
Short name T735
Test name
Test status
Simulation time 19873486 ps
CPU time 0.74 seconds
Started Mar 24 01:29:19 PM PDT 24
Finished Mar 24 01:29:20 PM PDT 24
Peak memory 205692 kb
Host smart-f90c62d3-fdf8-4a11-9d14-12f18853b7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566091375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3566091375 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.359925599
Short name T463
Test name
Test status
Simulation time 8083970330 ps
CPU time 184.56 seconds
Started Mar 24 01:29:14 PM PDT 24
Finished Mar 24 01:32:18 PM PDT 24
Peak memory 238384 kb
Host smart-bcce398b-47eb-44cc-9ca2-40a0d265c63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359925599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.359925599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.3205426006
Short name T97
Test name
Test status
Simulation time 25385689481 ps
CPU time 582.27 seconds
Started Mar 24 01:29:13 PM PDT 24
Finished Mar 24 01:38:55 PM PDT 24
Peak memory 230788 kb
Host smart-63aeff6c-b4ba-417f-921d-45b59f3cc799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205426006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3205426006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.4139905958
Short name T384
Test name
Test status
Simulation time 4179325070 ps
CPU time 27.08 seconds
Started Mar 24 01:29:16 PM PDT 24
Finished Mar 24 01:29:43 PM PDT 24
Peak memory 224784 kb
Host smart-82857b1a-ea8a-4759-ae02-2c9c257066f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139905958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.4139905958 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.3355901531
Short name T1014
Test name
Test status
Simulation time 18585789257 ps
CPU time 353.68 seconds
Started Mar 24 01:29:15 PM PDT 24
Finished Mar 24 01:35:09 PM PDT 24
Peak memory 266892 kb
Host smart-6557e671-d683-4e99-86f1-86946cfb9ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355901531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3355901531 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.70846325
Short name T1068
Test name
Test status
Simulation time 1095397945 ps
CPU time 3.34 seconds
Started Mar 24 01:29:19 PM PDT 24
Finished Mar 24 01:29:22 PM PDT 24
Peak memory 216016 kb
Host smart-3128c12c-e8c1-4b26-b211-bdbe50352556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70846325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.70846325 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1650307438
Short name T328
Test name
Test status
Simulation time 15595816369 ps
CPU time 171.53 seconds
Started Mar 24 01:29:12 PM PDT 24
Finished Mar 24 01:32:04 PM PDT 24
Peak memory 239356 kb
Host smart-ef8f051e-46b4-48c7-a12d-2313c8828edc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650307438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1650307438 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.3667729545
Short name T829
Test name
Test status
Simulation time 26570654946 ps
CPU time 319.68 seconds
Started Mar 24 01:29:06 PM PDT 24
Finished Mar 24 01:34:26 PM PDT 24
Peak memory 248380 kb
Host smart-c833f35c-25f6-4ae2-b789-6235895e0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667729545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3667729545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.2772955371
Short name T1015
Test name
Test status
Simulation time 16325533407 ps
CPU time 41.69 seconds
Started Mar 24 01:28:59 PM PDT 24
Finished Mar 24 01:29:41 PM PDT 24
Peak memory 218732 kb
Host smart-170f9254-e9c8-4546-b270-7da508ca06f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772955371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2772955371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.1112877282
Short name T708
Test name
Test status
Simulation time 43747261381 ps
CPU time 835.36 seconds
Started Mar 24 01:29:18 PM PDT 24
Finished Mar 24 01:43:14 PM PDT 24
Peak memory 314932 kb
Host smart-1367615f-f6be-48ac-addd-145ae99ac6b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1112877282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.1112877282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.3777540037
Short name T313
Test name
Test status
Simulation time 237850831 ps
CPU time 4.81 seconds
Started Mar 24 01:29:12 PM PDT 24
Finished Mar 24 01:29:17 PM PDT 24
Peak memory 216296 kb
Host smart-f02cc30a-7b2d-4523-b6cd-db47b280af3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777540037 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.3777540037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.4012811710
Short name T326
Test name
Test status
Simulation time 181886925 ps
CPU time 4.85 seconds
Started Mar 24 01:29:16 PM PDT 24
Finished Mar 24 01:29:21 PM PDT 24
Peak memory 216324 kb
Host smart-137fbfdd-55a5-4c18-b694-922155b82c6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012811710 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.4012811710 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.992762959
Short name T446
Test name
Test status
Simulation time 19017053111 ps
CPU time 1477.15 seconds
Started Mar 24 01:29:12 PM PDT 24
Finished Mar 24 01:53:50 PM PDT 24
Peak memory 396628 kb
Host smart-bbe97ef0-52f3-499a-93c8-b70ff9f50e23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=992762959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.992762959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.1771466393
Short name T617
Test name
Test status
Simulation time 17838784873 ps
CPU time 1493.39 seconds
Started Mar 24 01:29:13 PM PDT 24
Finished Mar 24 01:54:07 PM PDT 24
Peak memory 369464 kb
Host smart-461f652a-afbf-423c-9f49-4e80912ae83d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1771466393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.1771466393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.1590582780
Short name T665
Test name
Test status
Simulation time 309889878371 ps
CPU time 1452.3 seconds
Started Mar 24 01:29:12 PM PDT 24
Finished Mar 24 01:53:25 PM PDT 24
Peak memory 326768 kb
Host smart-ce9e7d6b-6cca-49c7-94ab-888dc1c63390
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1590582780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.1590582780 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.3872189056
Short name T321
Test name
Test status
Simulation time 51527195095 ps
CPU time 951.36 seconds
Started Mar 24 01:29:12 PM PDT 24
Finished Mar 24 01:45:04 PM PDT 24
Peak memory 295404 kb
Host smart-63211af7-edf4-425a-9aa8-e17d5e5e1d41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3872189056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.3872189056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.2376012615
Short name T123
Test name
Test status
Simulation time 172420782340 ps
CPU time 4752.78 seconds
Started Mar 24 01:29:13 PM PDT 24
Finished Mar 24 02:48:26 PM PDT 24
Peak memory 652240 kb
Host smart-237b9d35-fd6b-444a-923b-8968cb604a4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2376012615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2376012615 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.65399959
Short name T510
Test name
Test status
Simulation time 287004689132 ps
CPU time 4045.29 seconds
Started Mar 24 01:29:15 PM PDT 24
Finished Mar 24 02:36:41 PM PDT 24
Peak memory 551624 kb
Host smart-72e93fae-5a55-4318-9a38-ef9b7abdfb39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=65399959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.65399959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.4154853805
Short name T268
Test name
Test status
Simulation time 41487054 ps
CPU time 0.73 seconds
Started Mar 24 01:25:34 PM PDT 24
Finished Mar 24 01:25:35 PM PDT 24
Peak memory 205708 kb
Host smart-dd0a70ad-ae2b-491a-894a-52d75392ca49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154853805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.4154853805 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.3475757817
Short name T565
Test name
Test status
Simulation time 1812474987 ps
CPU time 75.19 seconds
Started Mar 24 01:25:32 PM PDT 24
Finished Mar 24 01:26:47 PM PDT 24
Peak memory 226720 kb
Host smart-702c2f5a-5994-4464-8f47-fe38204398b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475757817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3475757817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.57000940
Short name T719
Test name
Test status
Simulation time 16345136562 ps
CPU time 201.62 seconds
Started Mar 24 01:25:31 PM PDT 24
Finished Mar 24 01:28:52 PM PDT 24
Peak memory 238608 kb
Host smart-966affe0-c0a6-4df6-a027-703ddbe9bcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57000940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.57000940 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.2766389260
Short name T387
Test name
Test status
Simulation time 39332398252 ps
CPU time 420.31 seconds
Started Mar 24 01:25:26 PM PDT 24
Finished Mar 24 01:32:27 PM PDT 24
Peak memory 229840 kb
Host smart-0b6c6cb3-04ae-4633-8cc3-b2f60793857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766389260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2766389260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.2040911859
Short name T704
Test name
Test status
Simulation time 1407199997 ps
CPU time 31.5 seconds
Started Mar 24 01:25:31 PM PDT 24
Finished Mar 24 01:26:03 PM PDT 24
Peak memory 232044 kb
Host smart-5a86d6f0-ab4f-4d21-8a22-68db3d144e71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2040911859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2040911859 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.643489684
Short name T1032
Test name
Test status
Simulation time 928569108 ps
CPU time 24.56 seconds
Started Mar 24 01:25:32 PM PDT 24
Finished Mar 24 01:25:58 PM PDT 24
Peak memory 219856 kb
Host smart-0e9d4077-1bc3-4d71-888b-3b2493d11d4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=643489684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.643489684 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.4281799045
Short name T499
Test name
Test status
Simulation time 2230911685 ps
CPU time 22.18 seconds
Started Mar 24 01:25:33 PM PDT 24
Finished Mar 24 01:25:55 PM PDT 24
Peak memory 217176 kb
Host smart-056826bc-22da-4259-ae26-c572c48c866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281799045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.4281799045 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.2903952818
Short name T880
Test name
Test status
Simulation time 80268627229 ps
CPU time 212.62 seconds
Started Mar 24 01:25:30 PM PDT 24
Finished Mar 24 01:29:03 PM PDT 24
Peak memory 234728 kb
Host smart-d6f29de1-8969-49bf-b653-8f1f55f2173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903952818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2903952818 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.1467495774
Short name T363
Test name
Test status
Simulation time 5775749750 ps
CPU time 25.13 seconds
Started Mar 24 01:25:35 PM PDT 24
Finished Mar 24 01:26:00 PM PDT 24
Peak memory 237832 kb
Host smart-b3054599-ff72-4fc8-a33d-380691137777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467495774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1467495774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.180337966
Short name T509
Test name
Test status
Simulation time 1099007316 ps
CPU time 1.89 seconds
Started Mar 24 01:25:34 PM PDT 24
Finished Mar 24 01:25:37 PM PDT 24
Peak memory 207332 kb
Host smart-d924aedc-b479-4e21-b9d0-f18ca32a07d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180337966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.180337966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.3984401191
Short name T322
Test name
Test status
Simulation time 813659020 ps
CPU time 10.9 seconds
Started Mar 24 01:25:32 PM PDT 24
Finished Mar 24 01:25:43 PM PDT 24
Peak memory 224276 kb
Host smart-eb4cf967-fb20-4705-be70-3996bcc4235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984401191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3984401191 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.2351332648
Short name T292
Test name
Test status
Simulation time 280447037737 ps
CPU time 1514.25 seconds
Started Mar 24 01:25:30 PM PDT 24
Finished Mar 24 01:50:45 PM PDT 24
Peak memory 379012 kb
Host smart-5f364ca3-c8c9-4dfa-b002-64b57d3d2425
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351332648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.2351332648 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.861704024
Short name T86
Test name
Test status
Simulation time 12243644390 ps
CPU time 167.85 seconds
Started Mar 24 01:25:32 PM PDT 24
Finished Mar 24 01:28:20 PM PDT 24
Peak memory 239296 kb
Host smart-944588c2-953d-4c49-a7e4-8593179cc84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861704024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.861704024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.795516220
Short name T12
Test name
Test status
Simulation time 13009076150 ps
CPU time 59.33 seconds
Started Mar 24 01:25:35 PM PDT 24
Finished Mar 24 01:26:35 PM PDT 24
Peak memory 256584 kb
Host smart-36bf5a5e-cc06-4238-81f6-b26ae53002b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795516220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.795516220 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.2178763402
Short name T1034
Test name
Test status
Simulation time 1758981068 ps
CPU time 46.06 seconds
Started Mar 24 01:25:30 PM PDT 24
Finished Mar 24 01:26:16 PM PDT 24
Peak memory 224352 kb
Host smart-1e0bc234-535e-44a0-80db-1105e37c53da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178763402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2178763402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.1282872930
Short name T672
Test name
Test status
Simulation time 4775715008 ps
CPU time 33.5 seconds
Started Mar 24 01:25:26 PM PDT 24
Finished Mar 24 01:26:00 PM PDT 24
Peak memory 221256 kb
Host smart-b932546c-d02b-41eb-a293-b42c4006a2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282872930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1282872930 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.3383329879
Short name T586
Test name
Test status
Simulation time 242206575 ps
CPU time 3.72 seconds
Started Mar 24 01:25:32 PM PDT 24
Finished Mar 24 01:25:36 PM PDT 24
Peak memory 216284 kb
Host smart-bbcfb020-2f0d-4c25-a911-51a278fcc3b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383329879 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.3383329879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.934493905
Short name T286
Test name
Test status
Simulation time 68444841 ps
CPU time 4.27 seconds
Started Mar 24 01:25:33 PM PDT 24
Finished Mar 24 01:25:38 PM PDT 24
Peak memory 216244 kb
Host smart-03d13b27-4fe6-4a35-835f-8dca1e2bccf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934493905 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.kmac_test_vectors_kmac_xof.934493905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.3566438989
Short name T281
Test name
Test status
Simulation time 79553146479 ps
CPU time 1732.61 seconds
Started Mar 24 01:25:28 PM PDT 24
Finished Mar 24 01:54:21 PM PDT 24
Peak memory 389436 kb
Host smart-6f4a6da3-6b40-49c5-a7f8-5e03964df08a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3566438989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.3566438989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.3475775850
Short name T233
Test name
Test status
Simulation time 20582391831 ps
CPU time 1539.24 seconds
Started Mar 24 01:25:26 PM PDT 24
Finished Mar 24 01:51:05 PM PDT 24
Peak memory 373880 kb
Host smart-8ecbfc4b-d59f-45fe-87f2-f24b41e3463b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3475775850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3475775850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.3994069437
Short name T215
Test name
Test status
Simulation time 56603540920 ps
CPU time 1131.06 seconds
Started Mar 24 01:25:32 PM PDT 24
Finished Mar 24 01:44:23 PM PDT 24
Peak memory 334492 kb
Host smart-e40f3e8d-46be-44e0-a85c-96fb44b64a2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3994069437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3994069437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.1849620307
Short name T941
Test name
Test status
Simulation time 66928723593 ps
CPU time 935.07 seconds
Started Mar 24 01:25:33 PM PDT 24
Finished Mar 24 01:41:08 PM PDT 24
Peak memory 295800 kb
Host smart-593add4c-1f18-44a8-b4a4-f2d614aba31e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1849620307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1849620307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.2153846596
Short name T743
Test name
Test status
Simulation time 363945870236 ps
CPU time 5180.32 seconds
Started Mar 24 01:25:35 PM PDT 24
Finished Mar 24 02:51:55 PM PDT 24
Peak memory 667920 kb
Host smart-e8e888de-b680-4c8f-acf4-91f3a70008ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2153846596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.2153846596 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.2191983629
Short name T285
Test name
Test status
Simulation time 216949673955 ps
CPU time 4435.3 seconds
Started Mar 24 01:25:33 PM PDT 24
Finished Mar 24 02:39:29 PM PDT 24
Peak memory 554752 kb
Host smart-aec79743-97f7-42d8-bb51-5327643696eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2191983629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2191983629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.1085676526
Short name T319
Test name
Test status
Simulation time 25668528 ps
CPU time 0.78 seconds
Started Mar 24 01:29:30 PM PDT 24
Finished Mar 24 01:29:31 PM PDT 24
Peak memory 205708 kb
Host smart-50cea552-1bd1-4667-91a6-71abbfd05ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085676526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.1085676526 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.1669954993
Short name T128
Test name
Test status
Simulation time 4136414706 ps
CPU time 102.53 seconds
Started Mar 24 01:29:28 PM PDT 24
Finished Mar 24 01:31:11 PM PDT 24
Peak memory 230448 kb
Host smart-3041f526-f8d3-47a1-ab82-985ac956a4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669954993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1669954993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.3549298399
Short name T978
Test name
Test status
Simulation time 32845152835 ps
CPU time 650.3 seconds
Started Mar 24 01:29:26 PM PDT 24
Finished Mar 24 01:40:16 PM PDT 24
Peak memory 232012 kb
Host smart-d946e329-f803-4aac-bafa-d13a7d9137be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549298399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3549298399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.3081204647
Short name T734
Test name
Test status
Simulation time 2086802704 ps
CPU time 75.69 seconds
Started Mar 24 01:29:28 PM PDT 24
Finished Mar 24 01:30:44 PM PDT 24
Peak memory 226776 kb
Host smart-a1fa96ca-bbc9-447a-836c-4e950af9718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081204647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3081204647 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.1575295725
Short name T100
Test name
Test status
Simulation time 464251006 ps
CPU time 30.28 seconds
Started Mar 24 01:29:29 PM PDT 24
Finished Mar 24 01:29:59 PM PDT 24
Peak memory 232612 kb
Host smart-00be4b60-634b-4488-b10c-f89fb1237dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575295725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1575295725 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.836140483
Short name T762
Test name
Test status
Simulation time 302912898 ps
CPU time 1.08 seconds
Started Mar 24 01:29:29 PM PDT 24
Finished Mar 24 01:29:30 PM PDT 24
Peak memory 205896 kb
Host smart-5cc74110-de83-4257-9469-776c0fb79d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836140483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.836140483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.2132771326
Short name T304
Test name
Test status
Simulation time 40866453 ps
CPU time 1.05 seconds
Started Mar 24 01:29:29 PM PDT 24
Finished Mar 24 01:29:30 PM PDT 24
Peak memory 207924 kb
Host smart-374e15ab-8766-4929-a7be-057cc043d602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132771326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2132771326 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.2457002962
Short name T346
Test name
Test status
Simulation time 6396592669 ps
CPU time 568 seconds
Started Mar 24 01:29:19 PM PDT 24
Finished Mar 24 01:38:47 PM PDT 24
Peak memory 281452 kb
Host smart-b0abff83-d537-4cbe-ba82-5de8c5ef9f8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457002962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.2457002962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.2092106537
Short name T248
Test name
Test status
Simulation time 39110624416 ps
CPU time 419.5 seconds
Started Mar 24 01:29:27 PM PDT 24
Finished Mar 24 01:36:26 PM PDT 24
Peak memory 248672 kb
Host smart-12db7cd1-cf1e-4440-b55c-2ffc448ed403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092106537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.2092106537 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.3231637334
Short name T436
Test name
Test status
Simulation time 3373695420 ps
CPU time 55.83 seconds
Started Mar 24 01:29:20 PM PDT 24
Finished Mar 24 01:30:16 PM PDT 24
Peak memory 216704 kb
Host smart-67c6c553-8bfb-474c-891f-62f6f3843e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231637334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.3231637334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.2308509402
Short name T928
Test name
Test status
Simulation time 95849790951 ps
CPU time 2565.31 seconds
Started Mar 24 01:29:29 PM PDT 24
Finished Mar 24 02:12:15 PM PDT 24
Peak memory 513016 kb
Host smart-bf0e7de4-ba28-49bf-9ed8-a854d412485c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2308509402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2308509402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.1122095530
Short name T924
Test name
Test status
Simulation time 265131581 ps
CPU time 5.11 seconds
Started Mar 24 01:29:29 PM PDT 24
Finished Mar 24 01:29:34 PM PDT 24
Peak memory 216216 kb
Host smart-bbe4ded9-a2df-4c4b-9379-f0336e9d1602
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122095530 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.1122095530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.1844718788
Short name T535
Test name
Test status
Simulation time 361140423 ps
CPU time 4.16 seconds
Started Mar 24 01:29:30 PM PDT 24
Finished Mar 24 01:29:34 PM PDT 24
Peak memory 216272 kb
Host smart-4dfeaedd-f4e0-4542-969f-30a8c58fccf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844718788 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.1844718788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.483111958
Short name T933
Test name
Test status
Simulation time 369580010003 ps
CPU time 2131.77 seconds
Started Mar 24 01:29:25 PM PDT 24
Finished Mar 24 02:04:57 PM PDT 24
Peak memory 387772 kb
Host smart-d592ae0b-a881-4c5a-b6d0-382cd9390011
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=483111958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.483111958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.3549256644
Short name T588
Test name
Test status
Simulation time 118922358569 ps
CPU time 1759.1 seconds
Started Mar 24 01:29:26 PM PDT 24
Finished Mar 24 01:58:45 PM PDT 24
Peak memory 378532 kb
Host smart-5e858ecf-0111-4ba9-90b9-a477e48307f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3549256644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.3549256644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.3997420984
Short name T986
Test name
Test status
Simulation time 13833310603 ps
CPU time 1138.74 seconds
Started Mar 24 01:29:24 PM PDT 24
Finished Mar 24 01:48:23 PM PDT 24
Peak memory 333896 kb
Host smart-f3d1d886-085b-4ffe-903e-725db3dfe1c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3997420984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.3997420984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.3268649794
Short name T570
Test name
Test status
Simulation time 96250823710 ps
CPU time 1008.38 seconds
Started Mar 24 01:29:24 PM PDT 24
Finished Mar 24 01:46:12 PM PDT 24
Peak memory 292792 kb
Host smart-616745c9-1922-43a1-9807-a5544d87728d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3268649794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.3268649794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.1521914218
Short name T801
Test name
Test status
Simulation time 1027595573391 ps
CPU time 5540.53 seconds
Started Mar 24 01:29:25 PM PDT 24
Finished Mar 24 03:01:46 PM PDT 24
Peak memory 651160 kb
Host smart-c0e54ac7-3f4b-4b6f-9dd4-593e5eba2ea1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1521914218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.1521914218 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.592793125
Short name T129
Test name
Test status
Simulation time 1876741987717 ps
CPU time 3950.05 seconds
Started Mar 24 01:29:24 PM PDT 24
Finished Mar 24 02:35:15 PM PDT 24
Peak memory 559496 kb
Host smart-e1dd4603-cd34-471f-a339-6252889786f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=592793125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.592793125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.2724163298
Short name T876
Test name
Test status
Simulation time 14427766 ps
CPU time 0.75 seconds
Started Mar 24 01:29:46 PM PDT 24
Finished Mar 24 01:29:48 PM PDT 24
Peak memory 205712 kb
Host smart-025e2831-6e4e-4ec8-81d9-35ee61c03018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724163298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2724163298 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.2376470397
Short name T849
Test name
Test status
Simulation time 13503280140 ps
CPU time 225.05 seconds
Started Mar 24 01:29:33 PM PDT 24
Finished Mar 24 01:33:19 PM PDT 24
Peak memory 245356 kb
Host smart-eb13921e-e68e-42db-bb79-70ebadfb9911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376470397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.2376470397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.2463234846
Short name T401
Test name
Test status
Simulation time 8380792452 ps
CPU time 700.82 seconds
Started Mar 24 01:29:35 PM PDT 24
Finished Mar 24 01:41:16 PM PDT 24
Peak memory 234140 kb
Host smart-89f5aaa2-edcc-4478-b163-64f4b874c7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463234846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2463234846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.1182205732
Short name T775
Test name
Test status
Simulation time 41356944392 ps
CPU time 267.91 seconds
Started Mar 24 01:29:38 PM PDT 24
Finished Mar 24 01:34:06 PM PDT 24
Peak memory 241628 kb
Host smart-c5a06b71-4fe2-4721-8e94-31afd19199cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182205732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1182205732 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.4103598159
Short name T700
Test name
Test status
Simulation time 164374447747 ps
CPU time 407.56 seconds
Started Mar 24 01:29:40 PM PDT 24
Finished Mar 24 01:36:27 PM PDT 24
Peak memory 256296 kb
Host smart-51a9c35d-4cbc-407f-a09e-5cb267a69283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103598159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.4103598159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1530911222
Short name T771
Test name
Test status
Simulation time 668048756 ps
CPU time 3.66 seconds
Started Mar 24 01:29:39 PM PDT 24
Finished Mar 24 01:29:43 PM PDT 24
Peak memory 207640 kb
Host smart-e1aa1483-b6dc-4566-a9d1-25550d0e98b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530911222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1530911222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.3050285994
Short name T7
Test name
Test status
Simulation time 122891045 ps
CPU time 1.3 seconds
Started Mar 24 01:29:41 PM PDT 24
Finished Mar 24 01:29:42 PM PDT 24
Peak memory 217688 kb
Host smart-072c68d3-d6c0-4cc9-9971-85f8f4ce8fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050285994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.3050285994 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.1745947526
Short name T320
Test name
Test status
Simulation time 29320380397 ps
CPU time 1333.77 seconds
Started Mar 24 01:29:31 PM PDT 24
Finished Mar 24 01:51:45 PM PDT 24
Peak memory 356332 kb
Host smart-c9610624-a33d-437e-876d-905bfc2e959a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745947526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.1745947526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.2750651612
Short name T411
Test name
Test status
Simulation time 7611140191 ps
CPU time 79.09 seconds
Started Mar 24 01:29:30 PM PDT 24
Finished Mar 24 01:30:49 PM PDT 24
Peak memory 224664 kb
Host smart-7aa752f4-3964-4669-89d3-b247f349039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750651612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2750651612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.899422579
Short name T296
Test name
Test status
Simulation time 140024938 ps
CPU time 2.93 seconds
Started Mar 24 01:29:35 PM PDT 24
Finished Mar 24 01:29:38 PM PDT 24
Peak memory 216428 kb
Host smart-89043062-034b-4998-a268-848eb34bf598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899422579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.899422579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.3878819151
Short name T452
Test name
Test status
Simulation time 70022506675 ps
CPU time 725.41 seconds
Started Mar 24 01:29:38 PM PDT 24
Finished Mar 24 01:41:44 PM PDT 24
Peak memory 299124 kb
Host smart-4eee57af-1e46-48dd-b188-7b6b79267cc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3878819151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3878819151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_stress_all_with_rand_reset.577447404
Short name T144
Test name
Test status
Simulation time 57003778028 ps
CPU time 1418.9 seconds
Started Mar 24 01:29:43 PM PDT 24
Finished Mar 24 01:53:22 PM PDT 24
Peak memory 336868 kb
Host smart-95cfa3ce-1dce-4961-84c8-8e295d53d899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577447404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all_with_rand_reset.577447404 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.3545587695
Short name T972
Test name
Test status
Simulation time 1037122695 ps
CPU time 5.01 seconds
Started Mar 24 01:29:34 PM PDT 24
Finished Mar 24 01:29:39 PM PDT 24
Peak memory 216248 kb
Host smart-a1cef01a-cf60-4d13-9184-de43beb1ffa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545587695 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.3545587695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.650539211
Short name T338
Test name
Test status
Simulation time 335255172 ps
CPU time 4.4 seconds
Started Mar 24 01:29:34 PM PDT 24
Finished Mar 24 01:29:38 PM PDT 24
Peak memory 216228 kb
Host smart-9504bd98-8761-442b-a0e4-224ba0ea4dfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650539211 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.kmac_test_vectors_kmac_xof.650539211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.1118535671
Short name T764
Test name
Test status
Simulation time 19411090296 ps
CPU time 1607.7 seconds
Started Mar 24 01:29:33 PM PDT 24
Finished Mar 24 01:56:21 PM PDT 24
Peak memory 393028 kb
Host smart-3e35bf4b-7f4c-4286-9086-8e040bc81019
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1118535671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.1118535671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.2610372985
Short name T692
Test name
Test status
Simulation time 17889177179 ps
CPU time 1399.28 seconds
Started Mar 24 01:29:34 PM PDT 24
Finished Mar 24 01:52:54 PM PDT 24
Peak memory 373556 kb
Host smart-57993442-6b19-45be-b4a0-67cb01173ce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2610372985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.2610372985 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.2789105586
Short name T266
Test name
Test status
Simulation time 139125150335 ps
CPU time 1394.16 seconds
Started Mar 24 01:29:33 PM PDT 24
Finished Mar 24 01:52:48 PM PDT 24
Peak memory 333088 kb
Host smart-74187370-5c95-4ee3-966c-fb36d9c038bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2789105586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2789105586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1297692352
Short name T315
Test name
Test status
Simulation time 65739075912 ps
CPU time 857.15 seconds
Started Mar 24 01:29:35 PM PDT 24
Finished Mar 24 01:43:53 PM PDT 24
Peak memory 296132 kb
Host smart-26875e31-c9c6-492c-a7bc-19f73ba4e5ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1297692352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1297692352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.1521205087
Short name T807
Test name
Test status
Simulation time 173190258551 ps
CPU time 4593.92 seconds
Started Mar 24 01:29:34 PM PDT 24
Finished Mar 24 02:46:09 PM PDT 24
Peak memory 647560 kb
Host smart-df1f0e0d-3ca1-4808-835d-0e547577ef2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1521205087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.1521205087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.2471518543
Short name T1024
Test name
Test status
Simulation time 717626501610 ps
CPU time 3465.68 seconds
Started Mar 24 01:29:35 PM PDT 24
Finished Mar 24 02:27:21 PM PDT 24
Peak memory 557048 kb
Host smart-c13565b0-7371-479e-a8c3-31da69875ba8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2471518543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.2471518543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.1708092008
Short name T53
Test name
Test status
Simulation time 50845461 ps
CPU time 0.79 seconds
Started Mar 24 01:29:56 PM PDT 24
Finished Mar 24 01:29:57 PM PDT 24
Peak memory 205624 kb
Host smart-296d0a49-4419-4d13-86a2-dee9f022a63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708092008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1708092008 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.2950712877
Short name T831
Test name
Test status
Simulation time 5543011689 ps
CPU time 107.37 seconds
Started Mar 24 01:29:53 PM PDT 24
Finished Mar 24 01:31:40 PM PDT 24
Peak memory 229404 kb
Host smart-d63ee078-7327-4c00-9720-7f793c911a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950712877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2950712877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.3158312439
Short name T200
Test name
Test status
Simulation time 6849652150 ps
CPU time 580.94 seconds
Started Mar 24 01:29:43 PM PDT 24
Finished Mar 24 01:39:24 PM PDT 24
Peak memory 232552 kb
Host smart-a7534035-dd11-4c0b-a983-b190b28a4c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158312439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3158312439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.2253841320
Short name T49
Test name
Test status
Simulation time 10611394570 ps
CPU time 227.64 seconds
Started Mar 24 01:29:53 PM PDT 24
Finished Mar 24 01:33:41 PM PDT 24
Peak memory 242924 kb
Host smart-3b7e46d5-0dd5-4d15-95f7-e405a393be14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253841320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2253841320 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.1725378348
Short name T402
Test name
Test status
Simulation time 898489805 ps
CPU time 12.77 seconds
Started Mar 24 01:29:54 PM PDT 24
Finished Mar 24 01:30:07 PM PDT 24
Peak memory 224400 kb
Host smart-281497fa-b67c-4d03-ad2b-77701ff4260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725378348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1725378348 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.3097074039
Short name T1065
Test name
Test status
Simulation time 1259827552 ps
CPU time 2.5 seconds
Started Mar 24 01:29:52 PM PDT 24
Finished Mar 24 01:29:54 PM PDT 24
Peak memory 207820 kb
Host smart-48706e9d-e17a-4b01-8109-bc580f968acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097074039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3097074039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.372768770
Short name T347
Test name
Test status
Simulation time 32703251 ps
CPU time 1.32 seconds
Started Mar 24 01:29:52 PM PDT 24
Finished Mar 24 01:29:53 PM PDT 24
Peak memory 220788 kb
Host smart-3bdcb8c1-9b51-414a-bb8b-e3f7653097f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372768770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.372768770 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.1629673318
Short name T454
Test name
Test status
Simulation time 63769567903 ps
CPU time 1829.59 seconds
Started Mar 24 01:29:42 PM PDT 24
Finished Mar 24 02:00:12 PM PDT 24
Peak memory 397160 kb
Host smart-759b7af7-ca2e-48e4-9275-1207c168814b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629673318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.1629673318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_smoke.4132640022
Short name T418
Test name
Test status
Simulation time 2993816543 ps
CPU time 51.96 seconds
Started Mar 24 01:29:46 PM PDT 24
Finished Mar 24 01:30:38 PM PDT 24
Peak memory 222556 kb
Host smart-05605d41-6bc0-4021-b3a6-638dac629847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132640022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.4132640022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.118914375
Short name T682
Test name
Test status
Simulation time 2454982180 ps
CPU time 190.7 seconds
Started Mar 24 01:29:52 PM PDT 24
Finished Mar 24 01:33:03 PM PDT 24
Peak memory 240856 kb
Host smart-5b7d76f3-c494-4a90-a9ec-413b32d0e23f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=118914375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.118914375 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.3269366329
Short name T130
Test name
Test status
Simulation time 241444425 ps
CPU time 3.81 seconds
Started Mar 24 01:29:49 PM PDT 24
Finished Mar 24 01:29:53 PM PDT 24
Peak memory 216296 kb
Host smart-936ce9b3-87a5-4cb4-9c2a-71bf54b876db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269366329 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.3269366329 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.3633294626
Short name T152
Test name
Test status
Simulation time 426980102 ps
CPU time 4.28 seconds
Started Mar 24 01:29:52 PM PDT 24
Finished Mar 24 01:29:57 PM PDT 24
Peak memory 209564 kb
Host smart-953250dd-b7d9-4e5f-a03c-795181789d4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633294626 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.3633294626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.3123641622
Short name T410
Test name
Test status
Simulation time 18535228721 ps
CPU time 1444.04 seconds
Started Mar 24 01:29:49 PM PDT 24
Finished Mar 24 01:53:54 PM PDT 24
Peak memory 379604 kb
Host smart-da060728-a21b-4389-9da3-e0e48de2285d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3123641622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3123641622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.452279378
Short name T634
Test name
Test status
Simulation time 75089205820 ps
CPU time 1619.45 seconds
Started Mar 24 01:29:48 PM PDT 24
Finished Mar 24 01:56:48 PM PDT 24
Peak memory 387792 kb
Host smart-ebe2b054-b2af-4c21-8145-e21c5cab9f7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=452279378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.452279378 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.3826548517
Short name T217
Test name
Test status
Simulation time 49324514827 ps
CPU time 1350.33 seconds
Started Mar 24 01:29:48 PM PDT 24
Finished Mar 24 01:52:18 PM PDT 24
Peak memory 337956 kb
Host smart-a99a2904-11cd-47f3-bb43-24aa304aa954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3826548517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3826548517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.1472826231
Short name T603
Test name
Test status
Simulation time 40267433854 ps
CPU time 818.78 seconds
Started Mar 24 01:29:47 PM PDT 24
Finished Mar 24 01:43:26 PM PDT 24
Peak memory 298760 kb
Host smart-a3c8d514-cb1c-45d9-a765-17939f6c9fb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1472826231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.1472826231 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.376029251
Short name T793
Test name
Test status
Simulation time 254833489778 ps
CPU time 3978.75 seconds
Started Mar 24 01:29:48 PM PDT 24
Finished Mar 24 02:36:07 PM PDT 24
Peak memory 654444 kb
Host smart-2581921a-729d-4efe-8c60-48d8068c382c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=376029251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.376029251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.826742222
Short name T602
Test name
Test status
Simulation time 1368853909140 ps
CPU time 4657.35 seconds
Started Mar 24 01:29:50 PM PDT 24
Finished Mar 24 02:47:28 PM PDT 24
Peak memory 570740 kb
Host smart-728972e0-755b-4ac5-a568-56fb84931459
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=826742222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.826742222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.264408049
Short name T548
Test name
Test status
Simulation time 76890052 ps
CPU time 0.8 seconds
Started Mar 24 01:30:11 PM PDT 24
Finished Mar 24 01:30:12 PM PDT 24
Peak memory 205716 kb
Host smart-cf2eed00-f879-49c2-b4fc-7f91daeda478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264408049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.264408049 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.238686235
Short name T841
Test name
Test status
Simulation time 9205094611 ps
CPU time 206.89 seconds
Started Mar 24 01:30:07 PM PDT 24
Finished Mar 24 01:33:34 PM PDT 24
Peak memory 241572 kb
Host smart-6926d9f5-2eb8-4069-a284-6286cf190bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238686235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.238686235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.690217961
Short name T79
Test name
Test status
Simulation time 28074615296 ps
CPU time 600.02 seconds
Started Mar 24 01:30:01 PM PDT 24
Finished Mar 24 01:40:02 PM PDT 24
Peak memory 232280 kb
Host smart-18b47a66-227e-41dd-af90-b94038c301d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690217961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.690217961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.3977716764
Short name T729
Test name
Test status
Simulation time 19709267883 ps
CPU time 124.4 seconds
Started Mar 24 01:30:06 PM PDT 24
Finished Mar 24 01:32:11 PM PDT 24
Peak memory 234844 kb
Host smart-ac94ee24-0152-4496-b8e5-5bce24e92fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977716764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3977716764 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.2355264441
Short name T828
Test name
Test status
Simulation time 17764055679 ps
CPU time 95.66 seconds
Started Mar 24 01:30:06 PM PDT 24
Finished Mar 24 01:31:42 PM PDT 24
Peak memory 240900 kb
Host smart-15100e1b-1edf-4571-9c00-9517f2f1d59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355264441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2355264441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.1716664079
Short name T494
Test name
Test status
Simulation time 3245395086 ps
CPU time 4.86 seconds
Started Mar 24 01:30:07 PM PDT 24
Finished Mar 24 01:30:12 PM PDT 24
Peak memory 207832 kb
Host smart-b56ecb94-9e46-4540-b8e9-ff1da04b93c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716664079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1716664079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.3189485252
Short name T872
Test name
Test status
Simulation time 393239467 ps
CPU time 1.24 seconds
Started Mar 24 01:30:06 PM PDT 24
Finished Mar 24 01:30:08 PM PDT 24
Peak memory 216204 kb
Host smart-44d4702a-e064-481a-bd7a-154c9ad6c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189485252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3189485252 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.1395052853
Short name T576
Test name
Test status
Simulation time 41278868493 ps
CPU time 1123.33 seconds
Started Mar 24 01:29:57 PM PDT 24
Finished Mar 24 01:48:41 PM PDT 24
Peak memory 337552 kb
Host smart-319952fd-bba9-4890-bba2-14247c3bbc68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395052853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.1395052853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.2875109671
Short name T122
Test name
Test status
Simulation time 23850047932 ps
CPU time 309.54 seconds
Started Mar 24 01:29:56 PM PDT 24
Finished Mar 24 01:35:05 PM PDT 24
Peak memory 244048 kb
Host smart-cbb5b777-a2c1-4d84-af33-e276299d90f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875109671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2875109671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.521302405
Short name T1050
Test name
Test status
Simulation time 861942714 ps
CPU time 23.23 seconds
Started Mar 24 01:29:56 PM PDT 24
Finished Mar 24 01:30:20 PM PDT 24
Peak memory 221132 kb
Host smart-2a1ac479-311c-45d4-97b6-e93aa9550f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521302405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.521302405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3760992711
Short name T810
Test name
Test status
Simulation time 24800113750 ps
CPU time 491.94 seconds
Started Mar 24 01:30:08 PM PDT 24
Finished Mar 24 01:38:20 PM PDT 24
Peak memory 273512 kb
Host smart-7d816557-9160-4d64-927a-e58e208d0bfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3760992711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3760992711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.3887789562
Short name T393
Test name
Test status
Simulation time 1012589673 ps
CPU time 5.2 seconds
Started Mar 24 01:30:05 PM PDT 24
Finished Mar 24 01:30:10 PM PDT 24
Peak memory 209828 kb
Host smart-0c867524-0e1a-4a5a-9f77-f487e7a53f48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887789562 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.3887789562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3046786380
Short name T877
Test name
Test status
Simulation time 252601400 ps
CPU time 4.31 seconds
Started Mar 24 01:30:05 PM PDT 24
Finished Mar 24 01:30:10 PM PDT 24
Peak memory 216240 kb
Host smart-af6fc85c-8206-4591-aea5-90e6279e394d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046786380 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3046786380 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.3228645223
Short name T974
Test name
Test status
Simulation time 196932185197 ps
CPU time 2020.46 seconds
Started Mar 24 01:30:01 PM PDT 24
Finished Mar 24 02:03:42 PM PDT 24
Peak memory 389852 kb
Host smart-d88e3f8c-58cd-4a69-9959-06da52c444a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3228645223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.3228645223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.1856562989
Short name T449
Test name
Test status
Simulation time 39234742100 ps
CPU time 1566.35 seconds
Started Mar 24 01:30:02 PM PDT 24
Finished Mar 24 01:56:09 PM PDT 24
Peak memory 388380 kb
Host smart-c1f2e386-9283-44eb-af70-9d4f364b4c79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1856562989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.1856562989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.3058181681
Short name T534
Test name
Test status
Simulation time 196024718050 ps
CPU time 1396.75 seconds
Started Mar 24 01:30:05 PM PDT 24
Finished Mar 24 01:53:22 PM PDT 24
Peak memory 335700 kb
Host smart-16c644ed-e497-485c-8160-586f6eed0899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3058181681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3058181681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.698825369
Short name T897
Test name
Test status
Simulation time 50493501500 ps
CPU time 3766.32 seconds
Started Mar 24 01:30:08 PM PDT 24
Finished Mar 24 02:32:55 PM PDT 24
Peak memory 633188 kb
Host smart-f85503e9-ef8e-48ec-a96d-02269153a9ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=698825369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.698825369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.2933280632
Short name T1012
Test name
Test status
Simulation time 173259586210 ps
CPU time 3559.72 seconds
Started Mar 24 01:30:06 PM PDT 24
Finished Mar 24 02:29:27 PM PDT 24
Peak memory 562712 kb
Host smart-2b86eb8a-4c7a-445e-8794-582e39fbf383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2933280632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2933280632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.490715137
Short name T765
Test name
Test status
Simulation time 34831504 ps
CPU time 0.77 seconds
Started Mar 24 01:30:27 PM PDT 24
Finished Mar 24 01:30:28 PM PDT 24
Peak memory 205672 kb
Host smart-33490253-9870-409f-858c-faeb3dd9dee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490715137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.490715137 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.1463465855
Short name T779
Test name
Test status
Simulation time 24974120412 ps
CPU time 133.8 seconds
Started Mar 24 01:30:22 PM PDT 24
Finished Mar 24 01:32:36 PM PDT 24
Peak memory 232840 kb
Host smart-cacc201b-a345-44cf-b728-a77bcc9c3d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463465855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1463465855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.3691198437
Short name T380
Test name
Test status
Simulation time 3607940581 ps
CPU time 146.97 seconds
Started Mar 24 01:30:11 PM PDT 24
Finished Mar 24 01:32:39 PM PDT 24
Peak memory 224812 kb
Host smart-9f4711c5-6129-4616-9281-ee136754ee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691198437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3691198437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.1227218793
Short name T874
Test name
Test status
Simulation time 1981725816 ps
CPU time 9.13 seconds
Started Mar 24 01:30:22 PM PDT 24
Finished Mar 24 01:30:31 PM PDT 24
Peak memory 221272 kb
Host smart-7ab797a9-4759-4c95-a816-7b50a9ced7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227218793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1227218793 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.180211581
Short name T715
Test name
Test status
Simulation time 54118437334 ps
CPU time 400.56 seconds
Started Mar 24 01:30:27 PM PDT 24
Finished Mar 24 01:37:08 PM PDT 24
Peak memory 265720 kb
Host smart-2c894940-9def-41ea-ba24-3a07de2553aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180211581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.180211581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.1868875784
Short name T802
Test name
Test status
Simulation time 214828503 ps
CPU time 1.17 seconds
Started Mar 24 01:30:27 PM PDT 24
Finished Mar 24 01:30:29 PM PDT 24
Peak memory 206924 kb
Host smart-562e9a5e-ae6f-4253-acd4-0f9da4488348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868875784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1868875784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.1087272437
Short name T981
Test name
Test status
Simulation time 70127364 ps
CPU time 1.35 seconds
Started Mar 24 01:30:28 PM PDT 24
Finished Mar 24 01:30:30 PM PDT 24
Peak memory 216148 kb
Host smart-a489701f-4231-48c2-87ee-fdb5df1689c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087272437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1087272437 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.2618285300
Short name T359
Test name
Test status
Simulation time 61687607251 ps
CPU time 1806.58 seconds
Started Mar 24 01:30:11 PM PDT 24
Finished Mar 24 02:00:18 PM PDT 24
Peak memory 394612 kb
Host smart-e31ff352-8ed2-4f3b-862e-87db35ab73c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618285300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.2618285300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.2965095416
Short name T836
Test name
Test status
Simulation time 7689867954 ps
CPU time 160.45 seconds
Started Mar 24 01:30:11 PM PDT 24
Finished Mar 24 01:32:51 PM PDT 24
Peak memory 235692 kb
Host smart-8ac56bf7-d045-47fd-a046-c467898a3616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965095416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2965095416 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.2998846117
Short name T287
Test name
Test status
Simulation time 5837549102 ps
CPU time 34.8 seconds
Started Mar 24 01:30:11 PM PDT 24
Finished Mar 24 01:30:46 PM PDT 24
Peak memory 219744 kb
Host smart-670b32b2-4b48-43f0-854d-dcd8f78193dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998846117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2998846117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.3907974356
Short name T956
Test name
Test status
Simulation time 3394085395 ps
CPU time 74.61 seconds
Started Mar 24 01:30:26 PM PDT 24
Finished Mar 24 01:31:41 PM PDT 24
Peak memory 241148 kb
Host smart-e85b6981-3bf5-4faf-aa44-85de4db23b14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3907974356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3907974356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1162969917
Short name T354
Test name
Test status
Simulation time 67241641 ps
CPU time 3.7 seconds
Started Mar 24 01:30:15 PM PDT 24
Finished Mar 24 01:30:19 PM PDT 24
Peak memory 216200 kb
Host smart-b7bad4a3-cfd9-4573-8dee-4efe5a7a01d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162969917 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1162969917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.1499045086
Short name T377
Test name
Test status
Simulation time 67647716 ps
CPU time 4.18 seconds
Started Mar 24 01:30:23 PM PDT 24
Finished Mar 24 01:30:27 PM PDT 24
Peak memory 216256 kb
Host smart-d49b7320-7eb4-4879-87de-487ca22a5533
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499045086 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.1499045086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.3426826695
Short name T893
Test name
Test status
Simulation time 268697688461 ps
CPU time 1852.78 seconds
Started Mar 24 01:30:16 PM PDT 24
Finished Mar 24 02:01:09 PM PDT 24
Peak memory 390144 kb
Host smart-879c9fc1-e391-4df3-9951-a17208e39316
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3426826695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.3426826695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.1332733727
Short name T295
Test name
Test status
Simulation time 188387979491 ps
CPU time 1863.31 seconds
Started Mar 24 01:30:18 PM PDT 24
Finished Mar 24 02:01:23 PM PDT 24
Peak memory 370952 kb
Host smart-a2530030-13c5-46c1-b65b-27e1258c2524
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1332733727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.1332733727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.3774379552
Short name T616
Test name
Test status
Simulation time 246685079651 ps
CPU time 1316.41 seconds
Started Mar 24 01:30:17 PM PDT 24
Finished Mar 24 01:52:14 PM PDT 24
Peak memory 339400 kb
Host smart-434f8a05-41c8-49ec-84be-a1dcb91d94f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3774379552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.3774379552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.3494575032
Short name T608
Test name
Test status
Simulation time 72567395392 ps
CPU time 858.23 seconds
Started Mar 24 01:30:17 PM PDT 24
Finished Mar 24 01:44:36 PM PDT 24
Peak memory 293696 kb
Host smart-731fbc96-698d-4d3d-b790-24082f687882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3494575032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.3494575032 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.4147748229
Short name T727
Test name
Test status
Simulation time 2309630702037 ps
CPU time 6150.52 seconds
Started Mar 24 01:30:16 PM PDT 24
Finished Mar 24 03:12:49 PM PDT 24
Peak memory 639752 kb
Host smart-e22b5652-9f00-4d5e-bc49-d3b86f2fc40c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4147748229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.4147748229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.2153898002
Short name T830
Test name
Test status
Simulation time 292217375924 ps
CPU time 3840.41 seconds
Started Mar 24 01:30:16 PM PDT 24
Finished Mar 24 02:34:17 PM PDT 24
Peak memory 574340 kb
Host smart-0e48694b-68a5-49e0-8236-c09df7a93783
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2153898002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.2153898002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.910577790
Short name T555
Test name
Test status
Simulation time 13826852 ps
CPU time 0.77 seconds
Started Mar 24 01:30:48 PM PDT 24
Finished Mar 24 01:30:49 PM PDT 24
Peak memory 205700 kb
Host smart-fa29130b-e1f6-48fb-8237-b022a39808d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910577790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.910577790 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_burst_write.546806226
Short name T726
Test name
Test status
Simulation time 18217319383 ps
CPU time 380 seconds
Started Mar 24 01:30:27 PM PDT 24
Finished Mar 24 01:36:48 PM PDT 24
Peak memory 228860 kb
Host smart-3f7dda05-cfd2-447a-8d27-a78dbb2cc3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546806226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.546806226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.3146347948
Short name T154
Test name
Test status
Simulation time 11173924332 ps
CPU time 107.21 seconds
Started Mar 24 01:30:38 PM PDT 24
Finished Mar 24 01:32:26 PM PDT 24
Peak memory 231292 kb
Host smart-0fb5efa2-a97a-4e11-b199-2aae0ffddb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146347948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3146347948 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.3554033362
Short name T283
Test name
Test status
Simulation time 14020462313 ps
CPU time 163.8 seconds
Started Mar 24 01:30:38 PM PDT 24
Finished Mar 24 01:33:22 PM PDT 24
Peak memory 252352 kb
Host smart-92a936e7-3b85-4134-bf6e-5dc230a00634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554033362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3554033362 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.1500935631
Short name T20
Test name
Test status
Simulation time 5928227147 ps
CPU time 3.2 seconds
Started Mar 24 01:30:40 PM PDT 24
Finished Mar 24 01:30:44 PM PDT 24
Peak memory 207868 kb
Host smart-319402a3-b25b-4c37-982e-8e814125855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500935631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1500935631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.2644376264
Short name T424
Test name
Test status
Simulation time 58873255 ps
CPU time 1.27 seconds
Started Mar 24 01:30:42 PM PDT 24
Finished Mar 24 01:30:44 PM PDT 24
Peak memory 216208 kb
Host smart-7f205a3c-7582-4f32-be0b-491dbae0601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644376264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2644376264 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.3589342929
Short name T914
Test name
Test status
Simulation time 227417200749 ps
CPU time 1768.19 seconds
Started Mar 24 01:30:28 PM PDT 24
Finished Mar 24 01:59:56 PM PDT 24
Peak memory 376200 kb
Host smart-1ffaa310-4d2c-47c1-ac84-3c7cd1312bd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589342929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.3589342929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.3877548135
Short name T273
Test name
Test status
Simulation time 1380753877 ps
CPU time 95.36 seconds
Started Mar 24 01:30:27 PM PDT 24
Finished Mar 24 01:32:02 PM PDT 24
Peak memory 230512 kb
Host smart-5b843f38-3f3a-46c3-a88a-e8ce89ce380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877548135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3877548135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.2008890905
Short name T104
Test name
Test status
Simulation time 6711553725 ps
CPU time 66.88 seconds
Started Mar 24 01:30:27 PM PDT 24
Finished Mar 24 01:31:35 PM PDT 24
Peak memory 224536 kb
Host smart-d9234c92-287b-49d8-8127-d07d54de3123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008890905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.2008890905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all_with_rand_reset.2394563933
Short name T142
Test name
Test status
Simulation time 17749318048 ps
CPU time 358.65 seconds
Started Mar 24 01:30:42 PM PDT 24
Finished Mar 24 01:36:41 PM PDT 24
Peak memory 255080 kb
Host smart-fa5fcaa4-14db-4230-8988-e0b86e2f258b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2394563933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all_with_rand_reset.2394563933 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.309923088
Short name T1016
Test name
Test status
Simulation time 255532733 ps
CPU time 4.71 seconds
Started Mar 24 01:30:31 PM PDT 24
Finished Mar 24 01:30:36 PM PDT 24
Peak memory 216268 kb
Host smart-6933ab5b-6028-4979-a4ca-acab8f5ca16e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309923088 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.kmac_test_vectors_kmac.309923088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.3055170877
Short name T218
Test name
Test status
Simulation time 1053282360 ps
CPU time 5.47 seconds
Started Mar 24 01:30:31 PM PDT 24
Finished Mar 24 01:30:36 PM PDT 24
Peak memory 216284 kb
Host smart-1ad8bd13-f77d-4eb7-875a-4649dc40b789
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055170877 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.3055170877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2324437473
Short name T1009
Test name
Test status
Simulation time 406264212765 ps
CPU time 2023.89 seconds
Started Mar 24 01:30:29 PM PDT 24
Finished Mar 24 02:04:14 PM PDT 24
Peak memory 393176 kb
Host smart-882cc514-3b45-4479-a8ea-5cc061f7768a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2324437473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2324437473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.202741158
Short name T1013
Test name
Test status
Simulation time 127697597588 ps
CPU time 1727.85 seconds
Started Mar 24 01:30:27 PM PDT 24
Finished Mar 24 01:59:15 PM PDT 24
Peak memory 375852 kb
Host smart-442d7610-0971-4e88-bd17-b98ef94cb8a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=202741158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.202741158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.324882349
Short name T132
Test name
Test status
Simulation time 99748329106 ps
CPU time 1294.19 seconds
Started Mar 24 01:30:32 PM PDT 24
Finished Mar 24 01:52:07 PM PDT 24
Peak memory 340912 kb
Host smart-1f1f0797-088e-47d0-ae8e-3482d47219a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=324882349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.324882349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.2225852179
Short name T343
Test name
Test status
Simulation time 83553457885 ps
CPU time 935.89 seconds
Started Mar 24 01:30:32 PM PDT 24
Finished Mar 24 01:46:08 PM PDT 24
Peak memory 292908 kb
Host smart-0e755eb8-b28d-4e32-ac95-b144c8119465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2225852179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2225852179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.1194825960
Short name T903
Test name
Test status
Simulation time 1291377696175 ps
CPU time 4792.94 seconds
Started Mar 24 01:30:34 PM PDT 24
Finished Mar 24 02:50:27 PM PDT 24
Peak memory 636448 kb
Host smart-d26fe836-32e8-4da5-95e2-bf7408d6a70f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1194825960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.1194825960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.1881412372
Short name T247
Test name
Test status
Simulation time 182647769535 ps
CPU time 3425.65 seconds
Started Mar 24 01:30:34 PM PDT 24
Finished Mar 24 02:27:40 PM PDT 24
Peak memory 572836 kb
Host smart-62ca1f9b-8c70-4ce6-8924-eeb247ccbbad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1881412372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.1881412372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.1618679103
Short name T666
Test name
Test status
Simulation time 63919150 ps
CPU time 0.83 seconds
Started Mar 24 01:30:58 PM PDT 24
Finished Mar 24 01:30:59 PM PDT 24
Peak memory 205740 kb
Host smart-6b17078f-6006-4de5-b961-cbc8967772ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618679103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1618679103 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.2118060946
Short name T381
Test name
Test status
Simulation time 29292995177 ps
CPU time 59.31 seconds
Started Mar 24 01:30:53 PM PDT 24
Finished Mar 24 01:31:52 PM PDT 24
Peak memory 224532 kb
Host smart-10db13b9-d030-47e3-8d15-9b74955ddd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118060946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2118060946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.2644497979
Short name T370
Test name
Test status
Simulation time 43345445013 ps
CPU time 233.45 seconds
Started Mar 24 01:30:52 PM PDT 24
Finished Mar 24 01:34:45 PM PDT 24
Peak memory 242244 kb
Host smart-c9fb3411-7725-4c17-9ce6-3cd0a0cb5065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644497979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2644497979 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.2979044639
Short name T191
Test name
Test status
Simulation time 18975922171 ps
CPU time 343.34 seconds
Started Mar 24 01:30:53 PM PDT 24
Finished Mar 24 01:36:37 PM PDT 24
Peak memory 264656 kb
Host smart-fe2818e3-4789-4c4c-8135-ff8d5365cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979044639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2979044639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.2069700821
Short name T527
Test name
Test status
Simulation time 421717723 ps
CPU time 2.77 seconds
Started Mar 24 01:31:00 PM PDT 24
Finished Mar 24 01:31:03 PM PDT 24
Peak memory 207628 kb
Host smart-d7e59b32-ccd6-496c-91da-189252c3879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069700821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2069700821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.3616819911
Short name T41
Test name
Test status
Simulation time 41720355 ps
CPU time 1.34 seconds
Started Mar 24 01:31:03 PM PDT 24
Finished Mar 24 01:31:05 PM PDT 24
Peak memory 216156 kb
Host smart-85f8658f-726c-4480-9fd4-54086bcc0c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616819911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3616819911 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.3407467887
Short name T580
Test name
Test status
Simulation time 1855145596 ps
CPU time 164.65 seconds
Started Mar 24 01:30:46 PM PDT 24
Finished Mar 24 01:33:31 PM PDT 24
Peak memory 240788 kb
Host smart-dfdbfd05-a123-4a2a-a238-54e1ac4f026f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407467887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.3407467887 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.1084814630
Short name T523
Test name
Test status
Simulation time 4413391695 ps
CPU time 378.23 seconds
Started Mar 24 01:30:49 PM PDT 24
Finished Mar 24 01:37:08 PM PDT 24
Peak memory 250648 kb
Host smart-1fe9f020-7af3-4419-94e5-a1790009015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084814630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1084814630 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.700860065
Short name T724
Test name
Test status
Simulation time 1675681725 ps
CPU time 41.16 seconds
Started Mar 24 01:30:47 PM PDT 24
Finished Mar 24 01:31:28 PM PDT 24
Peak memory 218304 kb
Host smart-f1c2a541-8a60-4733-ac13-b3300ebb311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700860065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.700860065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.2005479541
Short name T869
Test name
Test status
Simulation time 44720942520 ps
CPU time 1289.24 seconds
Started Mar 24 01:30:59 PM PDT 24
Finished Mar 24 01:52:28 PM PDT 24
Peak memory 371060 kb
Host smart-6b6e240b-1142-46ac-99c1-033249a924b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2005479541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2005479541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.2507146502
Short name T327
Test name
Test status
Simulation time 68935674 ps
CPU time 3.97 seconds
Started Mar 24 01:30:52 PM PDT 24
Finished Mar 24 01:30:56 PM PDT 24
Peak memory 216240 kb
Host smart-3c447c61-5d33-4405-b8df-9aa955b180d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507146502 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.2507146502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.2575717539
Short name T611
Test name
Test status
Simulation time 246395892 ps
CPU time 5.16 seconds
Started Mar 24 01:30:53 PM PDT 24
Finished Mar 24 01:30:59 PM PDT 24
Peak memory 216296 kb
Host smart-a80667e5-7dfc-471a-9f96-8a0bc790f647
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575717539 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.2575717539 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.692362903
Short name T890
Test name
Test status
Simulation time 79124773640 ps
CPU time 1632.37 seconds
Started Mar 24 01:30:48 PM PDT 24
Finished Mar 24 01:58:01 PM PDT 24
Peak memory 395656 kb
Host smart-8c8100ec-bd23-4c92-94a2-c664aa5e4f4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=692362903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.692362903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.2658975868
Short name T573
Test name
Test status
Simulation time 96685093577 ps
CPU time 1852.71 seconds
Started Mar 24 01:30:49 PM PDT 24
Finished Mar 24 02:01:42 PM PDT 24
Peak memory 375272 kb
Host smart-7253d9b6-9726-45a0-9cb7-90a672ffa218
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2658975868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.2658975868 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.4132792809
Short name T934
Test name
Test status
Simulation time 124020867782 ps
CPU time 1177.53 seconds
Started Mar 24 01:30:49 PM PDT 24
Finished Mar 24 01:50:26 PM PDT 24
Peak memory 335308 kb
Host smart-fcc833e6-110f-4dd9-8021-ae8e74297594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4132792809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.4132792809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.2101281047
Short name T661
Test name
Test status
Simulation time 19356907074 ps
CPU time 796.97 seconds
Started Mar 24 01:30:48 PM PDT 24
Finished Mar 24 01:44:05 PM PDT 24
Peak memory 294832 kb
Host smart-f330357a-3d6b-438d-9965-6d2e4be41384
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2101281047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.2101281047 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.136416060
Short name T440
Test name
Test status
Simulation time 85828458066 ps
CPU time 4141.35 seconds
Started Mar 24 01:30:49 PM PDT 24
Finished Mar 24 02:39:51 PM PDT 24
Peak memory 648760 kb
Host smart-cbcd0e29-448c-4077-bbe7-e1b17165abb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=136416060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.136416060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.3114219314
Short name T178
Test name
Test status
Simulation time 854286693346 ps
CPU time 4179.91 seconds
Started Mar 24 01:30:53 PM PDT 24
Finished Mar 24 02:40:34 PM PDT 24
Peak memory 560940 kb
Host smart-393d17c6-b7f2-4d3d-8f11-f303a9cec2e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3114219314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.3114219314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.3773039846
Short name T242
Test name
Test status
Simulation time 25293042 ps
CPU time 0.77 seconds
Started Mar 24 01:31:14 PM PDT 24
Finished Mar 24 01:31:15 PM PDT 24
Peak memory 205660 kb
Host smart-a3fecbf1-7342-434d-99a1-51e19773639f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773039846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3773039846 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.1019961919
Short name T777
Test name
Test status
Simulation time 59991929379 ps
CPU time 82.77 seconds
Started Mar 24 01:31:09 PM PDT 24
Finished Mar 24 01:32:32 PM PDT 24
Peak memory 225744 kb
Host smart-18c09fcc-1cc8-4c9a-9ea0-d02348e08f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019961919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1019961919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.4004344790
Short name T50
Test name
Test status
Simulation time 15403991071 ps
CPU time 283.92 seconds
Started Mar 24 01:31:04 PM PDT 24
Finished Mar 24 01:35:48 PM PDT 24
Peak memory 227480 kb
Host smart-45a95e95-3759-4ffe-bbc4-bd326e1f19d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004344790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.4004344790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.1958568045
Short name T278
Test name
Test status
Simulation time 6714331132 ps
CPU time 258.26 seconds
Started Mar 24 01:31:10 PM PDT 24
Finished Mar 24 01:35:29 PM PDT 24
Peak memory 247428 kb
Host smart-d2f9ff2e-686b-4e94-a71c-49bf6e77b47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958568045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1958568045 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.227060167
Short name T636
Test name
Test status
Simulation time 4561454132 ps
CPU time 86.68 seconds
Started Mar 24 01:31:08 PM PDT 24
Finished Mar 24 01:32:35 PM PDT 24
Peak memory 236376 kb
Host smart-a933ecac-ace5-4707-9db8-bf9b794f6e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227060167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.227060167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.25921229
Short name T492
Test name
Test status
Simulation time 780641178 ps
CPU time 1.84 seconds
Started Mar 24 01:31:09 PM PDT 24
Finished Mar 24 01:31:12 PM PDT 24
Peak memory 207520 kb
Host smart-03258252-ba3c-4f2e-9987-d4f572d44f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25921229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.25921229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.1619138508
Short name T485
Test name
Test status
Simulation time 41164069 ps
CPU time 1.27 seconds
Started Mar 24 01:31:08 PM PDT 24
Finished Mar 24 01:31:10 PM PDT 24
Peak memory 216124 kb
Host smart-457f6b60-bffc-4dd4-b611-2e4f57391343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619138508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1619138508 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.1764231594
Short name T863
Test name
Test status
Simulation time 28670297671 ps
CPU time 857.57 seconds
Started Mar 24 01:31:03 PM PDT 24
Finished Mar 24 01:45:22 PM PDT 24
Peak memory 302308 kb
Host smart-d052c2a3-76a8-47a5-8593-31bf64ecd7ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764231594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.1764231594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.3207386001
Short name T461
Test name
Test status
Simulation time 39700211070 ps
CPU time 395.94 seconds
Started Mar 24 01:31:05 PM PDT 24
Finished Mar 24 01:37:41 PM PDT 24
Peak memory 247856 kb
Host smart-a00e1d68-2cce-4e98-be7d-8d01b893d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207386001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3207386001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.2406407907
Short name T913
Test name
Test status
Simulation time 1691203981 ps
CPU time 36.08 seconds
Started Mar 24 01:31:05 PM PDT 24
Finished Mar 24 01:31:41 PM PDT 24
Peak memory 220672 kb
Host smart-a7b4c21d-a24c-4136-ba4b-b6a70a065870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406407907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2406407907 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.3112210116
Short name T382
Test name
Test status
Simulation time 30355742515 ps
CPU time 581.4 seconds
Started Mar 24 01:31:15 PM PDT 24
Finished Mar 24 01:40:56 PM PDT 24
Peak memory 314940 kb
Host smart-880a07b9-6224-448a-bd95-670fa216044e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3112210116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3112210116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.509518431
Short name T220
Test name
Test status
Simulation time 904484436 ps
CPU time 5.22 seconds
Started Mar 24 01:31:03 PM PDT 24
Finished Mar 24 01:31:09 PM PDT 24
Peak memory 216284 kb
Host smart-0a49991d-6402-43cc-861a-125312cc5ffb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509518431 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.kmac_test_vectors_kmac.509518431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.1813448034
Short name T311
Test name
Test status
Simulation time 2357666725 ps
CPU time 4.99 seconds
Started Mar 24 01:31:03 PM PDT 24
Finished Mar 24 01:31:09 PM PDT 24
Peak memory 216360 kb
Host smart-95fb076e-6405-49a8-91c4-b5411728767a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813448034 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.1813448034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.2392255199
Short name T284
Test name
Test status
Simulation time 20700711801 ps
CPU time 1603.61 seconds
Started Mar 24 01:31:03 PM PDT 24
Finished Mar 24 01:57:47 PM PDT 24
Peak memory 392612 kb
Host smart-7e102ad8-e514-4866-ac7c-68a7e5638f24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2392255199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2392255199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.823573501
Short name T365
Test name
Test status
Simulation time 187763816956 ps
CPU time 1830.19 seconds
Started Mar 24 01:31:04 PM PDT 24
Finished Mar 24 02:01:34 PM PDT 24
Peak memory 376308 kb
Host smart-2a81fd9b-c013-4098-99c1-8655c367862d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=823573501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.823573501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.320158300
Short name T592
Test name
Test status
Simulation time 64716656890 ps
CPU time 1262.94 seconds
Started Mar 24 01:31:06 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 337496 kb
Host smart-5625405a-ae07-488b-922d-ade55b649b7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=320158300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.320158300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.1832403485
Short name T467
Test name
Test status
Simulation time 9934996870 ps
CPU time 840.85 seconds
Started Mar 24 01:31:04 PM PDT 24
Finished Mar 24 01:45:05 PM PDT 24
Peak memory 298780 kb
Host smart-803c039c-ee47-4ae9-aaf4-bc662e3f5fa9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1832403485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.1832403485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.4160111761
Short name T923
Test name
Test status
Simulation time 210021180590 ps
CPU time 4335.09 seconds
Started Mar 24 01:31:04 PM PDT 24
Finished Mar 24 02:43:20 PM PDT 24
Peak memory 641248 kb
Host smart-f2885e6d-991d-4110-a0a5-ee401f533af9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4160111761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.4160111761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.550922149
Short name T761
Test name
Test status
Simulation time 301123839914 ps
CPU time 3823.53 seconds
Started Mar 24 01:31:04 PM PDT 24
Finished Mar 24 02:34:48 PM PDT 24
Peak memory 557516 kb
Host smart-dd9260e1-2568-43f6-bfe4-29800cc64f4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=550922149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.550922149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3277166056
Short name T808
Test name
Test status
Simulation time 15720318 ps
CPU time 0.82 seconds
Started Mar 24 01:31:36 PM PDT 24
Finished Mar 24 01:31:37 PM PDT 24
Peak memory 205668 kb
Host smart-e35d3109-99d9-4215-a548-5e78f330dc2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277166056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3277166056 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1107828452
Short name T739
Test name
Test status
Simulation time 20811835263 ps
CPU time 97.59 seconds
Started Mar 24 01:31:25 PM PDT 24
Finished Mar 24 01:33:02 PM PDT 24
Peak memory 231216 kb
Host smart-675a77d6-32df-47f8-9d20-132177622760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107828452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1107828452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.453506862
Short name T1081
Test name
Test status
Simulation time 43633067109 ps
CPU time 698.57 seconds
Started Mar 24 01:31:19 PM PDT 24
Finished Mar 24 01:42:58 PM PDT 24
Peak memory 233188 kb
Host smart-393b52bd-038a-4fe8-b199-f0411ae2b585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453506862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.453506862 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.2604571280
Short name T397
Test name
Test status
Simulation time 29393147330 ps
CPU time 178.07 seconds
Started Mar 24 01:31:30 PM PDT 24
Finished Mar 24 01:34:28 PM PDT 24
Peak memory 236032 kb
Host smart-dfb95fb2-a50f-45df-961f-dd4374ea20bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604571280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2604571280 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.1934402427
Short name T396
Test name
Test status
Simulation time 23399762619 ps
CPU time 76.65 seconds
Started Mar 24 01:31:33 PM PDT 24
Finished Mar 24 01:32:50 PM PDT 24
Peak memory 240868 kb
Host smart-922e255c-6f54-4c9b-bf97-c6bf863e8186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934402427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1934402427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.72926288
Short name T1067
Test name
Test status
Simulation time 6633565197 ps
CPU time 6.04 seconds
Started Mar 24 01:31:33 PM PDT 24
Finished Mar 24 01:31:40 PM PDT 24
Peak memory 207868 kb
Host smart-a87dcc0e-9cb5-4146-a9b6-e109c8d8128c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72926288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.72926288 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.962660782
Short name T442
Test name
Test status
Simulation time 100699460 ps
CPU time 1.3 seconds
Started Mar 24 01:31:29 PM PDT 24
Finished Mar 24 01:31:31 PM PDT 24
Peak memory 216328 kb
Host smart-aad158f0-674f-4dba-b567-eaec2c8f725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962660782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.962660782 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.3572324463
Short name T957
Test name
Test status
Simulation time 149794976705 ps
CPU time 2253.84 seconds
Started Mar 24 01:31:21 PM PDT 24
Finished Mar 24 02:08:56 PM PDT 24
Peak memory 432368 kb
Host smart-34cb8fe8-ebe6-4fea-a69b-426370561a24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572324463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.3572324463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.1282934138
Short name T699
Test name
Test status
Simulation time 11533024691 ps
CPU time 270.14 seconds
Started Mar 24 01:31:20 PM PDT 24
Finished Mar 24 01:35:51 PM PDT 24
Peak memory 241848 kb
Host smart-3ff7e1e3-f1a9-4c10-90bb-7ec2d788035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282934138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1282934138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.2547714685
Short name T601
Test name
Test status
Simulation time 2873851726 ps
CPU time 58.93 seconds
Started Mar 24 01:31:13 PM PDT 24
Finished Mar 24 01:32:12 PM PDT 24
Peak memory 222992 kb
Host smart-df123324-1dfe-4427-8d8a-15385d681818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547714685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2547714685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.3810286116
Short name T817
Test name
Test status
Simulation time 167378030671 ps
CPU time 1128.58 seconds
Started Mar 24 01:31:37 PM PDT 24
Finished Mar 24 01:50:26 PM PDT 24
Peak memory 358952 kb
Host smart-2ce5023f-03a1-4906-9c27-9d5719b22050
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3810286116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3810286116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.564643015
Short name T658
Test name
Test status
Simulation time 714604287 ps
CPU time 4.68 seconds
Started Mar 24 01:31:24 PM PDT 24
Finished Mar 24 01:31:29 PM PDT 24
Peak memory 216264 kb
Host smart-75396fb3-4eec-419f-8931-19008ab9bd48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564643015 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.kmac_test_vectors_kmac.564643015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.1929373206
Short name T920
Test name
Test status
Simulation time 68300818 ps
CPU time 3.92 seconds
Started Mar 24 01:31:25 PM PDT 24
Finished Mar 24 01:31:29 PM PDT 24
Peak memory 216304 kb
Host smart-44347189-abba-4d7f-bbf9-f4e3d782a34b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929373206 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.1929373206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.2868410098
Short name T339
Test name
Test status
Simulation time 86275119250 ps
CPU time 1798.9 seconds
Started Mar 24 01:31:21 PM PDT 24
Finished Mar 24 02:01:20 PM PDT 24
Peak memory 378668 kb
Host smart-a68b8f6e-a513-4218-84b2-2225c0bdc9e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2868410098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.2868410098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.305830500
Short name T419
Test name
Test status
Simulation time 91781204330 ps
CPU time 1839.65 seconds
Started Mar 24 01:31:22 PM PDT 24
Finished Mar 24 02:02:02 PM PDT 24
Peak memory 368892 kb
Host smart-31587890-24fa-41a8-b6f7-11e2318473c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=305830500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.305830500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.2858350411
Short name T465
Test name
Test status
Simulation time 70945752860 ps
CPU time 1468.58 seconds
Started Mar 24 01:31:20 PM PDT 24
Finished Mar 24 01:55:49 PM PDT 24
Peak memory 330228 kb
Host smart-a53cc6af-15eb-4652-a59c-531d6289022c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2858350411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.2858350411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.449733440
Short name T259
Test name
Test status
Simulation time 22382167352 ps
CPU time 802.97 seconds
Started Mar 24 01:31:19 PM PDT 24
Finished Mar 24 01:44:42 PM PDT 24
Peak memory 298452 kb
Host smart-3732db22-b6bb-470d-9d23-f9fc030b5289
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=449733440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.449733440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.3257807424
Short name T973
Test name
Test status
Simulation time 203939377813 ps
CPU time 4137.01 seconds
Started Mar 24 01:31:19 PM PDT 24
Finished Mar 24 02:40:17 PM PDT 24
Peak memory 653552 kb
Host smart-d377e422-0316-4d3f-8f47-8cdd1b582bab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3257807424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3257807424 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.614158590
Short name T448
Test name
Test status
Simulation time 991588284379 ps
CPU time 4591.43 seconds
Started Mar 24 01:31:24 PM PDT 24
Finished Mar 24 02:47:56 PM PDT 24
Peak memory 563260 kb
Host smart-ba958e21-5ccf-4543-b23f-3738580747c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=614158590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.614158590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.43317736
Short name T314
Test name
Test status
Simulation time 52020192 ps
CPU time 0.82 seconds
Started Mar 24 01:31:52 PM PDT 24
Finished Mar 24 01:31:53 PM PDT 24
Peak memory 205672 kb
Host smart-29c163bf-ea23-4bc8-b463-46e491289055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43317736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.43317736 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.1101553707
Short name T695
Test name
Test status
Simulation time 5718205232 ps
CPU time 179.72 seconds
Started Mar 24 01:31:46 PM PDT 24
Finished Mar 24 01:34:47 PM PDT 24
Peak memory 237824 kb
Host smart-00cc83ec-bebe-4f1e-899b-db3cd09acabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101553707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1101553707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.2252542590
Short name T157
Test name
Test status
Simulation time 88338361185 ps
CPU time 597.59 seconds
Started Mar 24 01:31:38 PM PDT 24
Finished Mar 24 01:41:36 PM PDT 24
Peak memory 230044 kb
Host smart-ed0c4577-ebcc-4e5c-a0f9-bc33b1d6f36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252542590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2252542590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.3335152539
Short name T495
Test name
Test status
Simulation time 8197830458 ps
CPU time 74.58 seconds
Started Mar 24 01:31:48 PM PDT 24
Finished Mar 24 01:33:03 PM PDT 24
Peak memory 228316 kb
Host smart-89aea088-299e-473c-b52a-cb055988f0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335152539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3335152539 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_key_error.3902922011
Short name T792
Test name
Test status
Simulation time 3160085836 ps
CPU time 5.05 seconds
Started Mar 24 01:31:46 PM PDT 24
Finished Mar 24 01:31:52 PM PDT 24
Peak memory 207956 kb
Host smart-51396085-805d-466e-8d1b-18edef232d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902922011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3902922011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1450210599
Short name T900
Test name
Test status
Simulation time 2820150055 ps
CPU time 11.79 seconds
Started Mar 24 01:31:46 PM PDT 24
Finished Mar 24 01:31:58 PM PDT 24
Peak memory 224576 kb
Host smart-9490961c-1f01-47c2-9672-635bfe143de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450210599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1450210599 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.2735927914
Short name T731
Test name
Test status
Simulation time 109716152371 ps
CPU time 1554.16 seconds
Started Mar 24 01:31:35 PM PDT 24
Finished Mar 24 01:57:29 PM PDT 24
Peak memory 368588 kb
Host smart-01fed743-7916-4c3e-8654-e751d04897c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735927914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.2735927914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.2269344870
Short name T88
Test name
Test status
Simulation time 4265066184 ps
CPU time 328.75 seconds
Started Mar 24 01:31:38 PM PDT 24
Finished Mar 24 01:37:07 PM PDT 24
Peak memory 248240 kb
Host smart-6af8352b-6d39-4ace-9dad-68fad9ac3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269344870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.2269344870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.1691570075
Short name T1080
Test name
Test status
Simulation time 507212184 ps
CPU time 4.13 seconds
Started Mar 24 01:31:35 PM PDT 24
Finished Mar 24 01:31:40 PM PDT 24
Peak memory 224380 kb
Host smart-f66b4f8e-2683-4b78-8b97-1cc8f4407b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691570075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1691570075 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.2706355957
Short name T566
Test name
Test status
Simulation time 6964026186 ps
CPU time 124.22 seconds
Started Mar 24 01:31:46 PM PDT 24
Finished Mar 24 01:33:50 PM PDT 24
Peak memory 254896 kb
Host smart-b3f41c3f-d255-4c5f-9d74-2d4d83eb91e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2706355957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2706355957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.892900949
Short name T971
Test name
Test status
Simulation time 72953213 ps
CPU time 4.24 seconds
Started Mar 24 01:31:41 PM PDT 24
Finished Mar 24 01:31:46 PM PDT 24
Peak memory 216252 kb
Host smart-c15bbbb5-5ff5-480e-8adc-f6ef78448745
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892900949 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.kmac_test_vectors_kmac.892900949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.4075160735
Short name T1011
Test name
Test status
Simulation time 70341645 ps
CPU time 4.29 seconds
Started Mar 24 01:31:41 PM PDT 24
Finished Mar 24 01:31:46 PM PDT 24
Peak memory 216328 kb
Host smart-e3da50f1-4379-4a78-9d47-c568532177b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075160735 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.4075160735 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.2516307213
Short name T961
Test name
Test status
Simulation time 365050599834 ps
CPU time 1820.6 seconds
Started Mar 24 01:31:36 PM PDT 24
Finished Mar 24 02:01:57 PM PDT 24
Peak memory 397268 kb
Host smart-003d04e8-4f86-4cb7-9f30-bb7b2e3aaeeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2516307213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2516307213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.2593155564
Short name T590
Test name
Test status
Simulation time 79829283532 ps
CPU time 1564.91 seconds
Started Mar 24 01:31:36 PM PDT 24
Finished Mar 24 01:57:41 PM PDT 24
Peak memory 366120 kb
Host smart-cecb0288-45b7-4bd8-be19-0e74948a119f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2593155564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.2593155564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.2939589145
Short name T360
Test name
Test status
Simulation time 63962732940 ps
CPU time 1310.21 seconds
Started Mar 24 01:31:38 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 337776 kb
Host smart-8ef2f696-021b-413f-9974-9fa97457e848
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2939589145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.2939589145 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.1222298408
Short name T261
Test name
Test status
Simulation time 65591943524 ps
CPU time 939.37 seconds
Started Mar 24 01:31:40 PM PDT 24
Finished Mar 24 01:47:20 PM PDT 24
Peak memory 292440 kb
Host smart-21989ca1-dfc3-42a8-8f5b-ebf982501ead
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1222298408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.1222298408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.2361683905
Short name T300
Test name
Test status
Simulation time 211232568160 ps
CPU time 3954.6 seconds
Started Mar 24 01:31:42 PM PDT 24
Finished Mar 24 02:37:37 PM PDT 24
Peak memory 647388 kb
Host smart-2aca24af-cb39-413a-a176-69d57730b2c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2361683905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.2361683905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.1036880583
Short name T639
Test name
Test status
Simulation time 160159105086 ps
CPU time 3377.88 seconds
Started Mar 24 01:31:41 PM PDT 24
Finished Mar 24 02:27:59 PM PDT 24
Peak memory 561076 kb
Host smart-82471c72-6138-490d-ae1a-d25ea4613736
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1036880583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1036880583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.3874782064
Short name T783
Test name
Test status
Simulation time 16319232 ps
CPU time 0.78 seconds
Started Mar 24 01:25:45 PM PDT 24
Finished Mar 24 01:25:46 PM PDT 24
Peak memory 205700 kb
Host smart-71e20d3e-f3f2-4778-b618-d2a69950d24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874782064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3874782064 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.1821522480
Short name T979
Test name
Test status
Simulation time 19365909647 ps
CPU time 253.76 seconds
Started Mar 24 01:25:39 PM PDT 24
Finished Mar 24 01:29:52 PM PDT 24
Peak memory 244788 kb
Host smart-178f2c77-bb15-4de4-9d45-ba9ba7cb4156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821522480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1821522480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.2081242185
Short name T89
Test name
Test status
Simulation time 9281784659 ps
CPU time 230.99 seconds
Started Mar 24 01:25:40 PM PDT 24
Finished Mar 24 01:29:31 PM PDT 24
Peak memory 242284 kb
Host smart-edca74db-328c-4033-bbd0-948565c69360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081242185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2081242185 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.2463976086
Short name T763
Test name
Test status
Simulation time 15400769908 ps
CPU time 674.78 seconds
Started Mar 24 01:25:38 PM PDT 24
Finished Mar 24 01:36:53 PM PDT 24
Peak memory 231788 kb
Host smart-b51d0fe4-4b11-41af-a3ba-894fe87214d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463976086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2463976086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.4220453346
Short name T226
Test name
Test status
Simulation time 132603172 ps
CPU time 2.35 seconds
Started Mar 24 01:25:37 PM PDT 24
Finished Mar 24 01:25:40 PM PDT 24
Peak memory 216100 kb
Host smart-2cb1184a-d1b1-40b5-bfc8-c64c97d489e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4220453346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.4220453346 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.2363152650
Short name T1055
Test name
Test status
Simulation time 1424433569 ps
CPU time 27.55 seconds
Started Mar 24 01:25:38 PM PDT 24
Finished Mar 24 01:26:06 PM PDT 24
Peak memory 224260 kb
Host smart-7a3591e5-1b10-4b28-b6df-4fb3e4f2c5dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2363152650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2363152650 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.3691031408
Short name T429
Test name
Test status
Simulation time 6860275600 ps
CPU time 46.12 seconds
Started Mar 24 01:25:38 PM PDT 24
Finished Mar 24 01:26:25 PM PDT 24
Peak memory 217788 kb
Host smart-65bc99b7-9338-40d8-b0cf-25780f2c6a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691031408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3691031408 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.4234412612
Short name T844
Test name
Test status
Simulation time 721621930 ps
CPU time 30.93 seconds
Started Mar 24 01:25:37 PM PDT 24
Finished Mar 24 01:26:08 PM PDT 24
Peak memory 221956 kb
Host smart-7b393876-349d-4ecb-bde9-1486a1c0e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234412612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.4234412612 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.288338727
Short name T34
Test name
Test status
Simulation time 1374204830 ps
CPU time 97.43 seconds
Started Mar 24 01:25:41 PM PDT 24
Finished Mar 24 01:27:18 PM PDT 24
Peak memory 239328 kb
Host smart-04d9ba75-20e8-4729-9402-78b23c84d19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288338727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.288338727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.2299633960
Short name T68
Test name
Test status
Simulation time 97553491 ps
CPU time 1.32 seconds
Started Mar 24 01:25:37 PM PDT 24
Finished Mar 24 01:25:39 PM PDT 24
Peak memory 207568 kb
Host smart-4689511f-57da-441a-9664-5b6f38d7e6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299633960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2299633960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.4267286823
Short name T9
Test name
Test status
Simulation time 54005530 ps
CPU time 1.39 seconds
Started Mar 24 01:25:37 PM PDT 24
Finished Mar 24 01:25:39 PM PDT 24
Peak memory 216104 kb
Host smart-3b84f884-467d-4456-9aab-b00792907ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267286823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.4267286823 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.1443226943
Short name T235
Test name
Test status
Simulation time 5455616800 ps
CPU time 114.08 seconds
Started Mar 24 01:25:32 PM PDT 24
Finished Mar 24 01:27:26 PM PDT 24
Peak memory 235844 kb
Host smart-f2a82288-cfa0-4ad3-93ea-5002b7e17beb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443226943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.1443226943 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.1536966707
Short name T607
Test name
Test status
Simulation time 53784104523 ps
CPU time 199.7 seconds
Started Mar 24 01:25:37 PM PDT 24
Finished Mar 24 01:28:57 PM PDT 24
Peak memory 239744 kb
Host smart-5aef7cbe-689e-4891-b46f-2c1ef0dedfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536966707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1536966707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.689624864
Short name T69
Test name
Test status
Simulation time 22331040296 ps
CPU time 33.34 seconds
Started Mar 24 01:25:46 PM PDT 24
Finished Mar 24 01:26:19 PM PDT 24
Peak memory 243896 kb
Host smart-17f47d04-7a78-4091-9070-fecf28cb6846
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689624864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.689624864 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.3904364204
Short name T279
Test name
Test status
Simulation time 54075673440 ps
CPU time 377.83 seconds
Started Mar 24 01:25:34 PM PDT 24
Finished Mar 24 01:31:52 PM PDT 24
Peak memory 248580 kb
Host smart-f9fb9af8-b28b-47c6-aef3-b2ff8722bca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904364204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3904364204 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.266626168
Short name T669
Test name
Test status
Simulation time 887896422 ps
CPU time 5.51 seconds
Started Mar 24 01:25:33 PM PDT 24
Finished Mar 24 01:25:38 PM PDT 24
Peak memory 220016 kb
Host smart-66865cfa-0b6a-4b1b-aa36-99fbf70d148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266626168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.266626168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.3542795973
Short name T27
Test name
Test status
Simulation time 11024451885 ps
CPU time 823 seconds
Started Mar 24 01:25:41 PM PDT 24
Finished Mar 24 01:39:24 PM PDT 24
Peak memory 342184 kb
Host smart-ff297821-bdfb-499c-b698-edfd52c30b7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3542795973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3542795973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.2202568962
Short name T414
Test name
Test status
Simulation time 629694239 ps
CPU time 4.81 seconds
Started Mar 24 01:25:37 PM PDT 24
Finished Mar 24 01:25:42 PM PDT 24
Peak memory 216284 kb
Host smart-2152d43b-027a-4dfc-95f1-67d03d2c788b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202568962 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.2202568962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.2987143040
Short name T1053
Test name
Test status
Simulation time 214608718 ps
CPU time 4.77 seconds
Started Mar 24 01:25:41 PM PDT 24
Finished Mar 24 01:25:46 PM PDT 24
Peak memory 216304 kb
Host smart-b75b963e-d16a-45a6-8224-73d373cc75f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987143040 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2987143040 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.1988657044
Short name T935
Test name
Test status
Simulation time 279339951644 ps
CPU time 1930.81 seconds
Started Mar 24 01:25:36 PM PDT 24
Finished Mar 24 01:57:47 PM PDT 24
Peak memory 395020 kb
Host smart-abb4e195-b61c-4992-aa84-0fe0a84bb8af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1988657044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1988657044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.737595038
Short name T214
Test name
Test status
Simulation time 17786885983 ps
CPU time 1544.35 seconds
Started Mar 24 01:25:38 PM PDT 24
Finished Mar 24 01:51:22 PM PDT 24
Peak memory 375512 kb
Host smart-7f02d667-3572-4d3b-b853-43c33c751557
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=737595038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.737595038 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2866644463
Short name T260
Test name
Test status
Simulation time 27549339657 ps
CPU time 1086.26 seconds
Started Mar 24 01:25:41 PM PDT 24
Finished Mar 24 01:43:47 PM PDT 24
Peak memory 332768 kb
Host smart-5c873487-b1d5-422f-ba82-401bd3035cdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2866644463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2866644463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.581179258
Short name T1005
Test name
Test status
Simulation time 221646256587 ps
CPU time 975.73 seconds
Started Mar 24 01:25:40 PM PDT 24
Finished Mar 24 01:41:56 PM PDT 24
Peak memory 295124 kb
Host smart-66563fb1-49a2-46dd-b16e-bf7b705e5a6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=581179258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.581179258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.4064953206
Short name T950
Test name
Test status
Simulation time 52668688100 ps
CPU time 4254.94 seconds
Started Mar 24 01:25:39 PM PDT 24
Finished Mar 24 02:36:35 PM PDT 24
Peak memory 654760 kb
Host smart-ee8f8b77-b482-43f3-a815-33ce603edb21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4064953206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.4064953206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.120999683
Short name T930
Test name
Test status
Simulation time 1039212345773 ps
CPU time 4370.21 seconds
Started Mar 24 01:25:36 PM PDT 24
Finished Mar 24 02:38:28 PM PDT 24
Peak memory 561940 kb
Host smart-75ca3756-280c-4aa6-9e24-3652460d23bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=120999683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.120999683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.3547465426
Short name T791
Test name
Test status
Simulation time 14784648 ps
CPU time 0.82 seconds
Started Mar 24 01:32:16 PM PDT 24
Finished Mar 24 01:32:17 PM PDT 24
Peak memory 205732 kb
Host smart-10b78033-6ae2-4a30-8f95-ef8283c6c9fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547465426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3547465426 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.2606446966
Short name T98
Test name
Test status
Simulation time 15505052180 ps
CPU time 177.29 seconds
Started Mar 24 01:32:07 PM PDT 24
Finished Mar 24 01:35:05 PM PDT 24
Peak memory 240148 kb
Host smart-dd912f40-ea95-48f0-bbdc-c2bbe5325cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606446966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2606446966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.1904455491
Short name T818
Test name
Test status
Simulation time 78404658244 ps
CPU time 578.69 seconds
Started Mar 24 01:31:51 PM PDT 24
Finished Mar 24 01:41:30 PM PDT 24
Peak memory 231504 kb
Host smart-b09911d0-48c0-4c9f-a5a6-e2ce52ed811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904455491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.1904455491 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.328392427
Short name T31
Test name
Test status
Simulation time 5896887472 ps
CPU time 119.07 seconds
Started Mar 24 01:32:06 PM PDT 24
Finished Mar 24 01:34:06 PM PDT 24
Peak memory 233244 kb
Host smart-6e18988d-bd7d-43ba-b047-476d7e2be272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328392427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.328392427 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.329419981
Short name T917
Test name
Test status
Simulation time 2107162424 ps
CPU time 47 seconds
Started Mar 24 01:32:06 PM PDT 24
Finished Mar 24 01:32:54 PM PDT 24
Peak memory 239040 kb
Host smart-77f02536-ddd5-4cd5-ab5e-80bd30fd5f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329419981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.329419981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.1756598504
Short name T26
Test name
Test status
Simulation time 1336471839 ps
CPU time 6.78 seconds
Started Mar 24 01:32:06 PM PDT 24
Finished Mar 24 01:32:13 PM PDT 24
Peak memory 207828 kb
Host smart-78be1590-12fd-4120-a212-bea5120d1358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756598504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1756598504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.142832621
Short name T58
Test name
Test status
Simulation time 2760258579 ps
CPU time 14.91 seconds
Started Mar 24 01:32:06 PM PDT 24
Finished Mar 24 01:32:21 PM PDT 24
Peak memory 224688 kb
Host smart-031fb3d9-13cf-47c9-865d-585b6d4bf827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142832621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.142832621 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.3809690913
Short name T1058
Test name
Test status
Simulation time 79671832452 ps
CPU time 2417.9 seconds
Started Mar 24 01:31:52 PM PDT 24
Finished Mar 24 02:12:11 PM PDT 24
Peak memory 449504 kb
Host smart-0fc9c57e-0753-4797-acba-91e9aa707b56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809690913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.3809690913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.3713764274
Short name T684
Test name
Test status
Simulation time 15353885545 ps
CPU time 218.77 seconds
Started Mar 24 01:31:53 PM PDT 24
Finished Mar 24 01:35:32 PM PDT 24
Peak memory 239088 kb
Host smart-20664adb-c237-46cd-9355-d5e495c31189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713764274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3713764274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.957952389
Short name T478
Test name
Test status
Simulation time 9528926534 ps
CPU time 25.82 seconds
Started Mar 24 01:31:53 PM PDT 24
Finished Mar 24 01:32:19 PM PDT 24
Peak memory 222524 kb
Host smart-f08f34b2-5e7f-4be9-9194-d53b7e37fab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957952389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.957952389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.4284888156
Short name T413
Test name
Test status
Simulation time 84162599836 ps
CPU time 1314.65 seconds
Started Mar 24 01:32:06 PM PDT 24
Finished Mar 24 01:54:01 PM PDT 24
Peak memory 425548 kb
Host smart-97d120b7-5697-45d1-ba41-778807b4ed32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4284888156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.4284888156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.1321686872
Short name T716
Test name
Test status
Simulation time 266517706 ps
CPU time 5.12 seconds
Started Mar 24 01:32:02 PM PDT 24
Finished Mar 24 01:32:07 PM PDT 24
Peak memory 216224 kb
Host smart-f9994db4-6405-47dc-94f3-ca35618f8d86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321686872 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.1321686872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1495722153
Short name T225
Test name
Test status
Simulation time 310264821 ps
CPU time 4.27 seconds
Started Mar 24 01:32:02 PM PDT 24
Finished Mar 24 01:32:07 PM PDT 24
Peak memory 216188 kb
Host smart-94a91353-6aee-4479-b99b-f1c45ac0392b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495722153 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1495722153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.871025361
Short name T1079
Test name
Test status
Simulation time 68273837660 ps
CPU time 1939.12 seconds
Started Mar 24 01:31:52 PM PDT 24
Finished Mar 24 02:04:11 PM PDT 24
Peak memory 392696 kb
Host smart-a81f1f55-5d44-4733-a17a-899e5e452b1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=871025361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.871025361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.2357248690
Short name T847
Test name
Test status
Simulation time 289027234631 ps
CPU time 1724.58 seconds
Started Mar 24 01:31:51 PM PDT 24
Finished Mar 24 02:00:36 PM PDT 24
Peak memory 372320 kb
Host smart-1b294f4b-a527-421b-bf82-ff540b13ba1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2357248690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2357248690 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.915440642
Short name T1051
Test name
Test status
Simulation time 26963137708 ps
CPU time 1135.52 seconds
Started Mar 24 01:31:56 PM PDT 24
Finished Mar 24 01:50:52 PM PDT 24
Peak memory 332320 kb
Host smart-8b5fdf10-58c5-40b8-a144-a4273054b990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=915440642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.915440642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.1622158167
Short name T507
Test name
Test status
Simulation time 21645935892 ps
CPU time 823.97 seconds
Started Mar 24 01:31:56 PM PDT 24
Finished Mar 24 01:45:40 PM PDT 24
Peak memory 295936 kb
Host smart-acb63e9f-71f3-4228-90e7-1702bbc2728a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1622158167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1622158167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.3028179402
Short name T374
Test name
Test status
Simulation time 52685941436 ps
CPU time 4018.47 seconds
Started Mar 24 01:31:56 PM PDT 24
Finished Mar 24 02:38:55 PM PDT 24
Peak memory 644880 kb
Host smart-a764d08c-51db-40e7-9dfc-2bb97c03cf46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3028179402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.3028179402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.85675305
Short name T993
Test name
Test status
Simulation time 424604747465 ps
CPU time 4269.39 seconds
Started Mar 24 01:32:01 PM PDT 24
Finished Mar 24 02:43:11 PM PDT 24
Peak memory 544596 kb
Host smart-ed1bbe72-5ea3-47a5-89fe-4b86b87f1010
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=85675305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.85675305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.2395901531
Short name T951
Test name
Test status
Simulation time 29798927 ps
CPU time 0.79 seconds
Started Mar 24 01:32:23 PM PDT 24
Finished Mar 24 01:32:24 PM PDT 24
Peak memory 205732 kb
Host smart-57d3d623-01c3-464c-bd9b-b61d2b413a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395901531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2395901531 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.3782393986
Short name T427
Test name
Test status
Simulation time 84574710686 ps
CPU time 285.65 seconds
Started Mar 24 01:32:17 PM PDT 24
Finished Mar 24 01:37:03 PM PDT 24
Peak memory 246132 kb
Host smart-40cde1a3-0fd7-4ea4-9b3b-9a9e984bc40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782393986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3782393986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.2173223449
Short name T74
Test name
Test status
Simulation time 67950373957 ps
CPU time 162.56 seconds
Started Mar 24 01:32:16 PM PDT 24
Finished Mar 24 01:34:58 PM PDT 24
Peak memory 230896 kb
Host smart-f0a376c3-4496-4417-9f48-6ecda36cbbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173223449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.2173223449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.2300963215
Short name T1075
Test name
Test status
Simulation time 130085301064 ps
CPU time 247.23 seconds
Started Mar 24 01:32:17 PM PDT 24
Finished Mar 24 01:36:25 PM PDT 24
Peak memory 244696 kb
Host smart-65297cee-3fea-4de7-ad2c-d905ceefb3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300963215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2300963215 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.1504157214
Short name T265
Test name
Test status
Simulation time 3715001721 ps
CPU time 39.93 seconds
Started Mar 24 01:32:22 PM PDT 24
Finished Mar 24 01:33:02 PM PDT 24
Peak memory 232768 kb
Host smart-05e0c992-600e-4581-a4f8-88d2e3573729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504157214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1504157214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.3157906169
Short name T19
Test name
Test status
Simulation time 335298749 ps
CPU time 2.2 seconds
Started Mar 24 01:32:23 PM PDT 24
Finished Mar 24 01:32:25 PM PDT 24
Peak memory 207564 kb
Host smart-a86dab7c-5d2c-457b-9328-95568a67d6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157906169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3157906169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.1878915233
Short name T491
Test name
Test status
Simulation time 30139305999 ps
CPU time 650.82 seconds
Started Mar 24 01:32:14 PM PDT 24
Finished Mar 24 01:43:05 PM PDT 24
Peak memory 292720 kb
Host smart-c31553d3-8d79-4a64-b8bc-be1d841e1660
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878915233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.1878915233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.1245374222
Short name T462
Test name
Test status
Simulation time 25430795880 ps
CPU time 297.05 seconds
Started Mar 24 01:32:14 PM PDT 24
Finished Mar 24 01:37:11 PM PDT 24
Peak memory 245816 kb
Host smart-de6461fd-f52f-4852-8a6d-7330dbaeb468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245374222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1245374222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.4245967077
Short name T557
Test name
Test status
Simulation time 1720608118 ps
CPU time 43.74 seconds
Started Mar 24 01:32:12 PM PDT 24
Finished Mar 24 01:32:56 PM PDT 24
Peak memory 217596 kb
Host smart-9d5493d1-2be3-4fbf-b941-722b0aeabaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245967077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.4245967077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.2457270208
Short name T594
Test name
Test status
Simulation time 103960081445 ps
CPU time 1053.56 seconds
Started Mar 24 01:32:23 PM PDT 24
Finished Mar 24 01:49:56 PM PDT 24
Peak memory 355820 kb
Host smart-c7e77b0c-189c-4bbc-87fa-18e8033a8aa2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2457270208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2457270208 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.2301740853
Short name T482
Test name
Test status
Simulation time 790469200 ps
CPU time 5.12 seconds
Started Mar 24 01:32:18 PM PDT 24
Finished Mar 24 01:32:23 PM PDT 24
Peak memory 209812 kb
Host smart-d12dc7c4-7781-4511-8737-ab14119c286b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301740853 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.2301740853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.11660728
Short name T228
Test name
Test status
Simulation time 122690568 ps
CPU time 4.05 seconds
Started Mar 24 01:32:18 PM PDT 24
Finished Mar 24 01:32:22 PM PDT 24
Peak memory 216220 kb
Host smart-d41ced3e-e76b-42bb-b1bb-3d7e2a6101ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11660728 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.kmac_test_vectors_kmac_xof.11660728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.2904899732
Short name T353
Test name
Test status
Simulation time 39544468533 ps
CPU time 1627.02 seconds
Started Mar 24 01:32:12 PM PDT 24
Finished Mar 24 01:59:19 PM PDT 24
Peak memory 403544 kb
Host smart-2fc48d08-0b2a-4313-bdc1-f9f1445fb572
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2904899732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2904899732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.319901920
Short name T1076
Test name
Test status
Simulation time 61547761193 ps
CPU time 1745.38 seconds
Started Mar 24 01:32:17 PM PDT 24
Finished Mar 24 02:01:22 PM PDT 24
Peak memory 376812 kb
Host smart-d1bc1231-c65a-4aac-9669-15a2a6e8a936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=319901920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.319901920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.3611311972
Short name T262
Test name
Test status
Simulation time 38585346411 ps
CPU time 1154.89 seconds
Started Mar 24 01:32:17 PM PDT 24
Finished Mar 24 01:51:32 PM PDT 24
Peak memory 341068 kb
Host smart-f38c57c1-02ef-48c2-a87b-8128e4bdd3c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3611311972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.3611311972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.1242586643
Short name T366
Test name
Test status
Simulation time 118354556112 ps
CPU time 879.22 seconds
Started Mar 24 01:32:17 PM PDT 24
Finished Mar 24 01:46:56 PM PDT 24
Peak memory 294992 kb
Host smart-9d7c60c2-b3a2-4c70-a450-2a28fa757d2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1242586643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.1242586643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.3854384974
Short name T929
Test name
Test status
Simulation time 828435016742 ps
CPU time 4766.98 seconds
Started Mar 24 01:32:17 PM PDT 24
Finished Mar 24 02:51:45 PM PDT 24
Peak memory 655332 kb
Host smart-ed6f1959-0952-4b32-bd28-1e999aa4e44a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3854384974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.3854384974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.131792986
Short name T799
Test name
Test status
Simulation time 44173990142 ps
CPU time 3408.49 seconds
Started Mar 24 01:32:17 PM PDT 24
Finished Mar 24 02:29:06 PM PDT 24
Peak memory 562952 kb
Host smart-4e201dca-dec9-4236-9806-66f2c0e0a05a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=131792986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.131792986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.3724582132
Short name T503
Test name
Test status
Simulation time 21363033 ps
CPU time 0.82 seconds
Started Mar 24 01:32:37 PM PDT 24
Finished Mar 24 01:32:38 PM PDT 24
Peak memory 205688 kb
Host smart-8020bd49-3bdd-4469-855f-f7a1695be6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724582132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3724582132 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.80585922
Short name T1060
Test name
Test status
Simulation time 1893701500 ps
CPU time 37.94 seconds
Started Mar 24 01:32:32 PM PDT 24
Finished Mar 24 01:33:10 PM PDT 24
Peak memory 221484 kb
Host smart-982d8a6b-eda8-45a0-9cf2-da6bbc11a5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80585922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.80585922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.1559916385
Short name T960
Test name
Test status
Simulation time 8796227034 ps
CPU time 668.79 seconds
Started Mar 24 01:32:26 PM PDT 24
Finished Mar 24 01:43:35 PM PDT 24
Peak memory 232776 kb
Host smart-0ed7ddfd-71c5-4deb-ab3c-28ff151753f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559916385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.1559916385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.1942161119
Short name T745
Test name
Test status
Simulation time 7600404639 ps
CPU time 224.38 seconds
Started Mar 24 01:32:38 PM PDT 24
Finished Mar 24 01:36:22 PM PDT 24
Peak memory 241996 kb
Host smart-6ca42d24-118a-480a-a57d-654efa22849d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942161119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1942161119 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.4196190744
Short name T798
Test name
Test status
Simulation time 10598158477 ps
CPU time 198.28 seconds
Started Mar 24 01:32:37 PM PDT 24
Finished Mar 24 01:35:56 PM PDT 24
Peak memory 249080 kb
Host smart-0afd1d7f-39ae-42f0-9516-2501de2539c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196190744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.4196190744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.3861477054
Short name T67
Test name
Test status
Simulation time 989993274 ps
CPU time 5.69 seconds
Started Mar 24 01:32:40 PM PDT 24
Finished Mar 24 01:32:46 PM PDT 24
Peak memory 207696 kb
Host smart-1e65a34c-8364-4dae-a19f-aacacfbde8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861477054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3861477054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.1950382920
Short name T62
Test name
Test status
Simulation time 31988690 ps
CPU time 1.2 seconds
Started Mar 24 01:32:37 PM PDT 24
Finished Mar 24 01:32:39 PM PDT 24
Peak memory 216164 kb
Host smart-f30e8758-bdc5-442e-a033-cbc845f48d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950382920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1950382920 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.167445779
Short name T767
Test name
Test status
Simulation time 220889510332 ps
CPU time 672.35 seconds
Started Mar 24 01:32:28 PM PDT 24
Finished Mar 24 01:43:40 PM PDT 24
Peak memory 283288 kb
Host smart-b145d086-6a84-424e-be36-ad7a1482723a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167445779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_an
d_output.167445779 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.2731323376
Short name T303
Test name
Test status
Simulation time 15503715081 ps
CPU time 223.58 seconds
Started Mar 24 01:32:27 PM PDT 24
Finished Mar 24 01:36:11 PM PDT 24
Peak memory 236936 kb
Host smart-575795e2-158d-471c-b3d4-bba5639faed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731323376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2731323376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.1149719845
Short name T453
Test name
Test status
Simulation time 4403081645 ps
CPU time 45.84 seconds
Started Mar 24 01:32:24 PM PDT 24
Finished Mar 24 01:33:10 PM PDT 24
Peak memory 217456 kb
Host smart-29fbdbd3-7519-49ba-aadb-19ae3a3c91a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149719845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1149719845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.1704511984
Short name T781
Test name
Test status
Simulation time 12474219638 ps
CPU time 1017.34 seconds
Started Mar 24 01:32:40 PM PDT 24
Finished Mar 24 01:49:38 PM PDT 24
Peak memory 337496 kb
Host smart-2b925d51-baf2-4c61-ba68-d18a6a3d49c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1704511984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1704511984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.473410832
Short name T736
Test name
Test status
Simulation time 648571069 ps
CPU time 4.32 seconds
Started Mar 24 01:32:27 PM PDT 24
Finished Mar 24 01:32:31 PM PDT 24
Peak memory 216264 kb
Host smart-045741f8-5d25-40f9-9991-a19f8ca06f0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473410832 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_test_vectors_kmac.473410832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.239542872
Short name T967
Test name
Test status
Simulation time 244406153 ps
CPU time 4.97 seconds
Started Mar 24 01:32:31 PM PDT 24
Finished Mar 24 01:32:36 PM PDT 24
Peak memory 216208 kb
Host smart-5b4c5d3c-aa24-4fac-8313-b5f286bad63c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239542872 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.kmac_test_vectors_kmac_xof.239542872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.1357026765
Short name T674
Test name
Test status
Simulation time 101634132072 ps
CPU time 2147.19 seconds
Started Mar 24 01:32:29 PM PDT 24
Finished Mar 24 02:08:16 PM PDT 24
Peak memory 394172 kb
Host smart-ce36adf9-d37f-483b-b093-4bec81b4cf8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1357026765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.1357026765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.355344757
Short name T472
Test name
Test status
Simulation time 35225548586 ps
CPU time 1440.14 seconds
Started Mar 24 01:32:27 PM PDT 24
Finished Mar 24 01:56:27 PM PDT 24
Peak memory 372188 kb
Host smart-58639982-639f-4aa7-8f06-a4c9548a7dbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=355344757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.355344757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.3484768765
Short name T883
Test name
Test status
Simulation time 26875569232 ps
CPU time 1048.76 seconds
Started Mar 24 01:32:28 PM PDT 24
Finished Mar 24 01:49:57 PM PDT 24
Peak memory 331524 kb
Host smart-17564de9-5cda-4e85-bbeb-92f8cbf7d487
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3484768765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3484768765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.1198560652
Short name T1056
Test name
Test status
Simulation time 19242142211 ps
CPU time 775.69 seconds
Started Mar 24 01:32:30 PM PDT 24
Finished Mar 24 01:45:26 PM PDT 24
Peak memory 293872 kb
Host smart-e4f9167e-d537-418c-aedc-d0111aeb1e59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1198560652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.1198560652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.59511995
Short name T187
Test name
Test status
Simulation time 2160243095513 ps
CPU time 4821.23 seconds
Started Mar 24 01:32:28 PM PDT 24
Finished Mar 24 02:52:50 PM PDT 24
Peak memory 656028 kb
Host smart-4e08fee6-1e07-466f-95f1-f71080a744a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=59511995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.59511995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.229545923
Short name T625
Test name
Test status
Simulation time 390866729392 ps
CPU time 4009.45 seconds
Started Mar 24 01:32:27 PM PDT 24
Finished Mar 24 02:39:17 PM PDT 24
Peak memory 560460 kb
Host smart-67dcba0d-a24d-4019-9831-77c9464a2c34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=229545923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.229545923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.928577533
Short name T504
Test name
Test status
Simulation time 38997040 ps
CPU time 0.73 seconds
Started Mar 24 01:32:56 PM PDT 24
Finished Mar 24 01:32:57 PM PDT 24
Peak memory 205776 kb
Host smart-c8fa90f4-5103-44b4-95bd-a91aae070cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928577533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.928577533 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.2431974167
Short name T888
Test name
Test status
Simulation time 38436565964 ps
CPU time 219.88 seconds
Started Mar 24 01:32:52 PM PDT 24
Finished Mar 24 01:36:32 PM PDT 24
Peak memory 240556 kb
Host smart-61cc4025-db8b-4727-a842-58cf77e7fc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431974167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2431974167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.117870820
Short name T921
Test name
Test status
Simulation time 2027283158 ps
CPU time 30.94 seconds
Started Mar 24 01:32:42 PM PDT 24
Finished Mar 24 01:33:13 PM PDT 24
Peak memory 219376 kb
Host smart-4aa7d085-02c2-40b0-87e7-4bf8244e4c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117870820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.117870820 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.3042893742
Short name T638
Test name
Test status
Simulation time 76183423960 ps
CPU time 352.93 seconds
Started Mar 24 01:32:54 PM PDT 24
Finished Mar 24 01:38:49 PM PDT 24
Peak memory 246400 kb
Host smart-db131824-0c5f-4751-8885-0e7e251e6c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042893742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3042893742 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.2942711108
Short name T193
Test name
Test status
Simulation time 26381734267 ps
CPU time 177.96 seconds
Started Mar 24 01:32:52 PM PDT 24
Finished Mar 24 01:35:50 PM PDT 24
Peak memory 249080 kb
Host smart-a2dc7ef4-70ff-47ae-8b81-fa85c51c9a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942711108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2942711108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.1292384822
Short name T518
Test name
Test status
Simulation time 390420382 ps
CPU time 2.41 seconds
Started Mar 24 01:32:54 PM PDT 24
Finished Mar 24 01:32:58 PM PDT 24
Peak memory 207284 kb
Host smart-9f45a239-2444-4577-a03c-53ef1e5249da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292384822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1292384822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.3312601751
Short name T584
Test name
Test status
Simulation time 25396778 ps
CPU time 1.29 seconds
Started Mar 24 01:32:54 PM PDT 24
Finished Mar 24 01:32:57 PM PDT 24
Peak memory 221072 kb
Host smart-d11b400d-0932-4c96-a1d3-4a6dd7b35428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312601751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3312601751 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.2552707028
Short name T663
Test name
Test status
Simulation time 102275550012 ps
CPU time 2228.39 seconds
Started Mar 24 01:32:45 PM PDT 24
Finished Mar 24 02:09:54 PM PDT 24
Peak memory 417332 kb
Host smart-d34c9e37-378d-4660-9a6b-0b8b9aa2a059
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552707028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.2552707028 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.2413487909
Short name T701
Test name
Test status
Simulation time 18266294831 ps
CPU time 385.63 seconds
Started Mar 24 01:32:43 PM PDT 24
Finished Mar 24 01:39:08 PM PDT 24
Peak memory 246408 kb
Host smart-3e1082fe-eff4-4736-85a4-6a4b2bea8ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413487909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2413487909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.1330991414
Short name T149
Test name
Test status
Simulation time 2031817185 ps
CPU time 33.03 seconds
Started Mar 24 01:32:45 PM PDT 24
Finished Mar 24 01:33:18 PM PDT 24
Peak memory 218984 kb
Host smart-6c9f24f9-7375-4b8a-9ce6-fcae0433c217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330991414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1330991414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.1644609783
Short name T290
Test name
Test status
Simulation time 1399099896006 ps
CPU time 1564.27 seconds
Started Mar 24 01:32:57 PM PDT 24
Finished Mar 24 01:59:02 PM PDT 24
Peak memory 417912 kb
Host smart-a828d745-7929-4444-986d-41bc079d4bc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1644609783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.1644609783 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.4052011081
Short name T1046
Test name
Test status
Simulation time 170252405 ps
CPU time 4.87 seconds
Started Mar 24 01:32:47 PM PDT 24
Finished Mar 24 01:32:52 PM PDT 24
Peak memory 216136 kb
Host smart-e8a319b6-097c-44b0-bdc5-2ac06592ebef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052011081 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.4052011081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.3717987662
Short name T578
Test name
Test status
Simulation time 955946965 ps
CPU time 4.84 seconds
Started Mar 24 01:32:52 PM PDT 24
Finished Mar 24 01:32:57 PM PDT 24
Peak memory 216216 kb
Host smart-f731102c-3ceb-4e37-a1dd-1f70045ca116
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717987662 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.3717987662 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.3032889176
Short name T987
Test name
Test status
Simulation time 145699668591 ps
CPU time 1633.72 seconds
Started Mar 24 01:32:49 PM PDT 24
Finished Mar 24 02:00:03 PM PDT 24
Peak memory 394944 kb
Host smart-662c2d86-2992-4551-a8b3-1961162ce88a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3032889176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3032889176 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.3992178932
Short name T984
Test name
Test status
Simulation time 18443499707 ps
CPU time 1370.74 seconds
Started Mar 24 01:32:47 PM PDT 24
Finished Mar 24 01:55:38 PM PDT 24
Peak memory 370364 kb
Host smart-b8f4597f-87e2-4194-9f26-7402634bb451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3992178932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3992178932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.2613817951
Short name T409
Test name
Test status
Simulation time 55961807884 ps
CPU time 1111.14 seconds
Started Mar 24 01:32:47 PM PDT 24
Finished Mar 24 01:51:19 PM PDT 24
Peak memory 331564 kb
Host smart-5938c086-c1a5-47c3-9744-b4c999135cd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2613817951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2613817951 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.2087770839
Short name T560
Test name
Test status
Simulation time 285559540008 ps
CPU time 1011.57 seconds
Started Mar 24 01:32:48 PM PDT 24
Finished Mar 24 01:49:40 PM PDT 24
Peak memory 293944 kb
Host smart-a07eabfe-066a-4511-8a4e-65393b48af0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2087770839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.2087770839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.2575676173
Short name T723
Test name
Test status
Simulation time 74359179201 ps
CPU time 4309.24 seconds
Started Mar 24 01:32:47 PM PDT 24
Finished Mar 24 02:44:37 PM PDT 24
Peak memory 644852 kb
Host smart-9b1149be-2172-4252-9c7e-bd2e035ce093
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2575676173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.2575676173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.2646838344
Short name T707
Test name
Test status
Simulation time 160631522471 ps
CPU time 3561.84 seconds
Started Mar 24 01:32:49 PM PDT 24
Finished Mar 24 02:32:12 PM PDT 24
Peak memory 563656 kb
Host smart-4a82e2ee-2073-46ea-bd48-f2d6765fa761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2646838344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.2646838344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.3925908950
Short name T1063
Test name
Test status
Simulation time 54257324 ps
CPU time 0.8 seconds
Started Mar 24 01:33:14 PM PDT 24
Finished Mar 24 01:33:16 PM PDT 24
Peak memory 205672 kb
Host smart-fd8fcaab-45c1-42a0-8eae-568b7cfa4270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925908950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3925908950 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.2498467640
Short name T722
Test name
Test status
Simulation time 3609734923 ps
CPU time 200.03 seconds
Started Mar 24 01:33:12 PM PDT 24
Finished Mar 24 01:36:33 PM PDT 24
Peak memory 242884 kb
Host smart-98a1ee44-ff04-45ff-a81a-4a727f2e4d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498467640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.2498467640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.67766092
Short name T358
Test name
Test status
Simulation time 60253567159 ps
CPU time 454.07 seconds
Started Mar 24 01:33:01 PM PDT 24
Finished Mar 24 01:40:36 PM PDT 24
Peak memory 230756 kb
Host smart-461135a5-6784-4394-899d-802894590414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67766092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.67766092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.2466104896
Short name T628
Test name
Test status
Simulation time 16876475308 ps
CPU time 84.86 seconds
Started Mar 24 01:33:11 PM PDT 24
Finished Mar 24 01:34:36 PM PDT 24
Peak memory 227456 kb
Host smart-38297139-4195-4c06-bbc6-68401d9a0a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466104896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2466104896 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.2212395223
Short name T36
Test name
Test status
Simulation time 6994564620 ps
CPU time 184.31 seconds
Started Mar 24 01:33:11 PM PDT 24
Finished Mar 24 01:36:16 PM PDT 24
Peak memory 249128 kb
Host smart-a07c73e5-5eb8-4952-bdbd-8198730e5932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212395223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2212395223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.565758586
Short name T517
Test name
Test status
Simulation time 7147029211 ps
CPU time 7.21 seconds
Started Mar 24 01:33:12 PM PDT 24
Finished Mar 24 01:33:20 PM PDT 24
Peak memory 207952 kb
Host smart-65f53cce-e64c-4e0e-90b5-8fe61c5823aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565758586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.565758586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.541936504
Short name T892
Test name
Test status
Simulation time 38169387 ps
CPU time 1.21 seconds
Started Mar 24 01:33:10 PM PDT 24
Finished Mar 24 01:33:12 PM PDT 24
Peak memory 216128 kb
Host smart-fc0dc314-fbf1-4653-91c5-8788c9f9d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541936504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.541936504 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.895540714
Short name T540
Test name
Test status
Simulation time 38471108834 ps
CPU time 1598.16 seconds
Started Mar 24 01:32:59 PM PDT 24
Finished Mar 24 01:59:37 PM PDT 24
Peak memory 409896 kb
Host smart-48f37efd-2406-4cf6-8ced-8a90b0d0ed7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895540714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_an
d_output.895540714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.700482509
Short name T334
Test name
Test status
Simulation time 247789346 ps
CPU time 4.96 seconds
Started Mar 24 01:32:57 PM PDT 24
Finished Mar 24 01:33:02 PM PDT 24
Peak memory 224336 kb
Host smart-c7fe970c-8ff7-43bc-afac-a1229bee0191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700482509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.700482509 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.3398974205
Short name T840
Test name
Test status
Simulation time 572809340 ps
CPU time 3.78 seconds
Started Mar 24 01:32:58 PM PDT 24
Finished Mar 24 01:33:02 PM PDT 24
Peak memory 217280 kb
Host smart-f100dbe3-5727-436c-8f3a-12bc21a41f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398974205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3398974205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.2488038032
Short name T1035
Test name
Test status
Simulation time 4002914966 ps
CPU time 96.54 seconds
Started Mar 24 01:33:16 PM PDT 24
Finished Mar 24 01:34:57 PM PDT 24
Peak memory 240224 kb
Host smart-43787756-e882-4bbe-aca9-ff65f00b3230
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2488038032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.2488038032 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.3682921559
Short name T581
Test name
Test status
Simulation time 169423802 ps
CPU time 4.87 seconds
Started Mar 24 01:33:05 PM PDT 24
Finished Mar 24 01:33:11 PM PDT 24
Peak memory 216296 kb
Host smart-8b82490d-ef3c-4f7d-b482-e5885b4282d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682921559 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.3682921559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.3235830275
Short name T866
Test name
Test status
Simulation time 126703271 ps
CPU time 3.83 seconds
Started Mar 24 01:33:06 PM PDT 24
Finished Mar 24 01:33:10 PM PDT 24
Peak memory 216272 kb
Host smart-2aa258ce-170a-443b-9f2c-179eec06941a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235830275 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.3235830275 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.2739526542
Short name T3
Test name
Test status
Simulation time 66038661696 ps
CPU time 1758.2 seconds
Started Mar 24 01:33:02 PM PDT 24
Finished Mar 24 02:02:21 PM PDT 24
Peak memory 376792 kb
Host smart-33ae1fd6-6dbe-4d25-8c64-4829d45735d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2739526542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.2739526542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.381519902
Short name T301
Test name
Test status
Simulation time 669441158781 ps
CPU time 1571.56 seconds
Started Mar 24 01:33:00 PM PDT 24
Finished Mar 24 01:59:12 PM PDT 24
Peak memory 369564 kb
Host smart-c2c37afb-980a-4a87-9bd1-76cdd5a1d445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=381519902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.381519902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.3059086761
Short name T369
Test name
Test status
Simulation time 84786530691 ps
CPU time 1433.2 seconds
Started Mar 24 01:33:02 PM PDT 24
Finished Mar 24 01:56:56 PM PDT 24
Peak memory 343704 kb
Host smart-7606623c-bffc-4321-806d-b752be7b8381
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3059086761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.3059086761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.3365295347
Short name T251
Test name
Test status
Simulation time 43204755928 ps
CPU time 867.47 seconds
Started Mar 24 01:33:05 PM PDT 24
Finished Mar 24 01:47:34 PM PDT 24
Peak memory 291096 kb
Host smart-d737739a-6cd6-430a-9ba9-e5b310df3434
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3365295347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.3365295347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.1628574739
Short name T990
Test name
Test status
Simulation time 388094051550 ps
CPU time 4250.18 seconds
Started Mar 24 01:33:05 PM PDT 24
Finished Mar 24 02:43:57 PM PDT 24
Peak memory 643472 kb
Host smart-fdf0b5b2-2091-44fc-90a6-ed60554dd8e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1628574739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.1628574739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.2680961723
Short name T940
Test name
Test status
Simulation time 44676059755 ps
CPU time 3316.61 seconds
Started Mar 24 01:33:05 PM PDT 24
Finished Mar 24 02:28:24 PM PDT 24
Peak memory 572260 kb
Host smart-f672c0b9-74aa-4533-9163-e4959bfe2d13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2680961723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2680961723 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.163822159
Short name T1073
Test name
Test status
Simulation time 45455986 ps
CPU time 0.78 seconds
Started Mar 24 01:33:32 PM PDT 24
Finished Mar 24 01:33:33 PM PDT 24
Peak memory 205732 kb
Host smart-f7b983be-345f-483f-8575-4475d54858ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163822159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.163822159 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.2438515741
Short name T867
Test name
Test status
Simulation time 4523988556 ps
CPU time 96.65 seconds
Started Mar 24 01:33:29 PM PDT 24
Finished Mar 24 01:35:06 PM PDT 24
Peak memory 232156 kb
Host smart-ed44bb41-5681-424b-afbe-4d0f9b14ea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438515741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2438515741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.687410975
Short name T274
Test name
Test status
Simulation time 5659699811 ps
CPU time 43.24 seconds
Started Mar 24 01:33:20 PM PDT 24
Finished Mar 24 01:34:04 PM PDT 24
Peak memory 224584 kb
Host smart-a632d2ac-2bcb-4919-ab11-19be1411a91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687410975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.687410975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.2881183907
Short name T1062
Test name
Test status
Simulation time 9806316228 ps
CPU time 61.73 seconds
Started Mar 24 01:33:30 PM PDT 24
Finished Mar 24 01:34:31 PM PDT 24
Peak memory 224832 kb
Host smart-30818c44-b2ad-4f14-9d3f-56312c10e83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881183907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.2881183907 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.3424168849
Short name T348
Test name
Test status
Simulation time 15702423033 ps
CPU time 141.59 seconds
Started Mar 24 01:33:30 PM PDT 24
Finished Mar 24 01:35:54 PM PDT 24
Peak memory 240756 kb
Host smart-2e0c64aa-710d-4d29-9087-947bb2375a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424168849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3424168849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2193609965
Short name T812
Test name
Test status
Simulation time 1226816258 ps
CPU time 3.42 seconds
Started Mar 24 01:33:31 PM PDT 24
Finished Mar 24 01:33:36 PM PDT 24
Peak memory 207788 kb
Host smart-409118bb-2818-4038-98f7-39d43ae3772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193609965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2193609965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.4279190037
Short name T37
Test name
Test status
Simulation time 62262446 ps
CPU time 1.1 seconds
Started Mar 24 01:33:31 PM PDT 24
Finished Mar 24 01:33:34 PM PDT 24
Peak memory 216372 kb
Host smart-b5491eaa-c492-4bf1-bacf-b371f68a95b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279190037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.4279190037 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3281250318
Short name T905
Test name
Test status
Simulation time 82280538155 ps
CPU time 1851.73 seconds
Started Mar 24 01:33:15 PM PDT 24
Finished Mar 24 02:04:07 PM PDT 24
Peak memory 417824 kb
Host smart-f6a19504-cd2b-4b71-a3aa-32927757fc3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281250318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3281250318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.472430492
Short name T92
Test name
Test status
Simulation time 77015517797 ps
CPU time 349.87 seconds
Started Mar 24 01:33:22 PM PDT 24
Finished Mar 24 01:39:12 PM PDT 24
Peak memory 247064 kb
Host smart-670fb6de-2c3d-4c07-bab2-7e20fb77483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472430492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.472430492 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.3595041708
Short name T46
Test name
Test status
Simulation time 7215974544 ps
CPU time 39.77 seconds
Started Mar 24 01:33:16 PM PDT 24
Finished Mar 24 01:33:56 PM PDT 24
Peak memory 219992 kb
Host smart-6699544a-4030-463f-89df-812b198fbe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595041708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3595041708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.1101047034
Short name T673
Test name
Test status
Simulation time 8707249802 ps
CPU time 582.36 seconds
Started Mar 24 01:33:32 PM PDT 24
Finished Mar 24 01:43:15 PM PDT 24
Peak memory 299560 kb
Host smart-28987f90-7142-4f3f-9048-f4fd92551fe4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1101047034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1101047034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.491829046
Short name T610
Test name
Test status
Simulation time 68768967 ps
CPU time 4.1 seconds
Started Mar 24 01:33:26 PM PDT 24
Finished Mar 24 01:33:30 PM PDT 24
Peak memory 216240 kb
Host smart-e2a5a06b-ef24-48d0-9a85-7e1c768ca560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491829046 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.kmac_test_vectors_kmac.491829046 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3869717730
Short name T768
Test name
Test status
Simulation time 205373503 ps
CPU time 4.05 seconds
Started Mar 24 01:33:25 PM PDT 24
Finished Mar 24 01:33:29 PM PDT 24
Peak memory 209264 kb
Host smart-14d22387-4050-4cae-a364-0fb497d54998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869717730 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3869717730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.507770442
Short name T238
Test name
Test status
Simulation time 77596216339 ps
CPU time 1526.23 seconds
Started Mar 24 01:33:21 PM PDT 24
Finished Mar 24 01:58:47 PM PDT 24
Peak memory 388844 kb
Host smart-11bfb7cc-0add-4144-943c-6db03719b91f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=507770442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.507770442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.550424696
Short name T864
Test name
Test status
Simulation time 73069310051 ps
CPU time 1458.01 seconds
Started Mar 24 01:33:20 PM PDT 24
Finished Mar 24 01:57:39 PM PDT 24
Peak memory 370652 kb
Host smart-f13b20fd-b815-4021-b7f3-c4d3d0f04649
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=550424696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.550424696 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2487437351
Short name T551
Test name
Test status
Simulation time 113553080913 ps
CPU time 1110.58 seconds
Started Mar 24 01:33:26 PM PDT 24
Finished Mar 24 01:51:57 PM PDT 24
Peak memory 335316 kb
Host smart-8cf9f9a1-89d4-425f-8085-8bc8777f1e98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2487437351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2487437351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.3144227459
Short name T1048
Test name
Test status
Simulation time 38744980440 ps
CPU time 828.07 seconds
Started Mar 24 01:33:26 PM PDT 24
Finished Mar 24 01:47:14 PM PDT 24
Peak memory 291740 kb
Host smart-94936b0e-220e-47ad-843d-4f7e29470549
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3144227459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.3144227459 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.2702592428
Short name T93
Test name
Test status
Simulation time 178708747892 ps
CPU time 4804.97 seconds
Started Mar 24 01:33:26 PM PDT 24
Finished Mar 24 02:53:32 PM PDT 24
Peak memory 647900 kb
Host smart-6f67ec1e-6c5e-482f-807a-478afcfc41be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2702592428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.2702592428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.800856138
Short name T593
Test name
Test status
Simulation time 222001809432 ps
CPU time 4092.33 seconds
Started Mar 24 01:33:26 PM PDT 24
Finished Mar 24 02:41:39 PM PDT 24
Peak memory 554688 kb
Host smart-86bd86c5-98e9-46d7-9f9b-1f44c27138ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=800856138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.800856138 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.1622494656
Short name T379
Test name
Test status
Simulation time 35358012 ps
CPU time 0.74 seconds
Started Mar 24 01:33:47 PM PDT 24
Finished Mar 24 01:33:48 PM PDT 24
Peak memory 205692 kb
Host smart-daa41f2c-a145-428e-b200-bf80584d26bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622494656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1622494656 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.3135788571
Short name T1064
Test name
Test status
Simulation time 61231626917 ps
CPU time 283.39 seconds
Started Mar 24 01:33:44 PM PDT 24
Finished Mar 24 01:38:28 PM PDT 24
Peak memory 242660 kb
Host smart-6c55cd17-0c9e-4247-af8e-acf102e3054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135788571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3135788571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.65546098
Short name T441
Test name
Test status
Simulation time 90824778151 ps
CPU time 848.13 seconds
Started Mar 24 01:33:37 PM PDT 24
Finished Mar 24 01:47:45 PM PDT 24
Peak memory 233444 kb
Host smart-ea1e0447-2ac8-4d50-9ad9-6bc97085fd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65546098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.65546098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.4266692668
Short name T530
Test name
Test status
Simulation time 10740570891 ps
CPU time 218.31 seconds
Started Mar 24 01:33:47 PM PDT 24
Finished Mar 24 01:37:26 PM PDT 24
Peak memory 238460 kb
Host smart-002ac97c-8276-4ad7-9f31-ae2f664418df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266692668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.4266692668 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.4152442110
Short name T795
Test name
Test status
Simulation time 4919951982 ps
CPU time 268.81 seconds
Started Mar 24 01:33:49 PM PDT 24
Finished Mar 24 01:38:18 PM PDT 24
Peak memory 257192 kb
Host smart-1d78a7d5-ce4f-4f03-937e-b3268bd265d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152442110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.4152442110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.3032685688
Short name T569
Test name
Test status
Simulation time 2963985324 ps
CPU time 4.93 seconds
Started Mar 24 01:33:48 PM PDT 24
Finished Mar 24 01:33:53 PM PDT 24
Peak memory 207932 kb
Host smart-1ef60a4c-a517-4e21-8b97-1b4fa5bb1ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032685688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3032685688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.505978242
Short name T902
Test name
Test status
Simulation time 117946283 ps
CPU time 1.16 seconds
Started Mar 24 01:33:49 PM PDT 24
Finished Mar 24 01:33:50 PM PDT 24
Peak memory 216136 kb
Host smart-58252921-4e15-4e5f-8d6a-d4ac1a154a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505978242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.505978242 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1980844026
Short name T355
Test name
Test status
Simulation time 130728735684 ps
CPU time 1092.28 seconds
Started Mar 24 01:33:38 PM PDT 24
Finished Mar 24 01:51:50 PM PDT 24
Peak memory 325140 kb
Host smart-afe6313c-7865-4e24-9f2e-343671216c1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980844026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1980844026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.2530538049
Short name T650
Test name
Test status
Simulation time 46833936448 ps
CPU time 285.05 seconds
Started Mar 24 01:33:37 PM PDT 24
Finished Mar 24 01:38:22 PM PDT 24
Peak memory 241472 kb
Host smart-12b1cdf9-4556-4b77-a68e-c538b8a0fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530538049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2530538049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.2521560544
Short name T264
Test name
Test status
Simulation time 945601987 ps
CPU time 16 seconds
Started Mar 24 01:33:32 PM PDT 24
Finished Mar 24 01:33:49 PM PDT 24
Peak memory 219404 kb
Host smart-025875fd-ec0f-494d-8d12-37da5676dabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521560544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2521560544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.1008087989
Short name T466
Test name
Test status
Simulation time 44692066867 ps
CPU time 896.19 seconds
Started Mar 24 01:33:49 PM PDT 24
Finished Mar 24 01:48:45 PM PDT 24
Peak memory 347644 kb
Host smart-3e8e3ca3-d4a3-443a-b439-ff3e911f2ba2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1008087989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1008087989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.2951954375
Short name T999
Test name
Test status
Simulation time 2599917228 ps
CPU time 5.39 seconds
Started Mar 24 01:33:42 PM PDT 24
Finished Mar 24 01:33:47 PM PDT 24
Peak memory 216304 kb
Host smart-aaeda094-7cdc-4765-819e-61a053b05e0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951954375 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.2951954375 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1994115241
Short name T496
Test name
Test status
Simulation time 235861829 ps
CPU time 3.78 seconds
Started Mar 24 01:33:42 PM PDT 24
Finished Mar 24 01:33:46 PM PDT 24
Peak memory 216264 kb
Host smart-e1e329cf-7d52-4149-8e53-c10dc18b2d38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994115241 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1994115241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.405256668
Short name T706
Test name
Test status
Simulation time 18930278218 ps
CPU time 1575.06 seconds
Started Mar 24 01:33:37 PM PDT 24
Finished Mar 24 01:59:52 PM PDT 24
Peak memory 390796 kb
Host smart-58e06b6d-790e-47e8-86fd-3f2671cb999d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=405256668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.405256668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.4075954674
Short name T423
Test name
Test status
Simulation time 96498510964 ps
CPU time 1827.21 seconds
Started Mar 24 01:33:38 PM PDT 24
Finished Mar 24 02:04:05 PM PDT 24
Peak memory 379620 kb
Host smart-18b5654e-2155-4d6f-ad90-2eb81d526b86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4075954674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.4075954674 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.1881486151
Short name T525
Test name
Test status
Simulation time 14195381439 ps
CPU time 1149.48 seconds
Started Mar 24 01:33:40 PM PDT 24
Finished Mar 24 01:52:50 PM PDT 24
Peak memory 338652 kb
Host smart-d251a4ae-bd08-4d9d-96d6-6be5588390b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1881486151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.1881486151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2940472289
Short name T438
Test name
Test status
Simulation time 19422173611 ps
CPU time 776.63 seconds
Started Mar 24 01:33:38 PM PDT 24
Finished Mar 24 01:46:35 PM PDT 24
Peak memory 299632 kb
Host smart-80952270-e8fe-43cb-960f-1e430addd77c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2940472289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2940472289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.2301442334
Short name T364
Test name
Test status
Simulation time 689874433441 ps
CPU time 4912.07 seconds
Started Mar 24 01:33:37 PM PDT 24
Finished Mar 24 02:55:30 PM PDT 24
Peak memory 652940 kb
Host smart-eafde751-4e56-47cf-ab5c-0450fb8b6eb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2301442334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.2301442334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2570813322
Short name T742
Test name
Test status
Simulation time 187160086298 ps
CPU time 3492.59 seconds
Started Mar 24 01:33:42 PM PDT 24
Finished Mar 24 02:31:55 PM PDT 24
Peak memory 556492 kb
Host smart-1d165038-1a5a-45a7-bef8-517f756d22e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2570813322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2570813322 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.879643721
Short name T1059
Test name
Test status
Simulation time 60602150 ps
CPU time 0.78 seconds
Started Mar 24 01:33:59 PM PDT 24
Finished Mar 24 01:33:59 PM PDT 24
Peak memory 205720 kb
Host smart-fdfb11de-2c45-4a04-8f79-cc8c6d6c5dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879643721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.879643721 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.185420981
Short name T992
Test name
Test status
Simulation time 4420892044 ps
CPU time 104.31 seconds
Started Mar 24 01:33:52 PM PDT 24
Finished Mar 24 01:35:37 PM PDT 24
Peak memory 230796 kb
Host smart-a3aa9ce1-846b-41b2-a988-1632adcd93ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185420981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.185420981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.3582146548
Short name T773
Test name
Test status
Simulation time 35874218600 ps
CPU time 371.71 seconds
Started Mar 24 01:33:48 PM PDT 24
Finished Mar 24 01:40:00 PM PDT 24
Peak memory 229840 kb
Host smart-4e5d7f10-d592-494a-8bda-f79ab42a689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582146548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3582146548 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.1059189193
Short name T800
Test name
Test status
Simulation time 726461265 ps
CPU time 39.27 seconds
Started Mar 24 01:33:53 PM PDT 24
Finished Mar 24 01:34:33 PM PDT 24
Peak memory 224384 kb
Host smart-a2861678-225f-49b7-ab3e-881576739b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059189193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1059189193 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.1201036480
Short name T657
Test name
Test status
Simulation time 48690844651 ps
CPU time 341.26 seconds
Started Mar 24 01:33:53 PM PDT 24
Finished Mar 24 01:39:34 PM PDT 24
Peak memory 257288 kb
Host smart-93c38db7-d4d5-4f44-88ea-4fc1ccd5f59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201036480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1201036480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.3151762931
Short name T25
Test name
Test status
Simulation time 890539724 ps
CPU time 3 seconds
Started Mar 24 01:33:59 PM PDT 24
Finished Mar 24 01:34:02 PM PDT 24
Peak memory 207796 kb
Host smart-7f7e5cb7-17e1-49c3-89a8-cbc222a64520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151762931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3151762931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.725786517
Short name T5
Test name
Test status
Simulation time 25882614 ps
CPU time 1.27 seconds
Started Mar 24 01:33:58 PM PDT 24
Finished Mar 24 01:33:59 PM PDT 24
Peak memory 216588 kb
Host smart-fdfba268-c799-4d98-94bb-26b0e9a905d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725786517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.725786517 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.3886068364
Short name T826
Test name
Test status
Simulation time 53860994005 ps
CPU time 1090.97 seconds
Started Mar 24 01:33:48 PM PDT 24
Finished Mar 24 01:51:59 PM PDT 24
Peak memory 343696 kb
Host smart-a6c4b4ec-1f53-44f9-8000-6ac906be8b70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886068364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.3886068364 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.1520177477
Short name T433
Test name
Test status
Simulation time 4708650082 ps
CPU time 93.45 seconds
Started Mar 24 01:33:47 PM PDT 24
Finished Mar 24 01:35:21 PM PDT 24
Peak memory 227632 kb
Host smart-9a35fd0b-7553-4ed8-ac91-ff7f94d0c0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520177477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1520177477 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.2103036558
Short name T151
Test name
Test status
Simulation time 16526428259 ps
CPU time 67.08 seconds
Started Mar 24 01:33:49 PM PDT 24
Finished Mar 24 01:34:56 PM PDT 24
Peak memory 221100 kb
Host smart-c6131073-0cce-4b29-ba1f-ab09247adf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103036558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2103036558 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.1734104270
Short name T85
Test name
Test status
Simulation time 165862372099 ps
CPU time 1399.38 seconds
Started Mar 24 01:33:58 PM PDT 24
Finished Mar 24 01:57:18 PM PDT 24
Peak memory 429556 kb
Host smart-18222d1a-acfd-4e47-a203-02f87011a555
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1734104270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1734104270 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.2255465634
Short name T600
Test name
Test status
Simulation time 252155622 ps
CPU time 4.17 seconds
Started Mar 24 01:33:52 PM PDT 24
Finished Mar 24 01:33:57 PM PDT 24
Peak memory 216224 kb
Host smart-83ab6637-c555-4443-9ef5-1e67b59d7b74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255465634 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.2255465634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3715795201
Short name T755
Test name
Test status
Simulation time 766488053 ps
CPU time 4.74 seconds
Started Mar 24 01:33:54 PM PDT 24
Finished Mar 24 01:33:58 PM PDT 24
Peak memory 209284 kb
Host smart-e4b0cc8d-5241-4082-9bf2-d15ef054d60a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715795201 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3715795201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.1919435065
Short name T13
Test name
Test status
Simulation time 40010759120 ps
CPU time 1555.85 seconds
Started Mar 24 01:33:50 PM PDT 24
Finished Mar 24 01:59:46 PM PDT 24
Peak memory 400148 kb
Host smart-2bd75270-0392-44eb-8c72-66b3801dd896
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1919435065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.1919435065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.1815830777
Short name T1
Test name
Test status
Simulation time 62131022777 ps
CPU time 1668.83 seconds
Started Mar 24 01:33:47 PM PDT 24
Finished Mar 24 02:01:36 PM PDT 24
Peak memory 370252 kb
Host smart-da6d1082-1dd1-4b80-bb1e-de0a5c3b0799
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1815830777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.1815830777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.924025865
Short name T445
Test name
Test status
Simulation time 521886174583 ps
CPU time 1449.03 seconds
Started Mar 24 01:33:53 PM PDT 24
Finished Mar 24 01:58:02 PM PDT 24
Peak memory 335676 kb
Host smart-2b82bc10-d8ba-43b4-8284-9a568b8f49b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=924025865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.924025865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.2864228745
Short name T1021
Test name
Test status
Simulation time 145956580410 ps
CPU time 1018.79 seconds
Started Mar 24 01:33:53 PM PDT 24
Finished Mar 24 01:50:52 PM PDT 24
Peak memory 298108 kb
Host smart-85318086-8a53-4e24-8466-da8014e6dd13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2864228745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.2864228745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.3263300331
Short name T662
Test name
Test status
Simulation time 93015804122 ps
CPU time 4033.07 seconds
Started Mar 24 01:33:52 PM PDT 24
Finished Mar 24 02:41:06 PM PDT 24
Peak memory 657968 kb
Host smart-c687da3a-4946-4673-a158-d5e849e29cfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3263300331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3263300331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.3275923311
Short name T825
Test name
Test status
Simulation time 2708137802679 ps
CPU time 5248.1 seconds
Started Mar 24 01:33:52 PM PDT 24
Finished Mar 24 03:01:21 PM PDT 24
Peak memory 561576 kb
Host smart-cea4a00d-66ce-42c9-a9a6-bf8bf7e821ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3275923311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.3275923311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.1923373628
Short name T44
Test name
Test status
Simulation time 50290441 ps
CPU time 0.8 seconds
Started Mar 24 01:34:12 PM PDT 24
Finished Mar 24 01:34:14 PM PDT 24
Peak memory 205700 kb
Host smart-c1dcd129-7b98-464a-9c44-45bc7ac7ab21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923373628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1923373628 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.2047703913
Short name T1074
Test name
Test status
Simulation time 2972700429 ps
CPU time 174.24 seconds
Started Mar 24 01:34:07 PM PDT 24
Finished Mar 24 01:37:02 PM PDT 24
Peak memory 238056 kb
Host smart-2ad75cb7-60d4-4331-8a7c-2aee5425cd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047703913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2047703913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.1453317330
Short name T229
Test name
Test status
Simulation time 28228655714 ps
CPU time 752.27 seconds
Started Mar 24 01:34:01 PM PDT 24
Finished Mar 24 01:46:34 PM PDT 24
Peak memory 232856 kb
Host smart-ac876253-b2fc-4782-82bd-19b9be79dfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453317330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.1453317330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.518443551
Short name T681
Test name
Test status
Simulation time 8145451942 ps
CPU time 77.42 seconds
Started Mar 24 01:34:12 PM PDT 24
Finished Mar 24 01:35:31 PM PDT 24
Peak memory 240668 kb
Host smart-8fdef850-53ff-4297-982d-583a8dec6e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518443551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.518443551 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.1465940070
Short name T909
Test name
Test status
Simulation time 1196562262 ps
CPU time 37.42 seconds
Started Mar 24 01:34:12 PM PDT 24
Finished Mar 24 01:34:51 PM PDT 24
Peak memory 236144 kb
Host smart-3d76fd9e-d5f6-4412-bef8-4e26a5086884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465940070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1465940070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.1917759954
Short name T65
Test name
Test status
Simulation time 72109997 ps
CPU time 1.04 seconds
Started Mar 24 01:34:11 PM PDT 24
Finished Mar 24 01:34:13 PM PDT 24
Peak memory 206180 kb
Host smart-fb1a9ecc-9e28-4d84-be8c-99485fc6134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917759954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1917759954 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.177231008
Short name T963
Test name
Test status
Simulation time 63800092 ps
CPU time 1.19 seconds
Started Mar 24 01:34:07 PM PDT 24
Finished Mar 24 01:34:09 PM PDT 24
Peak memory 215972 kb
Host smart-8a68f49f-f265-4181-afb1-12eb8ed796b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177231008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.177231008 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.1123644126
Short name T277
Test name
Test status
Simulation time 78797815692 ps
CPU time 1638.76 seconds
Started Mar 24 01:33:58 PM PDT 24
Finished Mar 24 02:01:17 PM PDT 24
Peak memory 404644 kb
Host smart-93634593-15a6-4081-9e65-650e6b316ad2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123644126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.1123644126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3532006890
Short name T962
Test name
Test status
Simulation time 14265589951 ps
CPU time 304.64 seconds
Started Mar 24 01:33:57 PM PDT 24
Finished Mar 24 01:39:02 PM PDT 24
Peak memory 244892 kb
Host smart-d2b22bb1-a803-4ead-a15a-09d70af46b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532006890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3532006890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.2623658688
Short name T870
Test name
Test status
Simulation time 1494598123 ps
CPU time 23.66 seconds
Started Mar 24 01:33:58 PM PDT 24
Finished Mar 24 01:34:21 PM PDT 24
Peak memory 222132 kb
Host smart-aee5839b-a111-4403-9d35-e3ed30cc0375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623658688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2623658688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.274074844
Short name T845
Test name
Test status
Simulation time 42823451833 ps
CPU time 1208.25 seconds
Started Mar 24 01:34:12 PM PDT 24
Finished Mar 24 01:54:21 PM PDT 24
Peak memory 364996 kb
Host smart-3596c748-d769-48f2-98ef-57f529117df0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=274074844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.274074844 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.1140892542
Short name T394
Test name
Test status
Simulation time 219269027 ps
CPU time 4.77 seconds
Started Mar 24 01:34:08 PM PDT 24
Finished Mar 24 01:34:13 PM PDT 24
Peak memory 216272 kb
Host smart-1ce7daf3-0b5e-4f9c-9fd2-b223cbe75437
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140892542 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.1140892542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.1800969658
Short name T487
Test name
Test status
Simulation time 233981875 ps
CPU time 3.95 seconds
Started Mar 24 01:34:11 PM PDT 24
Finished Mar 24 01:34:15 PM PDT 24
Peak memory 216316 kb
Host smart-edb676a1-1300-4ec7-83db-b49f44fa5d67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800969658 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.1800969658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.3644433659
Short name T552
Test name
Test status
Simulation time 77043764336 ps
CPU time 1525.73 seconds
Started Mar 24 01:34:06 PM PDT 24
Finished Mar 24 01:59:32 PM PDT 24
Peak memory 378664 kb
Host smart-d0e6876a-32f3-41f7-92dc-37bf1528aab8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3644433659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3644433659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.136719263
Short name T833
Test name
Test status
Simulation time 330579095324 ps
CPU time 1651.6 seconds
Started Mar 24 01:34:02 PM PDT 24
Finished Mar 24 02:01:34 PM PDT 24
Peak memory 364468 kb
Host smart-300f7e4f-a420-4054-95d5-1321687e3ec1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=136719263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.136719263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.2616666584
Short name T405
Test name
Test status
Simulation time 155863234922 ps
CPU time 1367.84 seconds
Started Mar 24 01:34:05 PM PDT 24
Finished Mar 24 01:56:53 PM PDT 24
Peak memory 335356 kb
Host smart-bf13138a-0ae8-4f0e-a05f-00c68a53a529
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2616666584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.2616666584 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.464885518
Short name T426
Test name
Test status
Simulation time 197905840626 ps
CPU time 1003.54 seconds
Started Mar 24 01:34:02 PM PDT 24
Finished Mar 24 01:50:46 PM PDT 24
Peak memory 298132 kb
Host smart-50567281-3c68-4e42-bd26-19ee7200dddc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=464885518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.464885518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.3453395564
Short name T294
Test name
Test status
Simulation time 351948729169 ps
CPU time 5262.74 seconds
Started Mar 24 01:34:13 PM PDT 24
Finished Mar 24 03:01:57 PM PDT 24
Peak memory 637980 kb
Host smart-5fb8697f-6986-414c-8dee-dd6bb43e5edf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3453395564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.3453395564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.3931127337
Short name T216
Test name
Test status
Simulation time 44602406952 ps
CPU time 3523.94 seconds
Started Mar 24 01:34:09 PM PDT 24
Finished Mar 24 02:32:54 PM PDT 24
Peak memory 562000 kb
Host smart-c02aa689-5f3e-4b08-bc24-1a68c4dc35a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3931127337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3931127337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.2707111429
Short name T336
Test name
Test status
Simulation time 24692772 ps
CPU time 0.74 seconds
Started Mar 24 01:34:33 PM PDT 24
Finished Mar 24 01:34:34 PM PDT 24
Peak memory 205736 kb
Host smart-81864263-9da0-4dcd-8859-5c687dd8b695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707111429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2707111429 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.3914785680
Short name T1003
Test name
Test status
Simulation time 3830199519 ps
CPU time 92.96 seconds
Started Mar 24 01:34:29 PM PDT 24
Finished Mar 24 01:36:03 PM PDT 24
Peak memory 228488 kb
Host smart-08f8fc04-6daf-4437-bc12-b9d7e4f33242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914785680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3914785680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.979878253
Short name T1082
Test name
Test status
Simulation time 27781750314 ps
CPU time 602.19 seconds
Started Mar 24 01:34:22 PM PDT 24
Finished Mar 24 01:44:24 PM PDT 24
Peak memory 232744 kb
Host smart-fda603a2-2d51-4564-b502-b535492c80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979878253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.979878253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.547200063
Short name T291
Test name
Test status
Simulation time 16364841046 ps
CPU time 268.25 seconds
Started Mar 24 01:34:32 PM PDT 24
Finished Mar 24 01:39:00 PM PDT 24
Peak memory 242872 kb
Host smart-f6e9b439-6f5a-4f85-98b2-061594730b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547200063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.547200063 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.2218138686
Short name T1033
Test name
Test status
Simulation time 3187536910 ps
CPU time 246.19 seconds
Started Mar 24 01:34:32 PM PDT 24
Finished Mar 24 01:38:38 PM PDT 24
Peak memory 257288 kb
Host smart-14eb4b6a-8f7a-4ec8-9395-91ee8332929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218138686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2218138686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.271965822
Short name T1069
Test name
Test status
Simulation time 955642966 ps
CPU time 1.94 seconds
Started Mar 24 01:34:32 PM PDT 24
Finished Mar 24 01:34:34 PM PDT 24
Peak memory 207452 kb
Host smart-dd23702e-6222-45d4-ace8-baf170a44de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271965822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.271965822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.519913418
Short name T60
Test name
Test status
Simulation time 56561919 ps
CPU time 1.2 seconds
Started Mar 24 01:34:33 PM PDT 24
Finished Mar 24 01:34:34 PM PDT 24
Peak memory 216076 kb
Host smart-9dc0022d-e4e8-4037-a884-76e1caeada75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519913418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.519913418 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.4130824932
Short name T232
Test name
Test status
Simulation time 13824383474 ps
CPU time 275.06 seconds
Started Mar 24 01:34:23 PM PDT 24
Finished Mar 24 01:38:58 PM PDT 24
Peak memory 248808 kb
Host smart-20568168-4b43-4071-8624-6a3075445257
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130824932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.4130824932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.2791424434
Short name T794
Test name
Test status
Simulation time 73633067493 ps
CPU time 405.97 seconds
Started Mar 24 01:34:24 PM PDT 24
Finished Mar 24 01:41:10 PM PDT 24
Peak memory 250920 kb
Host smart-0fa8790d-fcea-4488-9ccf-903a9eefbcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791424434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2791424434 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.4231674935
Short name T344
Test name
Test status
Simulation time 1793358711 ps
CPU time 46.94 seconds
Started Mar 24 01:34:18 PM PDT 24
Finished Mar 24 01:35:06 PM PDT 24
Peak memory 216252 kb
Host smart-d3ec6777-bd50-4cbb-8828-cd96fff1dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231674935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.4231674935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.120155735
Short name T596
Test name
Test status
Simulation time 23006148093 ps
CPU time 1912.34 seconds
Started Mar 24 01:34:33 PM PDT 24
Finished Mar 24 02:06:27 PM PDT 24
Peak memory 444108 kb
Host smart-0f39bc77-e2f0-443f-a4fe-abef4e0f9d6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=120155735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.120155735 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.1636809641
Short name T236
Test name
Test status
Simulation time 305043703 ps
CPU time 4.33 seconds
Started Mar 24 01:34:29 PM PDT 24
Finished Mar 24 01:34:34 PM PDT 24
Peak memory 216232 kb
Host smart-9a2e4625-7275-47e4-b82d-bd1703e4a918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636809641 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.1636809641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.3679094843
Short name T943
Test name
Test status
Simulation time 722336007 ps
CPU time 4.83 seconds
Started Mar 24 01:34:30 PM PDT 24
Finished Mar 24 01:34:35 PM PDT 24
Peak memory 216228 kb
Host smart-4f4b2ee7-9939-4c68-a4d5-9a52fd203c11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679094843 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.3679094843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.3917444444
Short name T47
Test name
Test status
Simulation time 137699388029 ps
CPU time 1833.36 seconds
Started Mar 24 01:34:23 PM PDT 24
Finished Mar 24 02:04:57 PM PDT 24
Peak memory 391224 kb
Host smart-73a949c4-b626-4483-9fc4-ed75b9325ce9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3917444444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3917444444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.32935661
Short name T583
Test name
Test status
Simulation time 64337158206 ps
CPU time 1809.37 seconds
Started Mar 24 01:34:23 PM PDT 24
Finished Mar 24 02:04:33 PM PDT 24
Peak memory 375064 kb
Host smart-2a049e57-b55b-4221-b7c9-394537656dd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=32935661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.32935661 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.988023039
Short name T748
Test name
Test status
Simulation time 117036959220 ps
CPU time 1241.82 seconds
Started Mar 24 01:34:22 PM PDT 24
Finished Mar 24 01:55:04 PM PDT 24
Peak memory 335016 kb
Host smart-6df53916-82c8-4fc3-ac14-c0ded6c92015
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=988023039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.988023039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.89172757
Short name T480
Test name
Test status
Simulation time 194784045569 ps
CPU time 943.5 seconds
Started Mar 24 01:34:23 PM PDT 24
Finished Mar 24 01:50:07 PM PDT 24
Peak memory 295068 kb
Host smart-54cf0465-36dd-4b3a-a108-2cd5edaaa514
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=89172757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.89172757 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.332969069
Short name T352
Test name
Test status
Simulation time 444350915052 ps
CPU time 5067.64 seconds
Started Mar 24 01:34:23 PM PDT 24
Finished Mar 24 02:58:52 PM PDT 24
Peak memory 649496 kb
Host smart-698e01db-9adb-473a-8493-c7ecf15892c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=332969069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.332969069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.2528370444
Short name T671
Test name
Test status
Simulation time 150647555450 ps
CPU time 3616.2 seconds
Started Mar 24 01:34:27 PM PDT 24
Finished Mar 24 02:34:44 PM PDT 24
Peak memory 558420 kb
Host smart-f6b24268-34fb-456e-b74b-5a565842d97c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2528370444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.2528370444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1041918133
Short name T1054
Test name
Test status
Simulation time 40038970 ps
CPU time 0.77 seconds
Started Mar 24 01:25:49 PM PDT 24
Finished Mar 24 01:25:50 PM PDT 24
Peak memory 205732 kb
Host smart-efb34159-3933-46fd-a7d4-373ac12e66b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041918133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1041918133 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.3638218177
Short name T744
Test name
Test status
Simulation time 123856088526 ps
CPU time 224.91 seconds
Started Mar 24 01:25:55 PM PDT 24
Finished Mar 24 01:29:40 PM PDT 24
Peak memory 241292 kb
Host smart-8e05a7e0-0b17-4fb2-a554-f66e1794a5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638218177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3638218177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.351025844
Short name T288
Test name
Test status
Simulation time 970331881 ps
CPU time 28.78 seconds
Started Mar 24 01:25:56 PM PDT 24
Finished Mar 24 01:26:25 PM PDT 24
Peak memory 224360 kb
Host smart-6539c61f-2580-4f92-af9f-36c20b15ab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351025844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.351025844 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.721171000
Short name T965
Test name
Test status
Simulation time 36007534963 ps
CPU time 769.18 seconds
Started Mar 24 01:25:43 PM PDT 24
Finished Mar 24 01:38:33 PM PDT 24
Peak memory 232900 kb
Host smart-51b27e1d-3c4a-4328-9577-55a7131097ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721171000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.721171000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.1324706703
Short name T690
Test name
Test status
Simulation time 439887273 ps
CPU time 27.04 seconds
Started Mar 24 01:25:47 PM PDT 24
Finished Mar 24 01:26:14 PM PDT 24
Peak memory 224268 kb
Host smart-129fa368-7230-4236-a7cd-3a235336551b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1324706703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1324706703 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.351808485
Short name T351
Test name
Test status
Simulation time 1731051716 ps
CPU time 33.21 seconds
Started Mar 24 01:25:50 PM PDT 24
Finished Mar 24 01:26:23 PM PDT 24
Peak memory 224232 kb
Host smart-83d04e57-2e6a-4027-b850-2b1ebdd31ea2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=351808485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.351808485 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.3781647054
Short name T680
Test name
Test status
Simulation time 1176764981 ps
CPU time 6.96 seconds
Started Mar 24 01:25:46 PM PDT 24
Finished Mar 24 01:25:53 PM PDT 24
Peak memory 217312 kb
Host smart-15cccf13-5b20-425f-bf98-7b9bf80b07d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781647054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3781647054 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.1644701805
Short name T378
Test name
Test status
Simulation time 3472375329 ps
CPU time 161.44 seconds
Started Mar 24 01:25:47 PM PDT 24
Finished Mar 24 01:28:28 PM PDT 24
Peak memory 239084 kb
Host smart-07dd8aae-7c64-4a07-970c-43c6960b6363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644701805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1644701805 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.2523528064
Short name T22
Test name
Test status
Simulation time 24566065624 ps
CPU time 328.9 seconds
Started Mar 24 01:25:56 PM PDT 24
Finished Mar 24 01:31:25 PM PDT 24
Peak memory 257252 kb
Host smart-e0f3a3e1-d19e-4a18-bebc-7b971b9d29aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523528064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2523528064 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.1754488414
Short name T881
Test name
Test status
Simulation time 592029293 ps
CPU time 1.53 seconds
Started Mar 24 01:25:46 PM PDT 24
Finished Mar 24 01:25:48 PM PDT 24
Peak memory 207536 kb
Host smart-14a77a30-a322-4e00-b69c-33aae5275525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754488414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1754488414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.1744080659
Short name T39
Test name
Test status
Simulation time 69998502 ps
CPU time 1.36 seconds
Started Mar 24 01:25:50 PM PDT 24
Finished Mar 24 01:25:51 PM PDT 24
Peak memory 216096 kb
Host smart-bb8ba2e0-6afe-4dcc-af76-54c5db9daea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744080659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1744080659 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.3614891605
Short name T644
Test name
Test status
Simulation time 349488431302 ps
CPU time 2523.39 seconds
Started Mar 24 01:25:47 PM PDT 24
Finished Mar 24 02:07:50 PM PDT 24
Peak memory 474404 kb
Host smart-5780773c-0bd1-4133-84f6-63c28adda030
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614891605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.3614891605 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.2516314605
Short name T83
Test name
Test status
Simulation time 11871091767 ps
CPU time 311.66 seconds
Started Mar 24 01:25:48 PM PDT 24
Finished Mar 24 01:31:00 PM PDT 24
Peak memory 244836 kb
Host smart-76cd3d38-d24f-437f-a3b1-9fe5375b87fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516314605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2516314605 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.3571981534
Short name T241
Test name
Test status
Simulation time 479170829 ps
CPU time 3.07 seconds
Started Mar 24 01:25:47 PM PDT 24
Finished Mar 24 01:25:50 PM PDT 24
Peak memory 218512 kb
Host smart-0aa5722c-a223-418e-ae69-8f247247f639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571981534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3571981534 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.202136843
Short name T595
Test name
Test status
Simulation time 3453465583 ps
CPU time 42.09 seconds
Started Mar 24 01:25:45 PM PDT 24
Finished Mar 24 01:26:27 PM PDT 24
Peak memory 222496 kb
Host smart-75e0c674-c54a-4791-bb66-bf9ff5fa455c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202136843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.202136843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.1693170787
Short name T121
Test name
Test status
Simulation time 17360500754 ps
CPU time 955.04 seconds
Started Mar 24 01:25:55 PM PDT 24
Finished Mar 24 01:41:51 PM PDT 24
Peak memory 347376 kb
Host smart-b54caa2c-7c9d-4062-ad63-985dc4104b68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1693170787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1693170787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.2149281254
Short name T143
Test name
Test status
Simulation time 136559127155 ps
CPU time 1342.52 seconds
Started Mar 24 01:25:49 PM PDT 24
Finished Mar 24 01:48:12 PM PDT 24
Peak memory 366712 kb
Host smart-68463a28-ab07-4b81-9596-8faf386aa979
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149281254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.2149281254 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.1115164486
Short name T416
Test name
Test status
Simulation time 173265245 ps
CPU time 4.88 seconds
Started Mar 24 01:25:50 PM PDT 24
Finished Mar 24 01:25:55 PM PDT 24
Peak memory 216224 kb
Host smart-da755273-1604-4799-b5b0-0364e47663d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115164486 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.1115164486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3363286494
Short name T513
Test name
Test status
Simulation time 678332770 ps
CPU time 4.18 seconds
Started Mar 24 01:25:55 PM PDT 24
Finished Mar 24 01:25:59 PM PDT 24
Peak memory 216220 kb
Host smart-e1646d98-e8a2-4bb8-a769-bae804260ca7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363286494 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3363286494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.1562816517
Short name T1019
Test name
Test status
Simulation time 98104438168 ps
CPU time 1982.01 seconds
Started Mar 24 01:25:44 PM PDT 24
Finished Mar 24 01:58:46 PM PDT 24
Peak memory 388880 kb
Host smart-2dc6e510-b001-4864-b061-badff393a043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1562816517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.1562816517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.1550446807
Short name T361
Test name
Test status
Simulation time 39177673054 ps
CPU time 1548.52 seconds
Started Mar 24 01:25:44 PM PDT 24
Finished Mar 24 01:51:33 PM PDT 24
Peak memory 387508 kb
Host smart-a8997838-c63d-4c96-97b0-53d1d62329f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1550446807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1550446807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.621568263
Short name T896
Test name
Test status
Simulation time 773434534880 ps
CPU time 1696.15 seconds
Started Mar 24 01:25:42 PM PDT 24
Finished Mar 24 01:53:58 PM PDT 24
Peak memory 333484 kb
Host smart-b6c101b1-c7fc-4cea-9e6b-cdb352ab5487
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=621568263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.621568263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.4168364765
Short name T561
Test name
Test status
Simulation time 210228618843 ps
CPU time 1126.4 seconds
Started Mar 24 01:25:44 PM PDT 24
Finished Mar 24 01:44:31 PM PDT 24
Peak memory 301292 kb
Host smart-96dd7a07-ad0a-4139-a209-c4d8da3c4c6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4168364765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.4168364765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.186008097
Short name T988
Test name
Test status
Simulation time 102785455907 ps
CPU time 4212.95 seconds
Started Mar 24 01:25:42 PM PDT 24
Finished Mar 24 02:35:56 PM PDT 24
Peak memory 640896 kb
Host smart-d2f71d5f-f06b-449f-bf8f-a24d810d4a4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=186008097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.186008097 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.3235079297
Short name T865
Test name
Test status
Simulation time 160173552573 ps
CPU time 3530.49 seconds
Started Mar 24 01:25:49 PM PDT 24
Finished Mar 24 02:24:40 PM PDT 24
Peak memory 561188 kb
Host smart-a10c9cdb-f03a-49b9-b57c-0b8057b8c8c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3235079297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.3235079297 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.3798868525
Short name T349
Test name
Test status
Simulation time 19083604 ps
CPU time 0.8 seconds
Started Mar 24 01:25:52 PM PDT 24
Finished Mar 24 01:25:53 PM PDT 24
Peak memory 205696 kb
Host smart-c405352e-d6c2-466f-83db-041615c8ccfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798868525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3798868525 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.490477947
Short name T75
Test name
Test status
Simulation time 21778892865 ps
CPU time 107 seconds
Started Mar 24 01:25:54 PM PDT 24
Finished Mar 24 01:27:42 PM PDT 24
Peak memory 230596 kb
Host smart-309ba7ac-a530-4a63-bfd0-6faa0fff3cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490477947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.490477947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_burst_write.2836815877
Short name T18
Test name
Test status
Simulation time 577918851 ps
CPU time 49.37 seconds
Started Mar 24 01:25:48 PM PDT 24
Finished Mar 24 01:26:38 PM PDT 24
Peak memory 219260 kb
Host smart-e6107a59-27e7-4a00-8c5c-79d0b8aa0b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836815877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2836815877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.102159282
Short name T230
Test name
Test status
Simulation time 276161187 ps
CPU time 5.24 seconds
Started Mar 24 01:25:53 PM PDT 24
Finished Mar 24 01:25:59 PM PDT 24
Peak memory 219132 kb
Host smart-962bd643-5825-48f5-9908-533a52431b5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=102159282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.102159282 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.3951937803
Short name T977
Test name
Test status
Simulation time 3867388594 ps
CPU time 7.52 seconds
Started Mar 24 01:25:52 PM PDT 24
Finished Mar 24 01:26:00 PM PDT 24
Peak memory 224304 kb
Host smart-95d2731b-c072-4aca-a09b-d73fa89f4654
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3951937803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3951937803 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.1840794792
Short name T651
Test name
Test status
Simulation time 162098773 ps
CPU time 2.71 seconds
Started Mar 24 01:25:55 PM PDT 24
Finished Mar 24 01:25:58 PM PDT 24
Peak memory 216244 kb
Host smart-8a5165bf-a52c-49a7-a8fd-172800c8648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840794792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1840794792 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.2449536162
Short name T23
Test name
Test status
Simulation time 1005443769 ps
CPU time 14.17 seconds
Started Mar 24 01:25:54 PM PDT 24
Finished Mar 24 01:26:09 PM PDT 24
Peak memory 217264 kb
Host smart-022299fb-81a6-47a5-af29-20cf17e4546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449536162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.2449536162 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.1231232301
Short name T99
Test name
Test status
Simulation time 10309193530 ps
CPU time 284.66 seconds
Started Mar 24 01:25:52 PM PDT 24
Finished Mar 24 01:30:37 PM PDT 24
Peak memory 254796 kb
Host smart-d58aa8b0-a1f0-4ad8-b8b7-c806ffdcbb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231232301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1231232301 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.515874873
Short name T622
Test name
Test status
Simulation time 721620121 ps
CPU time 4.53 seconds
Started Mar 24 01:25:55 PM PDT 24
Finished Mar 24 01:26:00 PM PDT 24
Peak memory 207624 kb
Host smart-27a4b439-1480-4ff7-b41e-094af007bb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515874873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.515874873 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.1723545022
Short name T312
Test name
Test status
Simulation time 74487434832 ps
CPU time 1557.91 seconds
Started Mar 24 01:25:48 PM PDT 24
Finished Mar 24 01:51:46 PM PDT 24
Peak memory 358748 kb
Host smart-45655dc4-b3e7-4fdf-820b-3914ec209978
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723545022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.1723545022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.2075499970
Short name T652
Test name
Test status
Simulation time 4254939235 ps
CPU time 87.97 seconds
Started Mar 24 01:25:53 PM PDT 24
Finished Mar 24 01:27:21 PM PDT 24
Peak memory 228228 kb
Host smart-00a0693b-5e90-427f-9806-9205dddd0c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075499970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2075499970 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.911018272
Short name T481
Test name
Test status
Simulation time 1484065974 ps
CPU time 10.39 seconds
Started Mar 24 01:25:56 PM PDT 24
Finished Mar 24 01:26:06 PM PDT 24
Peak memory 220960 kb
Host smart-5dece6eb-e2f4-43c1-8297-a01a10b1670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911018272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.911018272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.2890899018
Short name T350
Test name
Test status
Simulation time 1013912813 ps
CPU time 49.59 seconds
Started Mar 24 01:25:47 PM PDT 24
Finished Mar 24 01:26:37 PM PDT 24
Peak memory 220264 kb
Host smart-9cd9a136-3a89-472c-b70e-d754905d28cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890899018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2890899018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.2131136182
Short name T746
Test name
Test status
Simulation time 4433488591 ps
CPU time 277.41 seconds
Started Mar 24 01:25:54 PM PDT 24
Finished Mar 24 01:30:32 PM PDT 24
Peak memory 282124 kb
Host smart-004b0dad-4e41-4f75-9e8f-51777fbaf870
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2131136182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2131136182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.3958814700
Short name T1017
Test name
Test status
Simulation time 282212641 ps
CPU time 4.85 seconds
Started Mar 24 01:25:55 PM PDT 24
Finished Mar 24 01:26:00 PM PDT 24
Peak memory 216468 kb
Host smart-3d6d9520-e7f9-46ad-b734-3c1f6e7a0d40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958814700 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.3958814700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.2755354518
Short name T843
Test name
Test status
Simulation time 66719750 ps
CPU time 4.02 seconds
Started Mar 24 01:25:54 PM PDT 24
Finished Mar 24 01:25:59 PM PDT 24
Peak memory 216280 kb
Host smart-b6141371-15ec-4850-a783-03541a5c239d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755354518 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.2755354518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.4111695231
Short name T884
Test name
Test status
Simulation time 18906848960 ps
CPU time 1596.48 seconds
Started Mar 24 01:25:48 PM PDT 24
Finished Mar 24 01:52:25 PM PDT 24
Peak memory 394484 kb
Host smart-ded75652-1e95-4b5b-9e10-e4180e495d82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4111695231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.4111695231 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.2795095445
Short name T968
Test name
Test status
Simulation time 873953836071 ps
CPU time 1719.52 seconds
Started Mar 24 01:25:49 PM PDT 24
Finished Mar 24 01:54:29 PM PDT 24
Peak memory 371444 kb
Host smart-df3d95c0-f9ef-481b-99f5-79e0f80052d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2795095445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.2795095445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.985063906
Short name T550
Test name
Test status
Simulation time 14059363059 ps
CPU time 1023.19 seconds
Started Mar 24 01:25:54 PM PDT 24
Finished Mar 24 01:42:58 PM PDT 24
Peak memory 331608 kb
Host smart-bfac1cd0-9015-4db8-847a-ddc5a3432058
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=985063906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.985063906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.3356129003
Short name T677
Test name
Test status
Simulation time 10930141406 ps
CPU time 761.44 seconds
Started Mar 24 01:25:52 PM PDT 24
Finished Mar 24 01:38:33 PM PDT 24
Peak memory 295700 kb
Host smart-a7bad6a2-7ad3-40bc-87a1-8ce9c151a036
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3356129003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.3356129003 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.2269754318
Short name T989
Test name
Test status
Simulation time 262344293404 ps
CPU time 5139.74 seconds
Started Mar 24 01:25:53 PM PDT 24
Finished Mar 24 02:51:33 PM PDT 24
Peak memory 652576 kb
Host smart-47018c4f-c32d-44e9-a322-14f68799bd26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2269754318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.2269754318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.1313813062
Short name T814
Test name
Test status
Simulation time 43213262191 ps
CPU time 3509.25 seconds
Started Mar 24 01:25:52 PM PDT 24
Finished Mar 24 02:24:22 PM PDT 24
Peak memory 560256 kb
Host smart-f33b78c1-b4d0-4e0e-9e82-6148261bc1a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1313813062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1313813062 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.1946668298
Short name T398
Test name
Test status
Simulation time 23664601 ps
CPU time 0.77 seconds
Started Mar 24 01:26:05 PM PDT 24
Finished Mar 24 01:26:06 PM PDT 24
Peak memory 205700 kb
Host smart-22583b3f-cdbf-4d90-af0a-6c195bff5b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946668298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1946668298 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.1129692245
Short name T811
Test name
Test status
Simulation time 2984145638 ps
CPU time 157.95 seconds
Started Mar 24 01:25:56 PM PDT 24
Finished Mar 24 01:28:34 PM PDT 24
Peak memory 237000 kb
Host smart-f9a52040-e361-46aa-bebd-1335e92d6d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129692245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1129692245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.1488758276
Short name T32
Test name
Test status
Simulation time 49485298454 ps
CPU time 97.54 seconds
Started Mar 24 01:25:58 PM PDT 24
Finished Mar 24 01:27:36 PM PDT 24
Peak memory 228448 kb
Host smart-067b2a8e-5246-4b88-ad5d-a60937404385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488758276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.1488758276 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.540874632
Short name T90
Test name
Test status
Simulation time 67146136324 ps
CPU time 440.95 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 01:33:19 PM PDT 24
Peak memory 229192 kb
Host smart-8c6bfbca-84a8-4bc9-b80d-d54f3d2d6bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540874632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.540874632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.3142047309
Short name T642
Test name
Test status
Simulation time 87776116 ps
CPU time 5.86 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 01:26:04 PM PDT 24
Peak memory 220456 kb
Host smart-affeb6bf-b0cd-4e63-b0f1-5b6d19230477
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3142047309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.3142047309 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.1586627416
Short name T306
Test name
Test status
Simulation time 3990579204 ps
CPU time 37.52 seconds
Started Mar 24 01:25:58 PM PDT 24
Finished Mar 24 01:26:36 PM PDT 24
Peak memory 224288 kb
Host smart-09fccb42-c2f8-4e12-b6d4-f17a7dea26bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1586627416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1586627416 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3381682146
Short name T856
Test name
Test status
Simulation time 10779697388 ps
CPU time 55.78 seconds
Started Mar 24 01:25:59 PM PDT 24
Finished Mar 24 01:26:55 PM PDT 24
Peak memory 216352 kb
Host smart-931ded66-81cf-4148-8c84-bc9edaedefe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381682146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3381682146 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.919259404
Short name T390
Test name
Test status
Simulation time 17598487752 ps
CPU time 151.08 seconds
Started Mar 24 01:25:56 PM PDT 24
Finished Mar 24 01:28:27 PM PDT 24
Peak memory 234452 kb
Host smart-14948689-4ef1-4555-8a21-740615812f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919259404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.919259404 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.1589684849
Short name T531
Test name
Test status
Simulation time 68525321693 ps
CPU time 233.54 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 01:29:51 PM PDT 24
Peak memory 249840 kb
Host smart-8f7d4b13-6c71-4c49-bb05-389fd3c2ad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589684849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1589684849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.2502365982
Short name T490
Test name
Test status
Simulation time 970966046 ps
CPU time 4.19 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 01:26:02 PM PDT 24
Peak memory 207848 kb
Host smart-8a24d8a1-cf69-42b8-9c99-19fb5f433bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502365982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.2502365982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.4199746391
Short name T910
Test name
Test status
Simulation time 47849656 ps
CPU time 1.4 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 01:26:00 PM PDT 24
Peak memory 217136 kb
Host smart-3fa1099a-b094-46a3-9b1f-e3fdf242f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199746391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.4199746391 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.3564917543
Short name T942
Test name
Test status
Simulation time 43707446683 ps
CPU time 613 seconds
Started Mar 24 01:25:53 PM PDT 24
Finished Mar 24 01:36:06 PM PDT 24
Peak memory 282008 kb
Host smart-a0d1740c-f5c2-4708-88f4-9e49b7a6db46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564917543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.3564917543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.3490130430
Short name T621
Test name
Test status
Simulation time 10624548767 ps
CPU time 261.94 seconds
Started Mar 24 01:25:56 PM PDT 24
Finished Mar 24 01:30:19 PM PDT 24
Peak memory 245184 kb
Host smart-a0a95191-e07a-452c-8243-5fa921c31f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490130430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3490130430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.3585779103
Short name T871
Test name
Test status
Simulation time 11094942139 ps
CPU time 71.92 seconds
Started Mar 24 01:25:53 PM PDT 24
Finished Mar 24 01:27:05 PM PDT 24
Peak memory 225192 kb
Host smart-9178f324-c38d-49c1-80c0-9320bdc5c8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585779103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3585779103 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.2455474374
Short name T766
Test name
Test status
Simulation time 819468180 ps
CPU time 42.63 seconds
Started Mar 24 01:25:51 PM PDT 24
Finished Mar 24 01:26:34 PM PDT 24
Peak memory 219748 kb
Host smart-5061274c-cecc-4697-8a37-f578ad872f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455474374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2455474374 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.3764212653
Short name T81
Test name
Test status
Simulation time 264649733011 ps
CPU time 1499.12 seconds
Started Mar 24 01:25:58 PM PDT 24
Finished Mar 24 01:50:58 PM PDT 24
Peak memory 351604 kb
Host smart-a494de2d-6c44-43ee-8441-3870445a2f06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3764212653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3764212653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.3895006215
Short name T56
Test name
Test status
Simulation time 30209838267 ps
CPU time 431.52 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 01:33:10 PM PDT 24
Peak memory 249356 kb
Host smart-fe940eb7-fe08-4b90-9e0f-5e600091df5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895006215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.3895006215 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.3153428179
Short name T329
Test name
Test status
Simulation time 917608410 ps
CPU time 5.25 seconds
Started Mar 24 01:25:58 PM PDT 24
Finished Mar 24 01:26:04 PM PDT 24
Peak memory 216248 kb
Host smart-1d89dc87-44e2-423b-a4a1-42b2efb970e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153428179 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.3153428179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2370809192
Short name T221
Test name
Test status
Simulation time 349740780 ps
CPU time 5.03 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 01:26:03 PM PDT 24
Peak memory 216336 kb
Host smart-89e859f1-c0e6-4643-90c8-ddb4b0da9dcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370809192 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2370809192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.3428771540
Short name T486
Test name
Test status
Simulation time 87315328470 ps
CPU time 1931.02 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 01:58:09 PM PDT 24
Peak memory 379060 kb
Host smart-220a6f1b-b968-4258-b86c-f8b0526b502d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3428771540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.3428771540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.3532336823
Short name T545
Test name
Test status
Simulation time 17476316786 ps
CPU time 1427.21 seconds
Started Mar 24 01:25:53 PM PDT 24
Finished Mar 24 01:49:40 PM PDT 24
Peak memory 369192 kb
Host smart-288e7336-6b04-4ada-a5eb-deeb0d934729
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3532336823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3532336823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.3148906838
Short name T368
Test name
Test status
Simulation time 279211892349 ps
CPU time 1344.71 seconds
Started Mar 24 01:25:58 PM PDT 24
Finished Mar 24 01:48:23 PM PDT 24
Peak memory 322904 kb
Host smart-83093600-a4ea-44b1-adbc-56bc0176185d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3148906838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.3148906838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.2501794907
Short name T713
Test name
Test status
Simulation time 42155931822 ps
CPU time 897.77 seconds
Started Mar 24 01:26:07 PM PDT 24
Finished Mar 24 01:41:05 PM PDT 24
Peak memory 294400 kb
Host smart-1babb294-9002-414a-a868-054a5b1b99c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2501794907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.2501794907 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.256993784
Short name T403
Test name
Test status
Simulation time 172171123548 ps
CPU time 4796.33 seconds
Started Mar 24 01:25:59 PM PDT 24
Finished Mar 24 02:45:56 PM PDT 24
Peak memory 652600 kb
Host smart-5f702ae5-b3b1-490d-bf9a-b5e148db3805
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=256993784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.256993784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.172725781
Short name T850
Test name
Test status
Simulation time 445296007978 ps
CPU time 4310.15 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 02:37:49 PM PDT 24
Peak memory 568088 kb
Host smart-f85f9820-1b66-482e-a4d9-5ca55cc4dae4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=172725781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.172725781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.1230096094
Short name T389
Test name
Test status
Simulation time 33278064 ps
CPU time 0.77 seconds
Started Mar 24 01:26:10 PM PDT 24
Finished Mar 24 01:26:11 PM PDT 24
Peak memory 205736 kb
Host smart-07dcbc52-ae60-450f-830d-e74f1f4182ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230096094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1230096094 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.3890965040
Short name T282
Test name
Test status
Simulation time 3270658037 ps
CPU time 50.82 seconds
Started Mar 24 01:26:09 PM PDT 24
Finished Mar 24 01:27:00 PM PDT 24
Peak memory 225424 kb
Host smart-5a7cd3cf-e6da-4adb-a2f1-4be9223fe8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890965040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3890965040 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.4284088754
Short name T688
Test name
Test status
Simulation time 7448785545 ps
CPU time 138.89 seconds
Started Mar 24 01:26:06 PM PDT 24
Finished Mar 24 01:28:26 PM PDT 24
Peak memory 233128 kb
Host smart-78cc524f-dac4-4cf3-8462-598f855663a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284088754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.4284088754 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.770484782
Short name T124
Test name
Test status
Simulation time 36937554298 ps
CPU time 205.92 seconds
Started Mar 24 01:26:04 PM PDT 24
Finished Mar 24 01:29:31 PM PDT 24
Peak memory 225032 kb
Host smart-ed8ca5a6-5ec8-4f7b-8097-1b019392f649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770484782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.770484782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2466110336
Short name T741
Test name
Test status
Simulation time 7175329955 ps
CPU time 44.89 seconds
Started Mar 24 01:26:11 PM PDT 24
Finished Mar 24 01:26:57 PM PDT 24
Peak memory 224396 kb
Host smart-6d9c516e-1bde-4c0a-bb6a-9dfef6d3ff17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2466110336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2466110336 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.512530377
Short name T705
Test name
Test status
Simulation time 3003237363 ps
CPU time 41.98 seconds
Started Mar 24 01:26:11 PM PDT 24
Finished Mar 24 01:26:53 PM PDT 24
Peak memory 224368 kb
Host smart-9409253f-58bb-422c-a768-7755817ca8a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=512530377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.512530377 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.326764103
Short name T127
Test name
Test status
Simulation time 4753358389 ps
CPU time 37.79 seconds
Started Mar 24 01:26:10 PM PDT 24
Finished Mar 24 01:26:48 PM PDT 24
Peak memory 224496 kb
Host smart-7003e2fa-3d4d-4d9a-9468-2dc9f5d1f5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326764103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.326764103 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.1777919693
Short name T119
Test name
Test status
Simulation time 20284132357 ps
CPU time 340.84 seconds
Started Mar 24 01:26:09 PM PDT 24
Finished Mar 24 01:31:50 PM PDT 24
Peak memory 245144 kb
Host smart-0b9466c0-af0b-494d-bc89-d5e3a27f884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777919693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1777919693 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.1805236635
Short name T698
Test name
Test status
Simulation time 2906190216 ps
CPU time 82.96 seconds
Started Mar 24 01:26:08 PM PDT 24
Finished Mar 24 01:27:32 PM PDT 24
Peak memory 240928 kb
Host smart-e2dd11cb-86d4-482d-bd9a-4d335995c4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805236635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1805236635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.3221114642
Short name T1028
Test name
Test status
Simulation time 877747031 ps
CPU time 4.53 seconds
Started Mar 24 01:26:11 PM PDT 24
Finished Mar 24 01:26:15 PM PDT 24
Peak memory 207868 kb
Host smart-77b04c35-c579-4ca0-9ba9-8c0ce1792fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221114642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3221114642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.3483159989
Short name T102
Test name
Test status
Simulation time 32296493 ps
CPU time 1.26 seconds
Started Mar 24 01:26:06 PM PDT 24
Finished Mar 24 01:26:08 PM PDT 24
Peak memory 216120 kb
Host smart-dab5e7ce-eb59-4bee-ae92-7bc9134f0b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483159989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3483159989 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.4078068181
Short name T567
Test name
Test status
Simulation time 286404187516 ps
CPU time 1982.34 seconds
Started Mar 24 01:26:06 PM PDT 24
Finished Mar 24 01:59:09 PM PDT 24
Peak memory 417332 kb
Host smart-167452eb-90a5-42fc-9536-b39715369604
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078068181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.4078068181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.2737863916
Short name T938
Test name
Test status
Simulation time 52526291338 ps
CPU time 181.18 seconds
Started Mar 24 01:26:07 PM PDT 24
Finished Mar 24 01:29:09 PM PDT 24
Peak memory 240880 kb
Host smart-675eefb8-7bd3-45a7-8db7-533db8178b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737863916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2737863916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.86717412
Short name T996
Test name
Test status
Simulation time 77816964277 ps
CPU time 427.57 seconds
Started Mar 24 01:26:07 PM PDT 24
Finished Mar 24 01:33:15 PM PDT 24
Peak memory 247784 kb
Host smart-6b1641d4-8c62-45d4-8cd2-d77eea700805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86717412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.86717412 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3606891465
Short name T337
Test name
Test status
Simulation time 480959486 ps
CPU time 24.16 seconds
Started Mar 24 01:25:57 PM PDT 24
Finished Mar 24 01:26:21 PM PDT 24
Peak memory 219384 kb
Host smart-3b84a8e8-9830-4649-a4c8-2edeb33d1cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606891465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3606891465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.2687248612
Short name T937
Test name
Test status
Simulation time 33134362742 ps
CPU time 917.8 seconds
Started Mar 24 01:26:07 PM PDT 24
Finished Mar 24 01:41:25 PM PDT 24
Peak memory 337508 kb
Host smart-ed6f5ec8-8247-41d9-a229-54ac29856b44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2687248612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2687248612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.3679899627
Short name T827
Test name
Test status
Simulation time 67862124 ps
CPU time 4.35 seconds
Started Mar 24 01:26:05 PM PDT 24
Finished Mar 24 01:26:10 PM PDT 24
Peak memory 216136 kb
Host smart-cff16001-3967-4aa8-914b-12659b0a0a16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679899627 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.3679899627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2833389196
Short name T556
Test name
Test status
Simulation time 348854656 ps
CPU time 3.97 seconds
Started Mar 24 01:26:07 PM PDT 24
Finished Mar 24 01:26:12 PM PDT 24
Peak memory 216276 kb
Host smart-b3563bce-a171-4ae1-a5e9-e0063e4f6d87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833389196 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2833389196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.2373436152
Short name T633
Test name
Test status
Simulation time 64850594454 ps
CPU time 1726.72 seconds
Started Mar 24 01:26:08 PM PDT 24
Finished Mar 24 01:54:55 PM PDT 24
Peak memory 392720 kb
Host smart-73a78eb6-16e5-45b5-8f26-cbd367635aa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2373436152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.2373436152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.614209850
Short name T786
Test name
Test status
Simulation time 245268305653 ps
CPU time 1739.21 seconds
Started Mar 24 01:26:08 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 375464 kb
Host smart-b59e884d-eace-48dd-8c87-8d5b2d290995
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=614209850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.614209850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.2337865287
Short name T886
Test name
Test status
Simulation time 47316521784 ps
CPU time 1320.77 seconds
Started Mar 24 01:26:06 PM PDT 24
Finished Mar 24 01:48:08 PM PDT 24
Peak memory 337956 kb
Host smart-57f0fca9-7dcf-44c1-9438-dfd1a7ade10a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2337865287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2337865287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.2543289581
Short name T640
Test name
Test status
Simulation time 10287114467 ps
CPU time 778.49 seconds
Started Mar 24 01:26:05 PM PDT 24
Finished Mar 24 01:39:03 PM PDT 24
Peak memory 292480 kb
Host smart-37d121f8-1d2f-4b5d-9c19-5670df8db09a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2543289581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.2543289581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.3656753125
Short name T469
Test name
Test status
Simulation time 267388913711 ps
CPU time 3980.03 seconds
Started Mar 24 01:26:06 PM PDT 24
Finished Mar 24 02:32:27 PM PDT 24
Peak memory 650504 kb
Host smart-fa48d7ea-efc8-4da6-b779-2066225fde7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3656753125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.3656753125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.4094933555
Short name T1001
Test name
Test status
Simulation time 43485965051 ps
CPU time 3485.52 seconds
Started Mar 24 01:26:07 PM PDT 24
Finished Mar 24 02:24:13 PM PDT 24
Peak memory 557124 kb
Host smart-82e3bfac-a99a-450f-8370-c1bee1e91503
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4094933555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.4094933555 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.126995491
Short name T778
Test name
Test status
Simulation time 20496620 ps
CPU time 0.8 seconds
Started Mar 24 01:26:18 PM PDT 24
Finished Mar 24 01:26:19 PM PDT 24
Peak memory 205740 kb
Host smart-a1e58c23-57a4-44b0-bc96-2d949e8f6215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126995491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.126995491 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.2050287184
Short name T709
Test name
Test status
Simulation time 32801786829 ps
CPU time 258.99 seconds
Started Mar 24 01:26:12 PM PDT 24
Finished Mar 24 01:30:31 PM PDT 24
Peak memory 243564 kb
Host smart-034ec23a-46d4-4264-803d-31fb3073eb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050287184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2050287184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.3417027525
Short name T458
Test name
Test status
Simulation time 686938449 ps
CPU time 28.46 seconds
Started Mar 24 01:26:12 PM PDT 24
Finished Mar 24 01:26:41 PM PDT 24
Peak memory 230468 kb
Host smart-d77b981e-3f23-4ffb-86db-5a05f5e4be37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417027525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.3417027525 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.1140429191
Short name T1078
Test name
Test status
Simulation time 36566526219 ps
CPU time 538.82 seconds
Started Mar 24 01:26:12 PM PDT 24
Finished Mar 24 01:35:11 PM PDT 24
Peak memory 231844 kb
Host smart-ba2c6a3c-aa10-47a6-b8bc-ee7feac79df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140429191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1140429191 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.1322201141
Short name T589
Test name
Test status
Simulation time 827139953 ps
CPU time 14.36 seconds
Started Mar 24 01:26:17 PM PDT 24
Finished Mar 24 01:26:31 PM PDT 24
Peak memory 223980 kb
Host smart-76ccfaf5-848c-4060-b086-3bbec65fe535
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1322201141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1322201141 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.553316621
Short name T1007
Test name
Test status
Simulation time 613327565 ps
CPU time 37.96 seconds
Started Mar 24 01:26:16 PM PDT 24
Finished Mar 24 01:26:54 PM PDT 24
Peak memory 224248 kb
Host smart-8c361699-78b7-4ba5-8bce-97a30c71d895
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=553316621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.553316621 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.2527560681
Short name T656
Test name
Test status
Simulation time 8750883803 ps
CPU time 19.58 seconds
Started Mar 24 01:26:16 PM PDT 24
Finished Mar 24 01:26:36 PM PDT 24
Peak memory 216324 kb
Host smart-a9e62fd5-6735-4645-8ea7-7e6c90a1ba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527560681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2527560681 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.3331117814
Short name T646
Test name
Test status
Simulation time 10463211700 ps
CPU time 181.76 seconds
Started Mar 24 01:26:11 PM PDT 24
Finished Mar 24 01:29:13 PM PDT 24
Peak memory 237928 kb
Host smart-ddeb514b-be74-4a24-9bbb-8c7544ed37d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331117814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3331117814 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.1954029086
Short name T1077
Test name
Test status
Simulation time 79203605927 ps
CPU time 235.67 seconds
Started Mar 24 01:26:16 PM PDT 24
Finished Mar 24 01:30:12 PM PDT 24
Peak memory 240884 kb
Host smart-201663d5-491f-4e1a-9bec-6fd6a3fcf151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954029086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1954029086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.4055351152
Short name T488
Test name
Test status
Simulation time 3906720951 ps
CPU time 5.12 seconds
Started Mar 24 01:26:17 PM PDT 24
Finished Mar 24 01:26:22 PM PDT 24
Peak memory 207900 kb
Host smart-83265e31-ae0d-41f5-8dbe-d123bbead86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055351152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.4055351152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.3656494013
Short name T784
Test name
Test status
Simulation time 54299960 ps
CPU time 1.39 seconds
Started Mar 24 01:26:17 PM PDT 24
Finished Mar 24 01:26:19 PM PDT 24
Peak memory 216124 kb
Host smart-69ba8ff3-6bf3-4d05-adb8-bcff6046acf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656494013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3656494013 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.3116981062
Short name T553
Test name
Test status
Simulation time 13586958714 ps
CPU time 1236.57 seconds
Started Mar 24 01:26:14 PM PDT 24
Finished Mar 24 01:46:51 PM PDT 24
Peak memory 349388 kb
Host smart-3fd7e45c-10d3-4f19-baf7-cebe16902b16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116981062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.3116981062 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.1697113297
Short name T676
Test name
Test status
Simulation time 1562382942 ps
CPU time 34.23 seconds
Started Mar 24 01:26:16 PM PDT 24
Finished Mar 24 01:26:50 PM PDT 24
Peak memory 224604 kb
Host smart-df6ea7b1-ca49-4321-9313-0faeae42f460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697113297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1697113297 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.537837675
Short name T907
Test name
Test status
Simulation time 21302421754 ps
CPU time 401.93 seconds
Started Mar 24 01:26:16 PM PDT 24
Finished Mar 24 01:32:58 PM PDT 24
Peak memory 247808 kb
Host smart-db43fa24-fabe-469a-9226-54eea1938d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537837675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.537837675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.1472625067
Short name T76
Test name
Test status
Simulation time 6473629980 ps
CPU time 25.79 seconds
Started Mar 24 01:26:07 PM PDT 24
Finished Mar 24 01:26:33 PM PDT 24
Peak memory 217440 kb
Host smart-909d2e69-0149-438f-999e-a74f09784483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472625067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1472625067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.1931724372
Short name T655
Test name
Test status
Simulation time 2673855218 ps
CPU time 78.66 seconds
Started Mar 24 01:26:17 PM PDT 24
Finished Mar 24 01:27:36 PM PDT 24
Peak memory 240976 kb
Host smart-0d12c04f-7fa9-4cbf-8ef1-c803d0136308
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1931724372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1931724372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.2955786387
Short name T969
Test name
Test status
Simulation time 177655757 ps
CPU time 4.64 seconds
Started Mar 24 01:26:12 PM PDT 24
Finished Mar 24 01:26:17 PM PDT 24
Peak memory 216260 kb
Host smart-015761f6-3188-469d-9398-5b241115c123
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955786387 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.2955786387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3464412787
Short name T239
Test name
Test status
Simulation time 169542359 ps
CPU time 4.42 seconds
Started Mar 24 01:26:16 PM PDT 24
Finished Mar 24 01:26:21 PM PDT 24
Peak memory 209344 kb
Host smart-f623f9b1-2694-428a-9c01-90c6706acab8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464412787 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3464412787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1022991679
Short name T785
Test name
Test status
Simulation time 67645854942 ps
CPU time 1890.22 seconds
Started Mar 24 01:26:11 PM PDT 24
Finished Mar 24 01:57:42 PM PDT 24
Peak memory 388184 kb
Host smart-ec8a5d9b-5b76-40f1-9168-2d6bc7a74f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1022991679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1022991679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.2304314871
Short name T14
Test name
Test status
Simulation time 72819612450 ps
CPU time 1418.68 seconds
Started Mar 24 01:26:12 PM PDT 24
Finished Mar 24 01:49:52 PM PDT 24
Peak memory 369176 kb
Host smart-c5a1fab5-13d8-4aab-b27d-8827f24041ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2304314871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.2304314871 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.3113957866
Short name T404
Test name
Test status
Simulation time 71439143468 ps
CPU time 1417.77 seconds
Started Mar 24 01:26:16 PM PDT 24
Finished Mar 24 01:49:54 PM PDT 24
Peak memory 329200 kb
Host smart-76063360-d617-4989-9359-48445f5b7d98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3113957866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3113957866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.857225121
Short name T760
Test name
Test status
Simulation time 189439186870 ps
CPU time 918.61 seconds
Started Mar 24 01:26:13 PM PDT 24
Finished Mar 24 01:41:31 PM PDT 24
Peak memory 292212 kb
Host smart-40b731d4-b6a5-49e3-9bb8-641a8dd31edc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=857225121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.857225121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.4264728107
Short name T915
Test name
Test status
Simulation time 208967285417 ps
CPU time 4157.96 seconds
Started Mar 24 01:26:12 PM PDT 24
Finished Mar 24 02:35:30 PM PDT 24
Peak memory 637180 kb
Host smart-f5f1a131-3a5f-4a66-9f8d-bb4843d74685
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4264728107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.4264728107 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.291636116
Short name T1042
Test name
Test status
Simulation time 93753694497 ps
CPU time 3653.14 seconds
Started Mar 24 01:26:11 PM PDT 24
Finished Mar 24 02:27:05 PM PDT 24
Peak memory 561096 kb
Host smart-f9daacb2-14d2-4302-9cbd-0c40faba4713
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=291636116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.291636116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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