Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100330929	1			T1	565322		T2	5898		T3	20953
all_values[1]	100330929	1			T1	565322		T2	5898		T3	20953
all_values[2]	100330929	1			T1	565322		T2	5898		T3	20953

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616766

1

T1

3

T2

581

T3

885

auto[1]

300376021

1

T1

169596

T2

17113

T3

61974

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299452404

1

T1

168545

T2

17505

T3

62178

auto[1]

1540383

1

T1

10509

T2

189

T3

681

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	245849	1			T2	465		T3	279		T14	1
all_values[0]	auto[0]	auto[1]	2323	1			T2	6		T3	6		T14	2
all_values[0]	auto[1]	auto[0]	99571619	1			T1	561819		T2	5370		T3	20447
all_values[0]	auto[1]	auto[1]	511138	1			T1	3503		T2	57		T3	221
all_values[1]	auto[0]	auto[0]	179726	1			T2	108		T3	26		T17	219
all_values[1]	auto[0]	auto[1]	1690	1			T2	2		T3	2		T17	1
all_values[1]	auto[1]	auto[0]	99637742	1			T1	561819		T2	5727		T3	20700
all_values[1]	auto[1]	auto[1]	511771	1			T1	3503		T2	61		T3	225
all_values[2]	auto[0]	auto[0]	185602	1			T1	2		T3	562		T17	466
all_values[2]	auto[0]	auto[1]	1576	1			T1	1		T3	10		T17	3
all_values[2]	auto[1]	auto[0]	99631866	1			T1	561817		T2	5835		T3	20164
all_values[2]	auto[1]	auto[1]	511885	1			T1	3502		T2	63		T3	217