Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100330929	1			T1	565322		T2	5898		T3	20953
all_pins[1]	100330929	1			T1	565322		T2	5898		T3	20953
all_pins[2]	100330929	1			T1	565322		T2	5898		T3	20953

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300127225	1			T1	169246		T2	17196		T3	62638
values[0x1]	865562	1			T1	3503		T2	498		T3	221
transitions[0x0=>0x1]	863318	1			T1	3503		T2	498		T3	221
transitions[0x1=>0x0]	863351	1			T1	3503		T2	498		T3	221

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99819791	1			T1	561819		T2	5841		T3	20732
all_pins[0]	values[0x1]	511138	1			T1	3503		T2	57		T3	221
all_pins[0]	transitions[0x0=>0x1]	511125	1			T1	3503		T2	57		T3	221
all_pins[0]	transitions[0x1=>0x0]	55	1			T46	2		T190	4		T191	2
all_pins[1]	values[0x0]	100330861	1			T1	565322		T2	5898		T3	20953
all_pins[1]	values[0x1]	68	1			T46	2		T190	4		T191	2
all_pins[1]	transitions[0x0=>0x1]	56	1			T46	2		T190	4		T191	2
all_pins[1]	transitions[0x1=>0x0]	354344	1			T2	441		T31	675		T26	1525
all_pins[2]	values[0x0]	99976573	1			T1	565322		T2	5457		T3	20953
all_pins[2]	values[0x1]	354356	1			T2	441		T31	675		T26	1525
all_pins[2]	transitions[0x0=>0x1]	352137	1			T2	441		T31	675		T26	1511
all_pins[2]	transitions[0x1=>0x0]	508952	1			T1	3503		T2	57		T3	221