Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T124 7 T125 4 T126 4
all_values[1] 272 1 T124 7 T125 4 T126 4
all_values[2] 272 1 T124 7 T125 4 T126 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 453 1 T124 14 T125 7 T126 5
auto[1] 363 1 T124 7 T125 5 T126 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357 1 T124 9 T125 4 T126 9
auto[1] 459 1 T124 12 T125 8 T126 3


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 460 1 T124 10 T125 6 T126 9
auto[1] 356 1 T124 11 T125 6 T126 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 65 1 T124 3 T125 1 T126 1
all_values[0] auto[0] auto[0] auto[1] 22 1 T176 1 T177 1 T178 1
all_values[0] auto[0] auto[1] auto[0] 40 1 T126 3 T155 1 T179 1
all_values[0] auto[0] auto[1] auto[1] 29 1 T124 1 T180 2 T181 1
all_values[0] auto[1] auto[0] auto[1] 68 1 T124 2 T125 3 T177 1
all_values[0] auto[1] auto[1] auto[1] 48 1 T124 1 T176 2 T177 1
all_values[1] auto[0] auto[0] auto[0] 83 1 T124 3 T125 2 T126 2
all_values[1] auto[0] auto[1] auto[0] 68 1 T124 1 T125 1 T176 2
all_values[1] auto[1] auto[0] auto[1] 70 1 T124 1 T125 1 T126 1
all_values[1] auto[1] auto[1] auto[1] 51 1 T124 2 T126 1 T176 1
all_values[2] auto[0] auto[0] auto[0] 56 1 T124 1 T126 1 T176 1
all_values[2] auto[0] auto[0] auto[1] 27 1 T155 1 T179 1 T182 1
all_values[2] auto[0] auto[1] auto[0] 45 1 T124 1 T126 2 T176 1
all_values[2] auto[0] auto[1] auto[1] 25 1 T125 2 T155 1 T178 1
all_values[2] auto[1] auto[0] auto[1] 62 1 T124 4 T176 1 T155 2
all_values[2] auto[1] auto[1] auto[1] 57 1 T124 1 T125 2 T126 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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