Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101058125	1			T1	3576		T2	47761		T3	6485
all_values[1]	101058125	1			T1	3576		T2	47761		T3	6485
all_values[2]	101058125	1			T1	3576		T2	47761		T3	6485

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

509762

1

T1

188

T2

4719

T3

3

auto[1]

302664613

1

T1

10540

T2

138564

T3

19452

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301630638

1

T1

10611

T2

143178

T3

19263

auto[1]

1543737

1

T1

117

T2

105

T3

192

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	150922	1			T2	1711		T15	68		T16	5
all_values[0]	auto[0]	auto[1]	2219	1			T2	2		T15	8		T16	6
all_values[0]	auto[1]	auto[0]	100392624	1			T1	3537		T2	46015		T3	6421
all_values[0]	auto[1]	auto[1]	512360	1			T1	39		T2	33		T3	64
all_values[1]	auto[0]	auto[0]	169464	1			T1	185		T3	1		T12	2
all_values[1]	auto[0]	auto[1]	1690	1			T1	3		T12	1		T15	1
all_values[1]	auto[1]	auto[0]	100374082	1			T1	3352		T2	47726		T3	6420
all_values[1]	auto[1]	auto[1]	512889	1			T1	36		T2	35		T3	64
all_values[2]	auto[0]	auto[0]	183863	1			T2	3003		T3	2		T12	2
all_values[2]	auto[0]	auto[1]	1604	1			T2	3		T12	1		T15	7
all_values[2]	auto[1]	auto[0]	100359683	1			T1	3537		T2	44723		T3	6419
all_values[2]	auto[1]	auto[1]	512975	1			T1	39		T2	32		T3	64