Unified Coverage Report :: Group :: kmac_env_pkg::config_unmasked_cg

Group : kmac_env_pkg::config_unmasked_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::config_unmasked_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	4	0	4	100.00

Variables for Group kmac_env_pkg::config_unmasked_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
key_len	5	0	5	100.00	100	1	1	0
kmac_en	2	0	2	100.00	100	1	1	2
mode	3	0	3	100.00	100	1	1	0
msg_endian	2	0	2	100.00	100	1	1	2
sideload	2	0	2	100.00	100	1	1	2
state_endian	2	0	2	100.00	100	1	1	2
strength	5	0	5	100.00	100	1	1	0
xof_en	2	0	2	100.00	100	1	1	2

Crosses for Group kmac_env_pkg::config_unmasked_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
kmac_cross	1	0	1	100.00	100	1	1	0
cshake_cross	1	0	1	100.00	100	1	1	0
shake_cross	1	0	1	100.00	100	1	1	0
sha3_cross	1	0	1	100.00	100	1	1	0

Summary for Variable key_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for key_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Key128]	66712	1			T1	4		T2	4		T3	11
auto[Key192]	66494	1			T1	4		T2	6		T3	10
auto[Key256]	82682	1			T1	31		T2	5		T3	27
auto[Key384]	66285	1			T1	7		T2	5		T3	4
auto[Key512]	66841	1			T1	5		T2	5		T3	9

---

Summary for Variable kmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313642

1

T1

32

T2

8

T3

32

auto[1]

35372

1

T1

19

T2

17

T3

29

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	67549	1			T3	2		T12	246		T14	4
auto[Shake]	242662	1			T1	18		T2	8		T3	21
auto[CShake]	38803	1			T1	33		T2	17		T3	38

---

Summary for Variable msg_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msg_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174936

1

T1

19

T2

14

T3

29

auto[1]

174078

1

T1

32

T2

11

T3

32

---

Summary for Variable sideload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sideload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338330

1

T1

38

T2

25

T3

49

auto[1]

10684

1

T1

13

T3

12

T13

5

---

Summary for Variable state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for state_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174802

1

T1

26

T2

14

T3

26

auto[1]

174212

1

T1

25

T2

11

T3

35

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	140534	1			T1	20		T2	10		T3	31
auto[L224]	19872	1			T3	1		T14	1		T15	5
auto[L256]	160017	1			T1	31		T2	15		T3	29
auto[L384]	15886	1			T14	1		T15	3		T42	310
auto[L512]	12705	1			T12	246		T14	2		T15	1

---

Summary for Variable xof_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for xof_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

328989

1

T1

46

T2

15

T3

54

auto[1]

20025

1

T1

5

T2

10

T3

7

---

Summary for Cross kmac_cross

Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for kmac_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

35372

1

T1

19

T2

17

T3

29

---

Summary for Cross cshake_cross

Samples crossed: mode strength msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for cshake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

38803

1

T1

33

T2

17

T3

38

---

Summary for Cross shake_cross

Samples crossed: mode strength msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for shake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

242662

1

T1

18

T2

8

T3

21

---

Summary for Cross sha3_cross

Samples crossed: mode strength msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for sha3_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

67549

1

T3

2

T12

246

T14

4