Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
374430 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
122 |
auto[1] |
325724 |
1 |
|
|
T1 |
100 |
|
T2 |
48 |
|
T12 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176033 |
1 |
|
|
T1 |
20 |
|
T2 |
9 |
|
T3 |
30 |
lower_val |
173390 |
1 |
|
|
T1 |
33 |
|
T2 |
10 |
|
T3 |
19 |
zero_val |
1913 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
350016 |
1 |
|
|
T1 |
38 |
|
T2 |
28 |
|
T3 |
66 |
lower_val |
350130 |
1 |
|
|
T1 |
64 |
|
T2 |
22 |
|
T3 |
56 |
zero_val |
8 |
1 |
|
|
T70 |
2 |
|
T144 |
2 |
|
T145 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46545 |
1 |
|
|
T3 |
18 |
|
T15 |
79 |
|
T16 |
79 |
higher_val |
higher_val |
auto[1] |
41214 |
1 |
|
|
T1 |
8 |
|
T2 |
4 |
|
T12 |
70 |
higher_val |
lower_val |
auto[0] |
47130 |
1 |
|
|
T3 |
12 |
|
T15 |
78 |
|
T16 |
99 |
higher_val |
lower_val |
auto[1] |
41143 |
1 |
|
|
T1 |
12 |
|
T2 |
5 |
|
T12 |
67 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T146 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
46331 |
1 |
|
|
T3 |
6 |
|
T14 |
1 |
|
T15 |
85 |
lower_val |
higher_val |
auto[1] |
40497 |
1 |
|
|
T1 |
10 |
|
T2 |
5 |
|
T12 |
48 |
lower_val |
lower_val |
auto[0] |
46301 |
1 |
|
|
T3 |
13 |
|
T15 |
83 |
|
T16 |
112 |
lower_val |
lower_val |
auto[1] |
40259 |
1 |
|
|
T1 |
23 |
|
T2 |
5 |
|
T12 |
64 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T144 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T146 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
704 |
1 |
|
|
T13 |
1 |
|
T14 |
1 |
|
T15 |
3 |
zero_val |
higher_val |
auto[1] |
263 |
1 |
|
|
T15 |
1 |
|
T79 |
2 |
|
T36 |
1 |
zero_val |
lower_val |
auto[0] |
703 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
243 |
1 |
|
|
T79 |
2 |
|
T147 |
1 |
|
T27 |
2 |