Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9045	1			T2	10		T14	21		T15	38
len_5001_7500	14659	1			T2	11		T12	33		T14	49
len_2501_5000	9334	1			T2	1		T12	34		T14	13
len_1025_2500	5434	1			T2	1		T12	20		T14	6
len_769_1024	6405	1			T1	3		T3	13		T12	4
len_513_768	6819	1			T1	8		T3	8		T12	3
len_257_512	21432	1			T1	8		T3	10		T12	4
len_0_256	259351	1			T1	7		T2	2		T3	11
len_keccak_block_sizes[72]	729	1			T12	2		T16	2		T42	2
len_keccak_block_sizes[104]	622	1			T16	2		T42	2		T79	3
len_keccak_block_sizes[136]	521	1			T16	2		T79	3		T81	3
len_keccak_block_sizes[144]	425	1			T16	2		T79	3		T81	3
len_keccak_block_sizes[168]	317	1			T79	3		T81	3		T69	3
len_1	775	1			T12	2		T15	3		T16	2
len_0	1250	1			T2	1		T12	2		T14	4