Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101058125	1			T1	3576		T2	47761		T3	6485
all_pins[1]	101058125	1			T1	3576		T2	47761		T3	6485
all_pins[2]	101058125	1			T1	3576		T2	47761		T3	6485

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	302395423	1			T1	10689		T2	143250		T3	19391
values[0x1]	778952	1			T1	39		T2	33		T3	64
transitions[0x0=>0x1]	777292	1			T1	39		T2	33		T3	64
transitions[0x1=>0x0]	777314	1			T1	39		T2	33		T3	64

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100545765	1			T1	3537		T2	47728		T3	6421
all_pins[0]	values[0x1]	512360	1			T1	39		T2	33		T3	64
all_pins[0]	transitions[0x0=>0x1]	512343	1			T1	39		T2	33		T3	64
all_pins[0]	transitions[0x1=>0x0]	79	1			T27	3		T111	3		T159	4
all_pins[1]	values[0x0]	101058029	1			T1	3576		T2	47761		T3	6485
all_pins[1]	values[0x1]	96	1			T27	3		T111	3		T159	4
all_pins[1]	transitions[0x0=>0x1]	84	1			T27	3		T111	3		T159	4
all_pins[1]	transitions[0x1=>0x0]	266484	1			T15	2046		T18	268		T24	1454
all_pins[2]	values[0x0]	100791629	1			T1	3576		T2	47761		T3	6485
all_pins[2]	values[0x1]	266496	1			T15	2046		T18	268		T24	1454
all_pins[2]	transitions[0x0=>0x1]	264865	1			T15	2031		T18	267		T24	1443
all_pins[2]	transitions[0x1=>0x0]	510751	1			T1	39		T2	33		T3	64