Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.60 96.18 92.13 100.00 90.91 94.52 98.84 96.60


Total test records in report: 1245
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T1059 /workspace/coverage/default/4.kmac_mubi.3879270917 Mar 28 01:50:46 PM PDT 24 Mar 28 01:53:10 PM PDT 24 2368889781 ps
T1060 /workspace/coverage/default/22.kmac_entropy_refresh.3946700411 Mar 28 01:54:32 PM PDT 24 Mar 28 01:56:52 PM PDT 24 35434117322 ps
T1061 /workspace/coverage/default/15.kmac_test_vectors_shake_128.1975200255 Mar 28 01:51:59 PM PDT 24 Mar 28 03:16:01 PM PDT 24 245509094401 ps
T1062 /workspace/coverage/default/42.kmac_test_vectors_sha3_512.114132484 Mar 28 02:07:32 PM PDT 24 Mar 28 02:24:59 PM PDT 24 36224207370 ps
T1063 /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.2211568366 Mar 28 01:50:55 PM PDT 24 Mar 28 01:50:59 PM PDT 24 990810719 ps
T1064 /workspace/coverage/default/39.kmac_key_error.2298891354 Mar 28 02:05:19 PM PDT 24 Mar 28 02:05:22 PM PDT 24 192599388 ps
T1065 /workspace/coverage/default/24.kmac_test_vectors_sha3_224.4290655992 Mar 28 01:55:28 PM PDT 24 Mar 28 02:28:16 PM PDT 24 338904972833 ps
T1066 /workspace/coverage/default/37.kmac_burst_write.3834518670 Mar 28 02:03:22 PM PDT 24 Mar 28 02:15:20 PM PDT 24 50022955260 ps
T1067 /workspace/coverage/default/15.kmac_long_msg_and_output.1487229342 Mar 28 01:51:57 PM PDT 24 Mar 28 02:00:05 PM PDT 24 37067617157 ps
T1068 /workspace/coverage/default/2.kmac_burst_write.3695459824 Mar 28 01:50:25 PM PDT 24 Mar 28 01:58:45 PM PDT 24 16510210737 ps
T1069 /workspace/coverage/default/41.kmac_stress_all.1227901249 Mar 28 02:07:31 PM PDT 24 Mar 28 02:08:41 PM PDT 24 5080230048 ps
T1070 /workspace/coverage/default/20.kmac_key_error.2423055410 Mar 28 01:53:52 PM PDT 24 Mar 28 01:53:53 PM PDT 24 181269514 ps
T1071 /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.716466747 Mar 28 01:58:27 PM PDT 24 Mar 28 01:58:33 PM PDT 24 742741993 ps
T1072 /workspace/coverage/default/18.kmac_entropy_refresh.4287485157 Mar 28 01:53:15 PM PDT 24 Mar 28 01:58:09 PM PDT 24 5721890717 ps
T1073 /workspace/coverage/default/22.kmac_test_vectors_sha3_224.2920851578 Mar 28 01:54:30 PM PDT 24 Mar 28 02:30:02 PM PDT 24 353005988098 ps
T1074 /workspace/coverage/default/39.kmac_test_vectors_kmac.3048767486 Mar 28 02:05:19 PM PDT 24 Mar 28 02:05:25 PM PDT 24 401721423 ps
T1075 /workspace/coverage/default/44.kmac_stress_all.844363957 Mar 28 02:10:01 PM PDT 24 Mar 28 02:11:01 PM PDT 24 2754064826 ps
T1076 /workspace/coverage/default/39.kmac_test_vectors_sha3_512.768238648 Mar 28 02:05:02 PM PDT 24 Mar 28 02:20:11 PM PDT 24 135158565775 ps
T1077 /workspace/coverage/default/31.kmac_sideload.2649537387 Mar 28 01:58:48 PM PDT 24 Mar 28 01:58:57 PM PDT 24 480329603 ps
T1078 /workspace/coverage/default/2.kmac_key_error.2922654542 Mar 28 01:50:26 PM PDT 24 Mar 28 01:50:31 PM PDT 24 1033452183 ps
T1079 /workspace/coverage/default/15.kmac_sideload.3424210225 Mar 28 01:51:57 PM PDT 24 Mar 28 01:57:37 PM PDT 24 4686308815 ps
T1080 /workspace/coverage/default/30.kmac_burst_write.474143595 Mar 28 01:58:06 PM PDT 24 Mar 28 01:58:57 PM PDT 24 3269293721 ps
T1081 /workspace/coverage/default/6.kmac_app.3177736353 Mar 28 01:50:55 PM PDT 24 Mar 28 01:53:21 PM PDT 24 58098872769 ps
T1082 /workspace/coverage/default/33.kmac_stress_all.3379430430 Mar 28 02:00:24 PM PDT 24 Mar 28 02:29:21 PM PDT 24 153812592099 ps
T1083 /workspace/coverage/default/49.kmac_long_msg_and_output.252353659 Mar 28 02:15:23 PM PDT 24 Mar 28 02:52:58 PM PDT 24 26495394415 ps
T1084 /workspace/coverage/default/8.kmac_sideload.3802314240 Mar 28 01:51:06 PM PDT 24 Mar 28 01:56:44 PM PDT 24 4574381902 ps
T1085 /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.491284286 Mar 28 01:51:19 PM PDT 24 Mar 28 01:51:23 PM PDT 24 1484136275 ps
T1086 /workspace/coverage/default/36.kmac_test_vectors_sha3_384.486799848 Mar 28 02:02:21 PM PDT 24 Mar 28 02:22:25 PM PDT 24 56433821239 ps
T1087 /workspace/coverage/default/47.kmac_test_vectors_sha3_384.782309897 Mar 28 02:13:05 PM PDT 24 Mar 28 02:32:33 PM PDT 24 28155345287 ps
T1088 /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.779042707 Mar 28 01:50:10 PM PDT 24 Mar 28 01:50:15 PM PDT 24 69130762 ps
T176 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2124740869 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 114161603 ps
T177 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3044815357 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 28780800 ps
T107 /workspace/coverage/cover_reg_top/33.kmac_intr_test.4100148496 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:51 PM PDT 24 36859207 ps
T1089 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3451487778 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:52 PM PDT 24 75443069 ps
T130 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4220455460 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 290445580 ps
T1090 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3147154825 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 469159318 ps
T104 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2687037865 Mar 28 12:36:20 PM PDT 24 Mar 28 12:36:23 PM PDT 24 68085359 ps
T131 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2012042369 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:51 PM PDT 24 71053592 ps
T108 /workspace/coverage/cover_reg_top/8.kmac_intr_test.382772244 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:46 PM PDT 24 24947487 ps
T105 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.741645134 Mar 28 12:36:42 PM PDT 24 Mar 28 12:36:47 PM PDT 24 1264939063 ps
T88 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.759260574 Mar 28 12:36:24 PM PDT 24 Mar 28 12:36:25 PM PDT 24 148722260 ps
T109 /workspace/coverage/cover_reg_top/20.kmac_intr_test.549077817 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:54 PM PDT 24 14765915 ps
T1091 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1675029034 Mar 28 12:36:54 PM PDT 24 Mar 28 12:36:55 PM PDT 24 50955105 ps
T1092 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2039828812 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:47 PM PDT 24 58294658 ps
T1093 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.966293732 Mar 28 12:36:33 PM PDT 24 Mar 28 12:36:34 PM PDT 24 13073668 ps
T132 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1646351262 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:53 PM PDT 24 52272984 ps
T1094 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2026825571 Mar 28 12:36:23 PM PDT 24 Mar 28 12:36:25 PM PDT 24 36834338 ps
T138 /workspace/coverage/cover_reg_top/38.kmac_intr_test.844186425 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 45869663 ps
T124 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2346462997 Mar 28 12:36:23 PM PDT 24 Mar 28 12:36:25 PM PDT 24 27378436 ps
T1095 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3470047728 Mar 28 12:36:52 PM PDT 24 Mar 28 12:37:14 PM PDT 24 973248664 ps
T1096 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2828063627 Mar 28 12:36:40 PM PDT 24 Mar 28 12:36:42 PM PDT 24 19470435 ps
T156 /workspace/coverage/cover_reg_top/43.kmac_intr_test.2857774839 Mar 28 12:36:55 PM PDT 24 Mar 28 12:36:57 PM PDT 24 21941927 ps
T89 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2638397301 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:56 PM PDT 24 95037564 ps
T133 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1077092703 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:54 PM PDT 24 32301569 ps
T155 /workspace/coverage/cover_reg_top/47.kmac_intr_test.3637733224 Mar 28 12:36:55 PM PDT 24 Mar 28 12:36:57 PM PDT 24 43747025 ps
T139 /workspace/coverage/cover_reg_top/48.kmac_intr_test.2344048797 Mar 28 12:36:52 PM PDT 24 Mar 28 12:37:04 PM PDT 24 15547956 ps
T106 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.258189934 Mar 28 12:36:50 PM PDT 24 Mar 28 12:36:55 PM PDT 24 235408011 ps
T1097 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1106579029 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:52 PM PDT 24 65134294 ps
T134 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.285002704 Mar 28 12:36:15 PM PDT 24 Mar 28 12:36:16 PM PDT 24 50723880 ps
T140 /workspace/coverage/cover_reg_top/6.kmac_intr_test.801049809 Mar 28 12:36:54 PM PDT 24 Mar 28 12:36:55 PM PDT 24 17714028 ps
T157 /workspace/coverage/cover_reg_top/5.kmac_intr_test.3936566883 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:55 PM PDT 24 15285218 ps
T90 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4137810391 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 78446837 ps
T135 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2030246641 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 54078623 ps
T160 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2316232879 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:58 PM PDT 24 159373595 ps
T136 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1355709904 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:52 PM PDT 24 24533834 ps
T1098 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2167779677 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 38632263 ps
T161 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3577114292 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:54 PM PDT 24 234623799 ps
T1099 /workspace/coverage/cover_reg_top/2.kmac_intr_test.42967338 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:48 PM PDT 24 26680500 ps
T1100 /workspace/coverage/cover_reg_top/30.kmac_intr_test.2047433000 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 32394112 ps
T1101 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1043379836 Mar 28 12:36:39 PM PDT 24 Mar 28 12:36:41 PM PDT 24 22120747 ps
T158 /workspace/coverage/cover_reg_top/28.kmac_intr_test.3679654300 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:54 PM PDT 24 21794803 ps
T98 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2532838792 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 45929766 ps
T137 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3933378542 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:56 PM PDT 24 80099736 ps
T142 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1575175474 Mar 28 12:36:32 PM PDT 24 Mar 28 12:36:33 PM PDT 24 23541711 ps
T1102 /workspace/coverage/cover_reg_top/15.kmac_intr_test.1293556404 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 24829232 ps
T1103 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.452998497 Mar 28 12:36:44 PM PDT 24 Mar 28 12:36:47 PM PDT 24 308149184 ps
T1104 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3999170820 Mar 28 12:36:29 PM PDT 24 Mar 28 12:36:35 PM PDT 24 227425749 ps
T1105 /workspace/coverage/cover_reg_top/22.kmac_intr_test.1148389900 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:55 PM PDT 24 94205576 ps
T141 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.4011112480 Mar 28 12:36:43 PM PDT 24 Mar 28 12:36:44 PM PDT 24 89944137 ps
T1106 /workspace/coverage/cover_reg_top/37.kmac_intr_test.2858562956 Mar 28 12:37:00 PM PDT 24 Mar 28 12:37:01 PM PDT 24 31514895 ps
T1107 /workspace/coverage/cover_reg_top/29.kmac_intr_test.3122718134 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:54 PM PDT 24 167622390 ps
T103 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3468195557 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 36060088 ps
T1108 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.4026973132 Mar 28 12:36:24 PM PDT 24 Mar 28 12:36:25 PM PDT 24 61565932 ps
T92 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.511878615 Mar 28 12:36:55 PM PDT 24 Mar 28 12:36:57 PM PDT 24 53074025 ps
T1109 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4209115341 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 123671159 ps
T1110 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1187719374 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:56 PM PDT 24 73629909 ps
T1111 /workspace/coverage/cover_reg_top/7.kmac_intr_test.3056580397 Mar 28 12:36:54 PM PDT 24 Mar 28 12:36:55 PM PDT 24 15196110 ps
T1112 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.2453876676 Mar 28 12:36:19 PM PDT 24 Mar 28 12:36:22 PM PDT 24 298189767 ps
T1113 /workspace/coverage/cover_reg_top/41.kmac_intr_test.4126407252 Mar 28 12:36:56 PM PDT 24 Mar 28 12:36:57 PM PDT 24 14899916 ps
T1114 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.547263116 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:52 PM PDT 24 20567016 ps
T1115 /workspace/coverage/cover_reg_top/25.kmac_intr_test.3590967597 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:53 PM PDT 24 139570399 ps
T143 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2397044557 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:52 PM PDT 24 32552310 ps
T1116 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1754484362 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:54 PM PDT 24 133915783 ps
T1117 /workspace/coverage/cover_reg_top/44.kmac_intr_test.782349017 Mar 28 12:36:55 PM PDT 24 Mar 28 12:36:57 PM PDT 24 14360663 ps
T94 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3471648783 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:47 PM PDT 24 55683631 ps
T1118 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.1211862714 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:54 PM PDT 24 35723382 ps
T1119 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2981110084 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:54 PM PDT 24 72806880 ps
T1120 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.425372574 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:52 PM PDT 24 87722276 ps
T1121 /workspace/coverage/cover_reg_top/32.kmac_intr_test.2857013952 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:51 PM PDT 24 14419377 ps
T125 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2688043147 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:52 PM PDT 24 33522623 ps
T1122 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3525670883 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 28902869 ps
T1123 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.671841796 Mar 28 12:36:50 PM PDT 24 Mar 28 12:36:55 PM PDT 24 55390304 ps
T1124 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3857137699 Mar 28 12:36:44 PM PDT 24 Mar 28 12:36:46 PM PDT 24 37798581 ps
T1125 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3103068731 Mar 28 12:36:54 PM PDT 24 Mar 28 12:37:16 PM PDT 24 6026313663 ps
T1126 /workspace/coverage/cover_reg_top/39.kmac_intr_test.3116192382 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:53 PM PDT 24 28369739 ps
T1127 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2118593646 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 206758755 ps
T1128 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.703636365 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:52 PM PDT 24 202196272 ps
T91 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2357015460 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 44596078 ps
T1129 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3545966932 Mar 28 12:36:33 PM PDT 24 Mar 28 12:36:41 PM PDT 24 722159318 ps
T1130 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1838977305 Mar 28 12:36:43 PM PDT 24 Mar 28 12:36:44 PM PDT 24 15167185 ps
T1131 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2240843632 Mar 28 12:36:30 PM PDT 24 Mar 28 12:36:33 PM PDT 24 219819792 ps
T1132 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3876115084 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:56 PM PDT 24 261799564 ps
T1133 /workspace/coverage/cover_reg_top/24.kmac_intr_test.1921600569 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 59554949 ps
T1134 /workspace/coverage/cover_reg_top/23.kmac_intr_test.2892859693 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:52 PM PDT 24 47172765 ps
T1135 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1524777541 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 62828180 ps
T1136 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3382867569 Mar 28 12:36:40 PM PDT 24 Mar 28 12:36:43 PM PDT 24 196924970 ps
T1137 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.994502232 Mar 28 12:36:52 PM PDT 24 Mar 28 12:37:04 PM PDT 24 56906877 ps
T1138 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.634186117 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:56 PM PDT 24 580045931 ps
T93 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1704831966 Mar 28 12:36:54 PM PDT 24 Mar 28 12:36:56 PM PDT 24 44566666 ps
T1139 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.412473452 Mar 28 12:36:55 PM PDT 24 Mar 28 12:36:58 PM PDT 24 273576058 ps
T1140 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.916333755 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:51 PM PDT 24 42964872 ps
T1141 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2090371779 Mar 28 12:36:24 PM PDT 24 Mar 28 12:36:25 PM PDT 24 142706354 ps
T1142 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.611993665 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:57 PM PDT 24 735410965 ps
T162 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2083642645 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:56 PM PDT 24 266191750 ps
T168 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.887113908 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:55 PM PDT 24 277555893 ps
T169 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1759834931 Mar 28 12:36:43 PM PDT 24 Mar 28 12:36:47 PM PDT 24 211477169 ps
T1143 /workspace/coverage/cover_reg_top/46.kmac_intr_test.757355450 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:55 PM PDT 24 21377326 ps
T95 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2311725955 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:54 PM PDT 24 61081740 ps
T1144 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3994516260 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 97733392 ps
T1145 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.71354555 Mar 28 12:36:22 PM PDT 24 Mar 28 12:36:23 PM PDT 24 49354910 ps
T96 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1484594154 Mar 28 12:36:50 PM PDT 24 Mar 28 12:36:54 PM PDT 24 505734679 ps
T1146 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2489697490 Mar 28 12:36:54 PM PDT 24 Mar 28 12:37:06 PM PDT 24 288511206 ps
T1147 /workspace/coverage/cover_reg_top/31.kmac_intr_test.3400423152 Mar 28 12:36:56 PM PDT 24 Mar 28 12:36:58 PM PDT 24 35771874 ps
T1148 /workspace/coverage/cover_reg_top/11.kmac_intr_test.4282680593 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:54 PM PDT 24 13658628 ps
T1149 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1325427655 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:53 PM PDT 24 254050965 ps
T1150 /workspace/coverage/cover_reg_top/1.kmac_intr_test.1388770016 Mar 28 12:36:23 PM PDT 24 Mar 28 12:36:24 PM PDT 24 121197130 ps
T1151 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1797403026 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 105212913 ps
T1152 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.4216528931 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:51 PM PDT 24 180832821 ps
T1153 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2670432446 Mar 28 12:36:23 PM PDT 24 Mar 28 12:36:28 PM PDT 24 198276803 ps
T1154 /workspace/coverage/cover_reg_top/9.kmac_intr_test.3341255352 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:54 PM PDT 24 10938302 ps
T174 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1650697302 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:59 PM PDT 24 1016479620 ps
T1155 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.4219520168 Mar 28 12:36:30 PM PDT 24 Mar 28 12:36:32 PM PDT 24 38913445 ps
T1156 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.324838116 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:54 PM PDT 24 24877289 ps
T97 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2115658071 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:57 PM PDT 24 235926136 ps
T172 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.257307733 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:57 PM PDT 24 520595764 ps
T1157 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1027779929 Mar 28 12:36:25 PM PDT 24 Mar 28 12:36:27 PM PDT 24 132311508 ps
T1158 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2787050291 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:56 PM PDT 24 100681880 ps
T1159 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.82642773 Mar 28 12:36:50 PM PDT 24 Mar 28 12:36:54 PM PDT 24 120740162 ps
T1160 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3889005644 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:54 PM PDT 24 91598875 ps
T1161 /workspace/coverage/cover_reg_top/34.kmac_intr_test.920027104 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:51 PM PDT 24 32595163 ps
T1162 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2158070289 Mar 28 12:36:22 PM PDT 24 Mar 28 12:36:38 PM PDT 24 372877695 ps
T1163 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3251494159 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 77549692 ps
T1164 /workspace/coverage/cover_reg_top/40.kmac_intr_test.2040163952 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:51 PM PDT 24 48076696 ps
T1165 /workspace/coverage/cover_reg_top/42.kmac_intr_test.210756416 Mar 28 12:36:50 PM PDT 24 Mar 28 12:36:53 PM PDT 24 22595628 ps
T1166 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.3732437538 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:56 PM PDT 24 1473149574 ps
T163 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2908235317 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:59 PM PDT 24 382841460 ps
T1167 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.525013325 Mar 28 12:36:24 PM PDT 24 Mar 28 12:36:25 PM PDT 24 69583920 ps
T165 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1169451948 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:58 PM PDT 24 187936016 ps
T1168 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1222604117 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:59 PM PDT 24 247279989 ps
T1169 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1795212086 Mar 28 12:36:50 PM PDT 24 Mar 28 12:36:54 PM PDT 24 32593276 ps
T126 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2725738299 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:55 PM PDT 24 19063631 ps
T1170 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1718310132 Mar 28 12:36:24 PM PDT 24 Mar 28 12:36:26 PM PDT 24 58847758 ps
T1171 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2788504673 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:51 PM PDT 24 48064462 ps
T1172 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3253449071 Mar 28 12:36:27 PM PDT 24 Mar 28 12:36:29 PM PDT 24 76018567 ps
T1173 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3041035040 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:55 PM PDT 24 155205091 ps
T1174 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.955266078 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:47 PM PDT 24 24776987 ps
T1175 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1327322473 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:52 PM PDT 24 64255254 ps
T1176 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.841582170 Mar 28 12:36:33 PM PDT 24 Mar 28 12:36:34 PM PDT 24 18108141 ps
T1177 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1521574430 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 27290661 ps
T1178 /workspace/coverage/cover_reg_top/36.kmac_intr_test.5450285 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 20525136 ps
T1179 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2412949848 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:49 PM PDT 24 74627290 ps
T1180 /workspace/coverage/cover_reg_top/35.kmac_intr_test.3713414696 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:52 PM PDT 24 34745480 ps
T1181 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1350626846 Mar 28 12:36:43 PM PDT 24 Mar 28 12:36:52 PM PDT 24 466598819 ps
T1182 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3896765607 Mar 28 12:36:43 PM PDT 24 Mar 28 12:36:46 PM PDT 24 49432194 ps
T1183 /workspace/coverage/cover_reg_top/10.kmac_intr_test.1046552132 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:54 PM PDT 24 36123437 ps
T1184 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2495752712 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:49 PM PDT 24 219288145 ps
T1185 /workspace/coverage/cover_reg_top/19.kmac_intr_test.3682153765 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:50 PM PDT 24 37679978 ps
T1186 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1201763079 Mar 28 12:36:55 PM PDT 24 Mar 28 12:36:57 PM PDT 24 27455576 ps
T1187 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3705475692 Mar 28 12:36:50 PM PDT 24 Mar 28 12:36:53 PM PDT 24 23690769 ps
T175 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.343978919 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:52 PM PDT 24 139385587 ps
T1188 /workspace/coverage/cover_reg_top/12.kmac_intr_test.1142776712 Mar 28 12:36:50 PM PDT 24 Mar 28 12:36:53 PM PDT 24 11818349 ps
T1189 /workspace/coverage/cover_reg_top/14.kmac_intr_test.249999568 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:52 PM PDT 24 15315158 ps
T1190 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2346933699 Mar 28 12:36:54 PM PDT 24 Mar 28 12:36:58 PM PDT 24 186038330 ps
T1191 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1538037230 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:54 PM PDT 24 29010947 ps
T1192 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2134739322 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 290115864 ps
T1193 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3673102981 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 287745913 ps
T1194 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1903767061 Mar 28 12:36:54 PM PDT 24 Mar 28 12:36:56 PM PDT 24 74511131 ps
T1195 /workspace/coverage/cover_reg_top/3.kmac_intr_test.1515314179 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:50 PM PDT 24 15002302 ps
T1196 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3240430801 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 119853503 ps
T1197 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3473869667 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:54 PM PDT 24 170955978 ps
T1198 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3055573386 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:53 PM PDT 24 60359587 ps
T1199 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.87025101 Mar 28 12:36:25 PM PDT 24 Mar 28 12:36:29 PM PDT 24 1451661497 ps
T1200 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3937729891 Mar 28 12:36:44 PM PDT 24 Mar 28 12:36:47 PM PDT 24 222015317 ps
T1201 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3556620093 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:55 PM PDT 24 33175284 ps
T1202 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1962014806 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:56 PM PDT 24 844198840 ps
T1203 /workspace/coverage/cover_reg_top/27.kmac_intr_test.2079566661 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 35634451 ps
T1204 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2392563614 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:47 PM PDT 24 81101064 ps
T1205 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2317829544 Mar 28 12:36:51 PM PDT 24 Mar 28 12:37:02 PM PDT 24 1902847630 ps
T1206 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.344803385 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:52 PM PDT 24 265940993 ps
T1207 /workspace/coverage/cover_reg_top/0.kmac_intr_test.1169020060 Mar 28 12:36:30 PM PDT 24 Mar 28 12:36:31 PM PDT 24 20067111 ps
T1208 /workspace/coverage/cover_reg_top/18.kmac_intr_test.1387938239 Mar 28 12:36:55 PM PDT 24 Mar 28 12:36:57 PM PDT 24 11905655 ps
T1209 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1171040118 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 17251796 ps
T1210 /workspace/coverage/cover_reg_top/21.kmac_intr_test.3335209735 Mar 28 12:36:46 PM PDT 24 Mar 28 12:36:51 PM PDT 24 51591914 ps
T1211 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1820625174 Mar 28 12:36:55 PM PDT 24 Mar 28 12:36:57 PM PDT 24 177487507 ps
T1212 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2361902847 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:56 PM PDT 24 153325733 ps
T1213 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1584785987 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:57 PM PDT 24 201604125 ps
T1214 /workspace/coverage/cover_reg_top/26.kmac_intr_test.3648110628 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:55 PM PDT 24 17429569 ps
T1215 /workspace/coverage/cover_reg_top/17.kmac_intr_test.1123286374 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 11240761 ps
T1216 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.51196777 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 343287408 ps
T1217 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.634460556 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 96385934 ps
T127 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1692699504 Mar 28 12:36:33 PM PDT 24 Mar 28 12:36:34 PM PDT 24 21647813 ps
T1218 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.108056515 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 16561582 ps
T1219 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3266318705 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:56 PM PDT 24 42779458 ps
T1220 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.893506234 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:52 PM PDT 24 34303107 ps
T1221 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2663321048 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 84635659 ps
T1222 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2036645287 Mar 28 12:36:54 PM PDT 24 Mar 28 12:36:55 PM PDT 24 15247389 ps
T1223 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3666027368 Mar 28 12:36:43 PM PDT 24 Mar 28 12:36:45 PM PDT 24 36635981 ps
T1224 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2679049880 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:55 PM PDT 24 144321219 ps
T1225 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1881040701 Mar 28 12:36:48 PM PDT 24 Mar 28 12:36:51 PM PDT 24 45716454 ps
T170 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3965063104 Mar 28 12:36:30 PM PDT 24 Mar 28 12:36:33 PM PDT 24 244474346 ps
T171 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.285376220 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:59 PM PDT 24 317784737 ps
T1226 /workspace/coverage/cover_reg_top/13.kmac_intr_test.2180494422 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:52 PM PDT 24 140048712 ps
T1227 /workspace/coverage/cover_reg_top/4.kmac_intr_test.3226366190 Mar 28 12:36:45 PM PDT 24 Mar 28 12:36:50 PM PDT 24 58040485 ps
T1228 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2989175874 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:56 PM PDT 24 34148707 ps
T1229 /workspace/coverage/cover_reg_top/16.kmac_intr_test.3846908839 Mar 28 12:36:50 PM PDT 24 Mar 28 12:36:54 PM PDT 24 13717472 ps
T1230 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3317802771 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:57 PM PDT 24 236750085 ps
T1231 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.336332382 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:54 PM PDT 24 77197076 ps
T1232 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1024123003 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:56 PM PDT 24 88615760 ps
T1233 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2414510357 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:57 PM PDT 24 219412233 ps
T1234 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2790290049 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 128684878 ps
T1235 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2186945109 Mar 28 12:36:44 PM PDT 24 Mar 28 12:36:48 PM PDT 24 1712407157 ps
T1236 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1765636270 Mar 28 12:36:53 PM PDT 24 Mar 28 12:36:55 PM PDT 24 111254157 ps
T1237 /workspace/coverage/cover_reg_top/45.kmac_intr_test.1789018612 Mar 28 12:36:55 PM PDT 24 Mar 28 12:36:57 PM PDT 24 13552161 ps
T1238 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2258352411 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:55 PM PDT 24 16667856 ps
T1239 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3617781177 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 261095301 ps
T1240 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3927793415 Mar 28 12:36:51 PM PDT 24 Mar 28 12:36:55 PM PDT 24 128252832 ps
T164 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.423670211 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 61066227 ps
T166 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.26561735 Mar 28 12:36:49 PM PDT 24 Mar 28 12:36:57 PM PDT 24 230448776 ps
T173 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2250753214 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:59 PM PDT 24 254671284 ps
T1241 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2534810041 Mar 28 12:36:39 PM PDT 24 Mar 28 12:36:40 PM PDT 24 91886924 ps
T167 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.89981658 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:58 PM PDT 24 189385210 ps
T1242 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.186369958 Mar 28 12:36:39 PM PDT 24 Mar 28 12:36:41 PM PDT 24 100720604 ps
T1243 /workspace/coverage/cover_reg_top/49.kmac_intr_test.1424589711 Mar 28 12:36:44 PM PDT 24 Mar 28 12:36:46 PM PDT 24 40987821 ps
T1244 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.661390346 Mar 28 12:36:47 PM PDT 24 Mar 28 12:36:54 PM PDT 24 582582845 ps
T1245 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.4126250360 Mar 28 12:36:52 PM PDT 24 Mar 28 12:36:56 PM PDT 24 30695909 ps

Test location /workspace/coverage/default/5.kmac_stress_all.2493804149
Short name T15
Test name
Test status
Simulation time 289852989774 ps
CPU time 2145.55 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 02:26:40 PM PDT 24
Peak memory 453980 kb
Host smart-639d26ed-a824-4324-8b15-421f2653c3a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2493804149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2493804149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.741645134
Short name T105
Test name
Test status
Simulation time 1264939063 ps
CPU time 5.53 seconds
Started Mar 28 12:36:42 PM PDT 24
Finished Mar 28 12:36:47 PM PDT 24
Peak memory 206712 kb
Host smart-b37e56d7-1a88-4942-87f6-bbacf1c5ea66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741645134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.741645
134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.618453693
Short name T6
Test name
Test status
Simulation time 1771513249 ps
CPU time 25.77 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 01:51:20 PM PDT 24
Peak memory 242076 kb
Host smart-e27e1f0b-0f80-411c-b7fc-e096242c7f30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618453693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.618453693 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/16.kmac_stress_all_with_rand_reset.477619325
Short name T44
Test name
Test status
Simulation time 42761345369 ps
CPU time 408.28 seconds
Started Mar 28 01:52:29 PM PDT 24
Finished Mar 28 01:59:17 PM PDT 24
Peak memory 286208 kb
Host smart-d1643d6c-2c9b-4596-ad99-2af11efff928
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477619325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all_with_rand_reset.477619325 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.kmac_key_error.3159233313
Short name T20
Test name
Test status
Simulation time 3547963128 ps
CPU time 5.26 seconds
Started Mar 28 02:12:33 PM PDT 24
Finished Mar 28 02:12:39 PM PDT 24
Peak memory 207716 kb
Host smart-1da29592-fb49-4046-b407-eec929fcf625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159233313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3159233313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.3431506345
Short name T9
Test name
Test status
Simulation time 52228123 ps
CPU time 1.41 seconds
Started Mar 28 02:02:46 PM PDT 24
Finished Mar 28 02:02:48 PM PDT 24
Peak memory 217064 kb
Host smart-0497732f-5b3c-4e29-88ac-3361f82ecc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431506345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3431506345 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1482833043
Short name T5
Test name
Test status
Simulation time 57796018 ps
CPU time 1.35 seconds
Started Mar 28 01:53:18 PM PDT 24
Finished Mar 28 01:53:19 PM PDT 24
Peak memory 216108 kb
Host smart-54c86629-9bc4-4174-a4df-aa86622cb3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482833043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1482833043 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_error.2446191120
Short name T153
Test name
Test status
Simulation time 28446437088 ps
CPU time 287.84 seconds
Started Mar 28 01:53:14 PM PDT 24
Finished Mar 28 01:58:02 PM PDT 24
Peak memory 253676 kb
Host smart-c027c629-d5c4-4989-9f2b-62dda57b1e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446191120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2446191120 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.204031504
Short name T50
Test name
Test status
Simulation time 911622607 ps
CPU time 10.33 seconds
Started Mar 28 02:01:56 PM PDT 24
Finished Mar 28 02:02:07 PM PDT 24
Peak memory 224340 kb
Host smart-78c8f24d-e86e-4e33-9319-fa9f97b080e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204031504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.204031504 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4137810391
Short name T90
Test name
Test status
Simulation time 78446837 ps
CPU time 1.3 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215276 kb
Host smart-29191e67-6ee5-473e-99ce-37caec170fe3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137810391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.4137810391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.kmac_app.978735399
Short name T3
Test name
Test status
Simulation time 1454722801 ps
CPU time 78.61 seconds
Started Mar 28 01:52:13 PM PDT 24
Finished Mar 28 01:53:31 PM PDT 24
Peak memory 228560 kb
Host smart-dbfbb03b-81f5-417b-b1bb-73e069e84219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978735399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.978735399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.801049809
Short name T140
Test name
Test status
Simulation time 17714028 ps
CPU time 0.88 seconds
Started Mar 28 12:36:54 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206496 kb
Host smart-5d0ed4d5-8411-49f5-86c8-16d7b5a21502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801049809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.801049809 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.3448379429
Short name T33
Test name
Test status
Simulation time 54976702 ps
CPU time 1.16 seconds
Started Mar 28 01:53:53 PM PDT 24
Finished Mar 28 01:53:54 PM PDT 24
Peak memory 215960 kb
Host smart-28a26ab1-a93a-4851-a0b8-7bc78a15c6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448379429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3448379429 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3378883860
Short name T7
Test name
Test status
Simulation time 34750066 ps
CPU time 1.38 seconds
Started Mar 28 02:11:12 PM PDT 24
Finished Mar 28 02:11:13 PM PDT 24
Peak memory 215972 kb
Host smart-25d144e2-1a72-42b2-88de-75b81eebd28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378883860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3378883860 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.2723543207
Short name T81
Test name
Test status
Simulation time 86611949301 ps
CPU time 3439.46 seconds
Started Mar 28 01:55:29 PM PDT 24
Finished Mar 28 02:52:49 PM PDT 24
Peak memory 560812 kb
Host smart-387f10dc-f5a7-45fd-8a19-fc4aa1703e07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2723543207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.2723543207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.549077817
Short name T109
Test name
Test status
Simulation time 14765915 ps
CPU time 0.74 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206428 kb
Host smart-40842cfe-bfda-48a3-9f3c-48e007a9793a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549077817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.549077817 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1692699504
Short name T127
Test name
Test status
Simulation time 21647813 ps
CPU time 1.21 seconds
Started Mar 28 12:36:33 PM PDT 24
Finished Mar 28 12:36:34 PM PDT 24
Peak memory 214920 kb
Host smart-25773e59-b55a-4b47-a85f-a013884af238
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692699504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.1692699504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/10.kmac_alert_test.1529045692
Short name T265
Test name
Test status
Simulation time 16840745 ps
CPU time 0.79 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 01:51:22 PM PDT 24
Peak memory 205612 kb
Host smart-692c0d88-24f3-42e1-87b6-2fce82656d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529045692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1529045692 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3471648783
Short name T94
Test name
Test status
Simulation time 55683631 ps
CPU time 1.31 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:47 PM PDT 24
Peak memory 215368 kb
Host smart-eab63e05-545d-415a-b732-e16e120768e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471648783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.3471648783 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.kmac_app.1119298578
Short name T71
Test name
Test status
Simulation time 15640224193 ps
CPU time 62.18 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:52:22 PM PDT 24
Peak memory 223944 kb
Host smart-95b209fa-dfc5-4739-935a-48126e4a4da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119298578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1119298578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.89981658
Short name T167
Test name
Test status
Simulation time 189385210 ps
CPU time 4.56 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:58 PM PDT 24
Peak memory 215008 kb
Host smart-329b374c-0132-498a-bdc1-65f47194f184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89981658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.899816
58 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/43.kmac_sideload.313511593
Short name T146
Test name
Test status
Simulation time 53429206320 ps
CPU time 190.3 seconds
Started Mar 28 02:08:21 PM PDT 24
Finished Mar 28 02:11:32 PM PDT 24
Peak memory 238236 kb
Host smart-cf075c10-3b6a-4a85-ad79-501ffaebec29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313511593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.313511593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1718310132
Short name T1170
Test name
Test status
Simulation time 58847758 ps
CPU time 1.72 seconds
Started Mar 28 12:36:24 PM PDT 24
Finished Mar 28 12:36:26 PM PDT 24
Peak memory 215300 kb
Host smart-f3ae8482-ab35-4f13-a237-75f2b9358885
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718310132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.1718310132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2250753214
Short name T173
Test name
Test status
Simulation time 254671284 ps
CPU time 4.98 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:59 PM PDT 24
Peak memory 214880 kb
Host smart-b0dcbc54-7330-4df7-a6c2-baada4890eda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250753214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2250
753214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.394517784
Short name T591
Test name
Test status
Simulation time 12011540500 ps
CPU time 93.14 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 01:53:10 PM PDT 24
Peak memory 229640 kb
Host smart-be36e38c-cfb2-4242-9805-49561d93d5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394517784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.394517784 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_stress_all.14679964
Short name T27
Test name
Test status
Simulation time 41531208146 ps
CPU time 1655.23 seconds
Started Mar 28 01:51:54 PM PDT 24
Finished Mar 28 02:19:30 PM PDT 24
Peak memory 412060 kb
Host smart-95387e15-7181-4247-a122-4e927e71b45d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=14679964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.14679964 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_key_error.1867391217
Short name T22
Test name
Test status
Simulation time 3648361088 ps
CPU time 5.56 seconds
Started Mar 28 02:04:39 PM PDT 24
Finished Mar 28 02:04:44 PM PDT 24
Peak memory 207812 kb
Host smart-3d8230ef-de95-485c-9cfa-fbf21546630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867391217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1867391217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3965063104
Short name T170
Test name
Test status
Simulation time 244474346 ps
CPU time 2.96 seconds
Started Mar 28 12:36:30 PM PDT 24
Finished Mar 28 12:36:33 PM PDT 24
Peak memory 214900 kb
Host smart-aeb1a328-4100-425c-b9bf-26d098c98ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965063104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.39650
63104 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.1293556404
Short name T1102
Test name
Test status
Simulation time 24829232 ps
CPU time 0.75 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206496 kb
Host smart-9de7a271-4cf7-4d8c-b5f2-f3ffc74f32cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293556404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1293556404 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/default/13.kmac_smoke.3970729528
Short name T303
Test name
Test status
Simulation time 1595832773 ps
CPU time 21.2 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 01:51:57 PM PDT 24
Peak memory 220004 kb
Host smart-2183a8de-0b8e-4b27-b201-e702187984ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970729528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3970729528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.4219340609
Short name T78
Test name
Test status
Simulation time 12567338700 ps
CPU time 160.91 seconds
Started Mar 28 01:53:39 PM PDT 24
Finished Mar 28 01:56:20 PM PDT 24
Peak memory 249556 kb
Host smart-a537d4d9-f605-407a-83f3-d6b2b2bdd797
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4219340609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.4219340609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.435608158
Short name T144
Test name
Test status
Simulation time 311169558079 ps
CPU time 1427.43 seconds
Started Mar 28 01:53:36 PM PDT 24
Finished Mar 28 02:17:24 PM PDT 24
Peak memory 340592 kb
Host smart-501b892a-bfdf-4d41-92f2-a68bb6a5ae51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=435608158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.435608158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.759260574
Short name T88
Test name
Test status
Simulation time 148722260 ps
CPU time 1.34 seconds
Started Mar 28 12:36:24 PM PDT 24
Finished Mar 28 12:36:25 PM PDT 24
Peak memory 215292 kb
Host smart-4d7b6c4f-572e-4f7c-a9d2-d11704704ee3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759260574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e
rrors.759260574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.kmac_burst_write.4022176622
Short name T409
Test name
Test status
Simulation time 7301731248 ps
CPU time 607.5 seconds
Started Mar 28 01:52:07 PM PDT 24
Finished Mar 28 02:02:15 PM PDT 24
Peak memory 231432 kb
Host smart-d511b350-7b07-40e3-8d93-eefa9bc7965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022176622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.4022176622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3999170820
Short name T1104
Test name
Test status
Simulation time 227425749 ps
CPU time 5.05 seconds
Started Mar 28 12:36:29 PM PDT 24
Finished Mar 28 12:36:35 PM PDT 24
Peak memory 206696 kb
Host smart-aad82414-ec34-4371-938f-3577a0fc51b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999170820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3999170
820 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3545966932
Short name T1129
Test name
Test status
Simulation time 722159318 ps
CPU time 8.37 seconds
Started Mar 28 12:36:33 PM PDT 24
Finished Mar 28 12:36:41 PM PDT 24
Peak memory 206724 kb
Host smart-846d3bce-8bd9-4faa-baa3-ccf539f21abd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545966932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3545966
932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1575175474
Short name T142
Test name
Test status
Simulation time 23541711 ps
CPU time 1.02 seconds
Started Mar 28 12:36:32 PM PDT 24
Finished Mar 28 12:36:33 PM PDT 24
Peak memory 206536 kb
Host smart-eed4b3c7-8a83-43d5-b0ce-9733316ec3b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575175474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1575175
474 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.285002704
Short name T134
Test name
Test status
Simulation time 50723880 ps
CPU time 1.64 seconds
Started Mar 28 12:36:15 PM PDT 24
Finished Mar 28 12:36:16 PM PDT 24
Peak memory 215048 kb
Host smart-c252daf9-b1c3-4b06-82ef-d65e0faaf3a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285002704 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.285002704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.71354555
Short name T1145
Test name
Test status
Simulation time 49354910 ps
CPU time 0.89 seconds
Started Mar 28 12:36:22 PM PDT 24
Finished Mar 28 12:36:23 PM PDT 24
Peak memory 206516 kb
Host smart-579314c8-5256-4cb4-b275-112df0f819ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71354555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.71354555 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.1169020060
Short name T1207
Test name
Test status
Simulation time 20067111 ps
CPU time 0.79 seconds
Started Mar 28 12:36:30 PM PDT 24
Finished Mar 28 12:36:31 PM PDT 24
Peak memory 206476 kb
Host smart-8aa242ef-5ee6-45ef-9d57-7b29d61b7484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169020060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1169020060 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.966293732
Short name T1093
Test name
Test status
Simulation time 13073668 ps
CPU time 0.75 seconds
Started Mar 28 12:36:33 PM PDT 24
Finished Mar 28 12:36:34 PM PDT 24
Peak memory 206568 kb
Host smart-18cd202b-3d66-49cd-86da-79141f8a6119
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966293732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.966293732 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2026825571
Short name T1094
Test name
Test status
Simulation time 36834338 ps
CPU time 2.13 seconds
Started Mar 28 12:36:23 PM PDT 24
Finished Mar 28 12:36:25 PM PDT 24
Peak memory 214904 kb
Host smart-8dee59b3-002d-461a-b569-8799fc472a50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026825571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.2026825571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.841582170
Short name T1176
Test name
Test status
Simulation time 18108141 ps
CPU time 0.83 seconds
Started Mar 28 12:36:33 PM PDT 24
Finished Mar 28 12:36:34 PM PDT 24
Peak memory 206528 kb
Host smart-cd48be59-0f3f-4831-9b3b-b415fe507cf2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841582170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_e
rrors.841582170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2240843632
Short name T1131
Test name
Test status
Simulation time 219819792 ps
CPU time 3.26 seconds
Started Mar 28 12:36:30 PM PDT 24
Finished Mar 28 12:36:33 PM PDT 24
Peak memory 215268 kb
Host smart-e4071209-f343-497d-b0c6-13a343743cb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240843632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.2240843632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.4219520168
Short name T1155
Test name
Test status
Simulation time 38913445 ps
CPU time 1.88 seconds
Started Mar 28 12:36:30 PM PDT 24
Finished Mar 28 12:36:32 PM PDT 24
Peak memory 217884 kb
Host smart-435995fb-be74-4b8d-adfa-8cab3d4b19a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219520168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.4219520168 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2670432446
Short name T1153
Test name
Test status
Simulation time 198276803 ps
CPU time 5.31 seconds
Started Mar 28 12:36:23 PM PDT 24
Finished Mar 28 12:36:28 PM PDT 24
Peak memory 206728 kb
Host smart-4d100113-f5c1-491c-aee3-a0f574814100
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670432446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2670432
446 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2158070289
Short name T1162
Test name
Test status
Simulation time 372877695 ps
CPU time 16.23 seconds
Started Mar 28 12:36:22 PM PDT 24
Finished Mar 28 12:36:38 PM PDT 24
Peak memory 206724 kb
Host smart-3cc6198e-e755-4606-a83d-9f1c14f2c1c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158070289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2158070
289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.525013325
Short name T1167
Test name
Test status
Simulation time 69583920 ps
CPU time 0.95 seconds
Started Mar 28 12:36:24 PM PDT 24
Finished Mar 28 12:36:25 PM PDT 24
Peak memory 206528 kb
Host smart-e2eec976-5056-4890-913d-20c6d269d208
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525013325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.52501332
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3253449071
Short name T1172
Test name
Test status
Simulation time 76018567 ps
CPU time 2.38 seconds
Started Mar 28 12:36:27 PM PDT 24
Finished Mar 28 12:36:29 PM PDT 24
Peak memory 223112 kb
Host smart-1569ba39-1202-4dcb-a9b2-a6d3a20a4816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253449071 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.3253449071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2090371779
Short name T1141
Test name
Test status
Simulation time 142706354 ps
CPU time 1.2 seconds
Started Mar 28 12:36:24 PM PDT 24
Finished Mar 28 12:36:25 PM PDT 24
Peak memory 206700 kb
Host smart-1daeca1f-428b-4e37-a0f2-5885207091fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090371779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2090371779 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.1388770016
Short name T1150
Test name
Test status
Simulation time 121197130 ps
CPU time 0.76 seconds
Started Mar 28 12:36:23 PM PDT 24
Finished Mar 28 12:36:24 PM PDT 24
Peak memory 206480 kb
Host smart-e84358e8-568e-480b-be24-c908581e2bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388770016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1388770016 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2346462997
Short name T124
Test name
Test status
Simulation time 27378436 ps
CPU time 1.29 seconds
Started Mar 28 12:36:23 PM PDT 24
Finished Mar 28 12:36:25 PM PDT 24
Peak memory 214900 kb
Host smart-d6e7c1e1-0c32-4f31-95cb-11c7bba47afa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346462997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.2346462997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.4026973132
Short name T1108
Test name
Test status
Simulation time 61565932 ps
CPU time 0.72 seconds
Started Mar 28 12:36:24 PM PDT 24
Finished Mar 28 12:36:25 PM PDT 24
Peak memory 206588 kb
Host smart-a4310ad2-1d7c-41d4-b3ab-354a3bd1b3e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026973132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.4026973132
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.87025101
Short name T1199
Test name
Test status
Simulation time 1451661497 ps
CPU time 2.75 seconds
Started Mar 28 12:36:25 PM PDT 24
Finished Mar 28 12:36:29 PM PDT 24
Peak memory 215036 kb
Host smart-14551777-2307-479b-bdfa-9ae0e48a8ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87025101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_o
utstanding.87025101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.2453876676
Short name T1112
Test name
Test status
Simulation time 298189767 ps
CPU time 3.09 seconds
Started Mar 28 12:36:19 PM PDT 24
Finished Mar 28 12:36:22 PM PDT 24
Peak memory 215000 kb
Host smart-4af295d7-cff1-490f-a37d-1d28336678be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453876676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2453876676 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2687037865
Short name T104
Test name
Test status
Simulation time 68085359 ps
CPU time 2.47 seconds
Started Mar 28 12:36:20 PM PDT 24
Finished Mar 28 12:36:23 PM PDT 24
Peak memory 216916 kb
Host smart-e9d06500-c8f5-440c-bf51-1c04b1a53132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687037865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.26870
37865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.634186117
Short name T1138
Test name
Test status
Simulation time 580045931 ps
CPU time 1.51 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 220624 kb
Host smart-835b15d9-431c-465b-97cb-66f0d201d720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634186117 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.634186117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1765636270
Short name T1236
Test name
Test status
Simulation time 111254157 ps
CPU time 1.19 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206752 kb
Host smart-9ca30c84-74ff-4ed4-9f7e-0e6c8c80b826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765636270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1765636270 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.1046552132
Short name T1183
Test name
Test status
Simulation time 36123437 ps
CPU time 0.74 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206448 kb
Host smart-2d708bfe-b6e1-484e-80e7-a7d35d878ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046552132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1046552132 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1201763079
Short name T1186
Test name
Test status
Simulation time 27455576 ps
CPU time 1.42 seconds
Started Mar 28 12:36:55 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 215028 kb
Host smart-eb2f48ff-6f2a-49e3-9a68-ab0ead5ca4d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201763079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.1201763079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.994502232
Short name T1137
Test name
Test status
Simulation time 56906877 ps
CPU time 1.22 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:37:04 PM PDT 24
Peak memory 215316 kb
Host smart-317af59f-ef35-4dcb-a968-60aff5113412
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994502232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_
errors.994502232 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2115658071
Short name T97
Test name
Test status
Simulation time 235926136 ps
CPU time 2.95 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 215268 kb
Host smart-d0bf49b5-518e-441d-b27f-5f56bf894f6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115658071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.2115658071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2346933699
Short name T1190
Test name
Test status
Simulation time 186038330 ps
CPU time 3.24 seconds
Started Mar 28 12:36:54 PM PDT 24
Finished Mar 28 12:36:58 PM PDT 24
Peak memory 215080 kb
Host smart-79ec97d2-81b6-41c2-bfb0-8c44bb951c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346933699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2346933699 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2083642645
Short name T162
Test name
Test status
Simulation time 266191750 ps
CPU time 4.78 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 214884 kb
Host smart-3c0c190c-216d-4203-bb26-74510b63de48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083642645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2083
642645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2989175874
Short name T1228
Test name
Test status
Simulation time 34148707 ps
CPU time 2.31 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 222876 kb
Host smart-c7cc7bae-9913-4f55-977b-26e2dd02bc98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989175874 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2989175874 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2258352411
Short name T1238
Test name
Test status
Simulation time 16667856 ps
CPU time 0.91 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206428 kb
Host smart-aa7a6d3a-569b-4a23-81a7-c7e7c04c9631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258352411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2258352411 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.4282680593
Short name T1148
Test name
Test status
Simulation time 13658628 ps
CPU time 0.88 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206336 kb
Host smart-7327640f-334e-42c2-999f-56ba921dfbd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282680593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.4282680593 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2663321048
Short name T1221
Test name
Test status
Simulation time 84635659 ps
CPU time 1.61 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215008 kb
Host smart-1c3e74ed-a2ac-424b-9068-42e2bd6c576b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663321048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.2663321048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.634460556
Short name T1217
Test name
Test status
Simulation time 96385934 ps
CPU time 1.11 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215292 kb
Host smart-63013348-2e72-48cf-8d96-0af18282ddcb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634460556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_
errors.634460556 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1325427655
Short name T1149
Test name
Test status
Simulation time 254050965 ps
CPU time 1.83 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:53 PM PDT 24
Peak memory 222628 kb
Host smart-853537d8-730a-4755-9c65-6e425a887aaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325427655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.1325427655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2039828812
Short name T1092
Test name
Test status
Simulation time 58294658 ps
CPU time 1.43 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:47 PM PDT 24
Peak memory 216064 kb
Host smart-308e8fd8-916d-4dcb-a589-65364243bbb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039828812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2039828812 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.336332382
Short name T1231
Test name
Test status
Simulation time 77197076 ps
CPU time 2.66 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 223112 kb
Host smart-f4307e7e-18a0-4a0b-adbb-9a25c3f8e6f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336332382 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.336332382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3705475692
Short name T1187
Test name
Test status
Simulation time 23690769 ps
CPU time 0.94 seconds
Started Mar 28 12:36:50 PM PDT 24
Finished Mar 28 12:36:53 PM PDT 24
Peak memory 206520 kb
Host smart-d2d71798-b617-452a-8376-6d9935019ba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705475692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3705475692 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.1142776712
Short name T1188
Test name
Test status
Simulation time 11818349 ps
CPU time 0.75 seconds
Started Mar 28 12:36:50 PM PDT 24
Finished Mar 28 12:36:53 PM PDT 24
Peak memory 206496 kb
Host smart-1e686df0-a414-43a4-bea6-4660ce48c287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142776712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1142776712 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2118593646
Short name T1127
Test name
Test status
Simulation time 206758755 ps
CPU time 2.46 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215024 kb
Host smart-e1378c6c-53c7-4cd8-b33b-fd47e2b57eb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118593646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.2118593646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2134739322
Short name T1192
Test name
Test status
Simulation time 290115864 ps
CPU time 1.38 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215356 kb
Host smart-64dd08ab-1b36-4bde-a5f9-6dd4b852a4bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134739322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.2134739322 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.511878615
Short name T92
Test name
Test status
Simulation time 53074025 ps
CPU time 1.73 seconds
Started Mar 28 12:36:55 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 215312 kb
Host smart-d0cb9b91-3e49-4db5-8619-37929b14563e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511878615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac
_shadow_reg_errors_with_csr_rw.511878615 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1903767061
Short name T1194
Test name
Test status
Simulation time 74511131 ps
CPU time 2.15 seconds
Started Mar 28 12:36:54 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215056 kb
Host smart-e69dbc5a-6596-4a85-8d32-51dcd5f76bee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903767061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1903767061 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.452998497
Short name T1103
Test name
Test status
Simulation time 308149184 ps
CPU time 1.5 seconds
Started Mar 28 12:36:44 PM PDT 24
Finished Mar 28 12:36:47 PM PDT 24
Peak memory 221808 kb
Host smart-30039f40-556e-4025-9992-3ca8f80cdea0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452998497 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.452998497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2036645287
Short name T1222
Test name
Test status
Simulation time 15247389 ps
CPU time 1.15 seconds
Started Mar 28 12:36:54 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 214684 kb
Host smart-2687ab72-31f3-4fcf-ae94-44369a1cad5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036645287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2036645287 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.2180494422
Short name T1226
Test name
Test status
Simulation time 140048712 ps
CPU time 0.75 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 206492 kb
Host smart-b802726b-7a9e-486d-abd4-a5074180fd30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180494422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2180494422 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3937729891
Short name T1200
Test name
Test status
Simulation time 222015317 ps
CPU time 1.84 seconds
Started Mar 28 12:36:44 PM PDT 24
Finished Mar 28 12:36:47 PM PDT 24
Peak memory 214844 kb
Host smart-97708c8b-3638-4a84-8511-54dc63373627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937729891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3937729891 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2397044557
Short name T143
Test name
Test status
Simulation time 32552310 ps
CPU time 1.08 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 215276 kb
Host smart-df4056a8-d0f1-4fb1-8fea-daf817745fb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397044557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.2397044557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3617781177
Short name T1239
Test name
Test status
Simulation time 261095301 ps
CPU time 2.12 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 214864 kb
Host smart-8cbea6a9-c3cc-4d04-a1be-9564936cc280
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617781177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.3617781177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3266318705
Short name T1219
Test name
Test status
Simulation time 42779458 ps
CPU time 2.63 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215008 kb
Host smart-99d7846a-18f4-469a-b78c-a48f1d2d883f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266318705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3266318705 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.887113908
Short name T168
Test name
Test status
Simulation time 277555893 ps
CPU time 4.52 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 214896 kb
Host smart-96ec24f1-53d1-4896-91fe-5f71171f0802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887113908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.88711
3908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.4216528931
Short name T1152
Test name
Test status
Simulation time 180832821 ps
CPU time 1.6 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 214996 kb
Host smart-b5abf66b-a9e7-4a36-ba97-257f0d7c1267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216528931 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.4216528931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1077092703
Short name T133
Test name
Test status
Simulation time 32301569 ps
CPU time 1.12 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206652 kb
Host smart-07b773f3-5146-457e-b9f3-886c50354e36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077092703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1077092703 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.249999568
Short name T1189
Test name
Test status
Simulation time 15315158 ps
CPU time 0.79 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 206484 kb
Host smart-5a9f44d0-f803-4ae7-941c-260a674af2b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249999568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.249999568 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4209115341
Short name T1109
Test name
Test status
Simulation time 123671159 ps
CPU time 2.14 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 214976 kb
Host smart-b2a810ee-71b0-461e-bc4c-84380215d7bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209115341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.4209115341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2638397301
Short name T89
Test name
Test status
Simulation time 95037564 ps
CPU time 2.41 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215292 kb
Host smart-1af7fa2b-8cf4-4249-af68-5b2d12810683
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638397301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.2638397301 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3451487778
Short name T1089
Test name
Test status
Simulation time 75443069 ps
CPU time 2.05 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 215048 kb
Host smart-6e800759-e873-4471-a568-6f7f05283d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451487778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3451487778 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.423670211
Short name T164
Test name
Test status
Simulation time 61066227 ps
CPU time 2.54 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 217084 kb
Host smart-a3959bb1-51a6-4484-b012-06ef515e025c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423670211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.42367
0211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1584785987
Short name T1213
Test name
Test status
Simulation time 201604125 ps
CPU time 2.48 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 223120 kb
Host smart-f1ade8e7-6ef8-4ca4-aa85-01573fb6c62e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584785987 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1584785987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2124740869
Short name T176
Test name
Test status
Simulation time 114161603 ps
CPU time 0.92 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206500 kb
Host smart-96549baf-a34a-48c6-ab03-d18b5548e276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124740869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2124740869 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1646351262
Short name T132
Test name
Test status
Simulation time 52272984 ps
CPU time 1.59 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:53 PM PDT 24
Peak memory 214888 kb
Host smart-f90f4db8-0e54-4d9e-ba0d-a771dfd25caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646351262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1646351262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2311725955
Short name T95
Test name
Test status
Simulation time 61081740 ps
CPU time 0.82 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206524 kb
Host smart-a70c3ca8-e6e9-4b52-8f2a-7250e07863d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311725955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.2311725955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.51196777
Short name T1216
Test name
Test status
Simulation time 343287408 ps
CPU time 2.54 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215352 kb
Host smart-8c88bf8d-c561-41e2-8fe2-49c8cf6d5f02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51196777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_
shadow_reg_errors_with_csr_rw.51196777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1521574430
Short name T1177
Test name
Test status
Simulation time 27290661 ps
CPU time 1.72 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215048 kb
Host smart-001831d8-7c28-4491-8473-a2c4d49ee4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521574430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1521574430 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1650697302
Short name T174
Test name
Test status
Simulation time 1016479620 ps
CPU time 4.68 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:59 PM PDT 24
Peak memory 206712 kb
Host smart-4bd73db6-7c24-4af4-b6d4-a2914a0ca8bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650697302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1650
697302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.412473452
Short name T1139
Test name
Test status
Simulation time 273576058 ps
CPU time 2.36 seconds
Started Mar 28 12:36:55 PM PDT 24
Finished Mar 28 12:36:58 PM PDT 24
Peak memory 223144 kb
Host smart-f6812875-567e-4f1e-8424-1905457ebf89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412473452 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.412473452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1355709904
Short name T136
Test name
Test status
Simulation time 24533834 ps
CPU time 0.95 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 206564 kb
Host smart-c5eb30d7-3d85-4151-9865-8c5e9514058f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355709904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1355709904 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.3846908839
Short name T1229
Test name
Test status
Simulation time 13717472 ps
CPU time 0.8 seconds
Started Mar 28 12:36:50 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206548 kb
Host smart-ce2ea315-d967-4695-b2a5-91e7824ac8d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846908839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3846908839 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1820625174
Short name T1211
Test name
Test status
Simulation time 177487507 ps
CPU time 2.04 seconds
Started Mar 28 12:36:55 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 215116 kb
Host smart-d0268b70-18ce-4242-bfd1-7bac752567e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820625174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.1820625174 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2788504673
Short name T1171
Test name
Test status
Simulation time 48064462 ps
CPU time 1.02 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 215308 kb
Host smart-add20c92-3dfc-4206-92c8-62ca4fcc58b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788504673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2788504673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3251494159
Short name T1163
Test name
Test status
Simulation time 77549692 ps
CPU time 1.95 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215300 kb
Host smart-84c72279-c3b7-4cae-8bc1-38ad22e4c327
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251494159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.3251494159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1024123003
Short name T1232
Test name
Test status
Simulation time 88615760 ps
CPU time 1.45 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215052 kb
Host smart-b1fd4638-36f4-4476-873e-d9e7fc4792e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024123003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1024123003 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.26561735
Short name T166
Test name
Test status
Simulation time 230448776 ps
CPU time 5.12 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 206732 kb
Host smart-1e23352f-a8cc-4625-87ca-d5c7451edb25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26561735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.265617
35 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1187719374
Short name T1110
Test name
Test status
Simulation time 73629909 ps
CPU time 2.35 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 223112 kb
Host smart-f2af7c3b-8993-4333-814a-b4f601f640de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187719374 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.1187719374 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.108056515
Short name T1218
Test name
Test status
Simulation time 16561582 ps
CPU time 1.09 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206704 kb
Host smart-b86cd8ae-1369-4673-b3fc-79111aa25213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108056515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.108056515 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.1123286374
Short name T1215
Test name
Test status
Simulation time 11240761 ps
CPU time 0.75 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206532 kb
Host smart-b9ae0c00-4652-4f88-b28e-4d8fd2dac9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123286374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1123286374 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2167779677
Short name T1098
Test name
Test status
Simulation time 38632263 ps
CPU time 2.24 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215028 kb
Host smart-ac11d5c4-abde-4e43-b74d-0daec9e0d3e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167779677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.2167779677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.82642773
Short name T1159
Test name
Test status
Simulation time 120740162 ps
CPU time 1.06 seconds
Started Mar 28 12:36:50 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 214976 kb
Host smart-7cfdf65f-5a68-4152-b709-6952dcb60d73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82642773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_e
rrors.82642773 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3994516260
Short name T1144
Test name
Test status
Simulation time 97733392 ps
CPU time 1.77 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215344 kb
Host smart-e5e37510-5e0d-4056-8b5a-68d6aaac711f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994516260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.3994516260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.671841796
Short name T1123
Test name
Test status
Simulation time 55390304 ps
CPU time 2.06 seconds
Started Mar 28 12:36:50 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215004 kb
Host smart-7f000433-f530-4076-ba86-11c553ace2f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671841796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.671841796 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1169451948
Short name T165
Test name
Test status
Simulation time 187936016 ps
CPU time 4.69 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:58 PM PDT 24
Peak memory 214908 kb
Host smart-a24ced68-9435-4a79-9d33-15a48eec8d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169451948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1169
451948 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1106579029
Short name T1097
Test name
Test status
Simulation time 65134294 ps
CPU time 2.34 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 223100 kb
Host smart-7b1c2562-1c41-4217-9ceb-e1a6277a148a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106579029 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1106579029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1754484362
Short name T1116
Test name
Test status
Simulation time 133915783 ps
CPU time 1.2 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206696 kb
Host smart-794373f8-1028-40ab-b2b1-1269aa9c1da5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754484362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1754484362 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.1387938239
Short name T1208
Test name
Test status
Simulation time 11905655 ps
CPU time 0.77 seconds
Started Mar 28 12:36:55 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 206540 kb
Host smart-733ea055-7f0a-4479-97a9-fed1c3cdba23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387938239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1387938239 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2012042369
Short name T131
Test name
Test status
Simulation time 71053592 ps
CPU time 1.88 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 214964 kb
Host smart-1a9353eb-e88a-46fb-a13a-5a7a347d7b10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012042369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.2012042369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1795212086
Short name T1169
Test name
Test status
Simulation time 32593276 ps
CPU time 1.15 seconds
Started Mar 28 12:36:50 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 215308 kb
Host smart-ee93119a-7864-4225-85e0-4fcf4a928fa8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795212086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1795212086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1797403026
Short name T1151
Test name
Test status
Simulation time 105212913 ps
CPU time 1.94 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 222704 kb
Host smart-eb8bd059-dec7-4dd5-8854-8648b9461aff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797403026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.1797403026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2787050291
Short name T1158
Test name
Test status
Simulation time 100681880 ps
CPU time 2.66 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215064 kb
Host smart-bc4e954e-088d-4cb4-9caf-915a8712698f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787050291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2787050291 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.285376220
Short name T171
Test name
Test status
Simulation time 317784737 ps
CPU time 5.05 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:59 PM PDT 24
Peak memory 214904 kb
Host smart-28178973-82b0-49d6-bff8-ef858fbc1010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285376220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.28537
6220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4220455460
Short name T130
Test name
Test status
Simulation time 290445580 ps
CPU time 2.34 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 223088 kb
Host smart-435cab53-d61e-4bdf-bfdc-2df88c3fc6d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220455460 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.4220455460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2412949848
Short name T1179
Test name
Test status
Simulation time 74627290 ps
CPU time 0.95 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:49 PM PDT 24
Peak memory 206492 kb
Host smart-52c1ce57-c9ed-425c-af1d-0872e1457663
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412949848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2412949848 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.3682153765
Short name T1185
Test name
Test status
Simulation time 37679978 ps
CPU time 0.76 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:50 PM PDT 24
Peak memory 206488 kb
Host smart-8991496e-50e9-40dd-a692-edf6068129c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682153765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3682153765 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3240430801
Short name T1196
Test name
Test status
Simulation time 119853503 ps
CPU time 1.67 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 214892 kb
Host smart-5e6638e9-185a-4ff2-a6a7-31e633c599a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240430801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.3240430801 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3468195557
Short name T103
Test name
Test status
Simulation time 36060088 ps
CPU time 1.61 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215000 kb
Host smart-32f6d068-f012-4786-bf50-29f99e8abf73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468195557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.3468195557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2414510357
Short name T1233
Test name
Test status
Simulation time 219412233 ps
CPU time 2.72 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 215004 kb
Host smart-c3c67801-4f47-4eb0-ad70-c05f8d96940e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414510357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2414510357 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2495752712
Short name T1184
Test name
Test status
Simulation time 219288145 ps
CPU time 2.52 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:49 PM PDT 24
Peak memory 214876 kb
Host smart-8caeb67f-9e72-4804-841b-4169dfa6657b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495752712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2495
752712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1350626846
Short name T1181
Test name
Test status
Simulation time 466598819 ps
CPU time 9 seconds
Started Mar 28 12:36:43 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 206684 kb
Host smart-85ee984f-b43c-4aee-a0a1-6546c579645b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350626846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1350626
846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.611993665
Short name T1142
Test name
Test status
Simulation time 735410965 ps
CPU time 10.61 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 206704 kb
Host smart-37b62861-b033-4ecb-8a13-2a2fbae31043
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611993665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.61199366
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1524777541
Short name T1135
Test name
Test status
Simulation time 62828180 ps
CPU time 1.03 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206708 kb
Host smart-b81c1a77-4764-49c3-9f39-8631dc7ed829
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524777541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1524777
541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.893506234
Short name T1220
Test name
Test status
Simulation time 34303107 ps
CPU time 2.22 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 223100 kb
Host smart-e917aa16-a8c2-4ba9-9483-ca0cb7dfaa64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893506234 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.893506234 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.955266078
Short name T1174
Test name
Test status
Simulation time 24776987 ps
CPU time 0.93 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:47 PM PDT 24
Peak memory 206500 kb
Host smart-9fe4a4ad-7519-4c98-bd0d-3f5fb8b37417
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955266078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.955266078 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.42967338
Short name T1099
Test name
Test status
Simulation time 26680500 ps
CPU time 0.79 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:48 PM PDT 24
Peak memory 206528 kb
Host smart-fda71bcb-2aa3-471d-a1b5-5cfb2e882295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42967338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.42967338 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2392563614
Short name T1204
Test name
Test status
Simulation time 81101064 ps
CPU time 1.43 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:47 PM PDT 24
Peak memory 214932 kb
Host smart-8b3b5783-f8fb-4f5d-af0a-7be72194528e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392563614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.2392563614 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1838977305
Short name T1130
Test name
Test status
Simulation time 15167185 ps
CPU time 0.71 seconds
Started Mar 28 12:36:43 PM PDT 24
Finished Mar 28 12:36:44 PM PDT 24
Peak memory 206524 kb
Host smart-c550b5c8-b929-4992-812a-6b5fc0d48edd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838977305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1838977305
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3382867569
Short name T1136
Test name
Test status
Simulation time 196924970 ps
CPU time 1.64 seconds
Started Mar 28 12:36:40 PM PDT 24
Finished Mar 28 12:36:43 PM PDT 24
Peak memory 214980 kb
Host smart-65119432-1861-4283-a216-1845da29db04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382867569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.3382867569 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1027779929
Short name T1157
Test name
Test status
Simulation time 132311508 ps
CPU time 1.22 seconds
Started Mar 28 12:36:25 PM PDT 24
Finished Mar 28 12:36:27 PM PDT 24
Peak memory 215328 kb
Host smart-5b94717a-d073-42ae-801a-8d5b855e0f26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027779929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.1027779929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3525670883
Short name T1122
Test name
Test status
Simulation time 28902869 ps
CPU time 1.65 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215116 kb
Host smart-d97c98f5-baea-4845-9675-986d9afa85f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525670883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.3525670883 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2981110084
Short name T1119
Test name
Test status
Simulation time 72806880 ps
CPU time 1.99 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 215032 kb
Host smart-e8073d2c-7bd6-41f2-9894-8d2809275ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981110084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2981110084 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3577114292
Short name T161
Test name
Test status
Simulation time 234623799 ps
CPU time 2.82 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206736 kb
Host smart-7efa7ad5-dbca-4969-9868-16dcf09a4a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577114292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.35771
14292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.3335209735
Short name T1210
Test name
Test status
Simulation time 51591914 ps
CPU time 0.75 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 206560 kb
Host smart-29ab9ca1-0511-4001-8947-d07c9eadc2b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335209735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3335209735 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.1148389900
Short name T1105
Test name
Test status
Simulation time 94205576 ps
CPU time 0.76 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206556 kb
Host smart-9ce0c2a5-2b84-4759-90b9-2b0fbb44821a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148389900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1148389900 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2892859693
Short name T1134
Test name
Test status
Simulation time 47172765 ps
CPU time 0.74 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 206552 kb
Host smart-2118530a-dc0a-450c-ab2c-8f9495efef50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892859693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2892859693 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.1921600569
Short name T1133
Test name
Test status
Simulation time 59554949 ps
CPU time 0.76 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206460 kb
Host smart-6f991f1f-d3f5-4823-96db-e988aab7f4ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921600569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1921600569 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.3590967597
Short name T1115
Test name
Test status
Simulation time 139570399 ps
CPU time 0.81 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:53 PM PDT 24
Peak memory 206504 kb
Host smart-e9e6ac2e-5781-4bf9-b5c4-f8436e75fced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590967597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3590967597 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.3648110628
Short name T1214
Test name
Test status
Simulation time 17429569 ps
CPU time 0.8 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206432 kb
Host smart-b017934e-2fe1-4289-b782-269355e1197b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648110628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3648110628 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.2079566661
Short name T1203
Test name
Test status
Simulation time 35634451 ps
CPU time 0.76 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206432 kb
Host smart-c6b49048-c9be-42b9-8c8e-bc51ea0a6dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079566661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2079566661 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.3679654300
Short name T158
Test name
Test status
Simulation time 21794803 ps
CPU time 0.85 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206480 kb
Host smart-f714b209-c116-4ca3-b8e1-0a9d14a4e5f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679654300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3679654300 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.3122718134
Short name T1107
Test name
Test status
Simulation time 167622390 ps
CPU time 0.73 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206500 kb
Host smart-05335098-52f2-4332-a776-6a7fd88e1778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122718134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3122718134 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1222604117
Short name T1168
Test name
Test status
Simulation time 247279989 ps
CPU time 5.22 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:59 PM PDT 24
Peak memory 206692 kb
Host smart-6fa8a1f3-2567-4727-8c18-c298d19d6d4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222604117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1222604
117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3470047728
Short name T1095
Test name
Test status
Simulation time 973248664 ps
CPU time 19.56 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:37:14 PM PDT 24
Peak memory 206712 kb
Host smart-5bff609a-e869-4873-9bac-db08c48d5f71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470047728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3470047
728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2828063627
Short name T1096
Test name
Test status
Simulation time 19470435 ps
CPU time 0.91 seconds
Started Mar 28 12:36:40 PM PDT 24
Finished Mar 28 12:36:42 PM PDT 24
Peak memory 206572 kb
Host smart-10f9af18-46a5-4eb1-a7f7-9019248f3797
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828063627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2828063
627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3041035040
Short name T1173
Test name
Test status
Simulation time 155205091 ps
CPU time 2.52 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 223124 kb
Host smart-81d7e212-32a9-4153-9c16-1e4d95ba033b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041035040 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3041035040 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1327322473
Short name T1175
Test name
Test status
Simulation time 64255254 ps
CPU time 0.96 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 214716 kb
Host smart-2e6b2d67-5ca0-421f-930e-af1a78be310f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327322473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1327322473 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1515314179
Short name T1195
Test name
Test status
Simulation time 15002302 ps
CPU time 0.78 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:50 PM PDT 24
Peak memory 206508 kb
Host smart-63bf7e57-4195-4251-beac-799381a7cf8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515314179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1515314179 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2688043147
Short name T125
Test name
Test status
Simulation time 33522623 ps
CPU time 1.24 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 214928 kb
Host smart-83e4d248-2d4c-4123-9750-af74b793212f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688043147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.2688043147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3857137699
Short name T1124
Test name
Test status
Simulation time 37798581 ps
CPU time 0.72 seconds
Started Mar 28 12:36:44 PM PDT 24
Finished Mar 28 12:36:46 PM PDT 24
Peak memory 206584 kb
Host smart-e1f75508-1b31-430c-bf34-1a7747d0d3a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857137699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3857137699
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2186945109
Short name T1235
Test name
Test status
Simulation time 1712407157 ps
CPU time 2.71 seconds
Started Mar 28 12:36:44 PM PDT 24
Finished Mar 28 12:36:48 PM PDT 24
Peak memory 215020 kb
Host smart-8ddc6f6b-ecdd-4b5d-9c19-a1ecbb62cb94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186945109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.2186945109 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2532838792
Short name T98
Test name
Test status
Simulation time 45929766 ps
CPU time 1.3 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215156 kb
Host smart-28fba6ab-f7b8-4fa4-bcce-364ac2349914
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532838792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.2532838792 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.186369958
Short name T1242
Test name
Test status
Simulation time 100720604 ps
CPU time 1.65 seconds
Started Mar 28 12:36:39 PM PDT 24
Finished Mar 28 12:36:41 PM PDT 24
Peak memory 222636 kb
Host smart-1429cf9e-242e-4a92-8fb3-bbee820b56fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186369958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_
shadow_reg_errors_with_csr_rw.186369958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.703636365
Short name T1128
Test name
Test status
Simulation time 202196272 ps
CPU time 1.5 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 215064 kb
Host smart-b97a0827-5c62-4c65-a2f8-0980e4366a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703636365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.703636365 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.343978919
Short name T175
Test name
Test status
Simulation time 139385587 ps
CPU time 3.01 seconds
Started Mar 28 12:36:46 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 214936 kb
Host smart-aaa65e1f-1bf0-46c5-924f-8d796e7f781b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343978919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.343978
919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.2047433000
Short name T1100
Test name
Test status
Simulation time 32394112 ps
CPU time 0.77 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206448 kb
Host smart-ac138e97-18ce-4507-9dbd-f782b1ab51bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047433000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2047433000 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.3400423152
Short name T1147
Test name
Test status
Simulation time 35771874 ps
CPU time 0.81 seconds
Started Mar 28 12:36:56 PM PDT 24
Finished Mar 28 12:36:58 PM PDT 24
Peak memory 206448 kb
Host smart-fbe90aba-2d3d-45fc-891e-566c2a5a1760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400423152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3400423152 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.2857013952
Short name T1121
Test name
Test status
Simulation time 14419377 ps
CPU time 0.76 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 206496 kb
Host smart-ab7397bb-61d1-4b95-b2d6-ab080a89e38e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857013952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2857013952 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.4100148496
Short name T107
Test name
Test status
Simulation time 36859207 ps
CPU time 0.71 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 206492 kb
Host smart-abc2aacd-a3c4-48f1-8ebb-e63f019c3e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100148496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.4100148496 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.920027104
Short name T1161
Test name
Test status
Simulation time 32595163 ps
CPU time 0.77 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 206516 kb
Host smart-6baeb690-d7f9-4c61-966a-fb4437c420ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920027104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.920027104 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.3713414696
Short name T1180
Test name
Test status
Simulation time 34745480 ps
CPU time 0.82 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 206500 kb
Host smart-dd044922-2cbc-452a-930b-f582b61eda5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713414696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3713414696 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.5450285
Short name T1178
Test name
Test status
Simulation time 20525136 ps
CPU time 0.73 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206532 kb
Host smart-9a4f24e0-68d4-4fc1-af0e-a569a25288ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5450285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.5450285 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.2858562956
Short name T1106
Test name
Test status
Simulation time 31514895 ps
CPU time 0.78 seconds
Started Mar 28 12:37:00 PM PDT 24
Finished Mar 28 12:37:01 PM PDT 24
Peak memory 206452 kb
Host smart-851a2d45-39ef-4108-8e76-d74f3736dc55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858562956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2858562956 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.844186425
Short name T138
Test name
Test status
Simulation time 45869663 ps
CPU time 0.75 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206512 kb
Host smart-06e214f1-c411-49fa-b1f3-ca67e0b6321e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844186425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.844186425 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.3116192382
Short name T1126
Test name
Test status
Simulation time 28369739 ps
CPU time 0.75 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:53 PM PDT 24
Peak memory 206560 kb
Host smart-7ac67818-172d-4871-8af8-9b04d49559c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116192382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3116192382 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2317829544
Short name T1205
Test name
Test status
Simulation time 1902847630 ps
CPU time 8.46 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:37:02 PM PDT 24
Peak memory 206692 kb
Host smart-3dfc440a-96f2-4a81-bf22-7b94195ceb57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317829544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2317829
544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3103068731
Short name T1125
Test name
Test status
Simulation time 6026313663 ps
CPU time 21.63 seconds
Started Mar 28 12:36:54 PM PDT 24
Finished Mar 28 12:37:16 PM PDT 24
Peak memory 206624 kb
Host smart-bcfecff2-d24a-4d7a-994f-6be0d6573de8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103068731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3103068
731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1043379836
Short name T1101
Test name
Test status
Simulation time 22120747 ps
CPU time 1.07 seconds
Started Mar 28 12:36:39 PM PDT 24
Finished Mar 28 12:36:41 PM PDT 24
Peak memory 206756 kb
Host smart-e9853b8e-e356-47b1-ba98-3c9cbe704f73
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043379836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1043379
836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2679049880
Short name T1224
Test name
Test status
Simulation time 144321219 ps
CPU time 2.38 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 216580 kb
Host smart-8936be4c-63ac-4a73-8e3c-9cb6565b2fd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679049880 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2679049880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3556620093
Short name T1201
Test name
Test status
Simulation time 33175284 ps
CPU time 0.9 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206512 kb
Host smart-61f99e28-427e-421b-b9a6-376f68f5dd39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556620093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3556620093 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.3226366190
Short name T1227
Test name
Test status
Simulation time 58040485 ps
CPU time 0.8 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:50 PM PDT 24
Peak memory 206476 kb
Host smart-4d57036d-5b9e-48c9-99dc-c554f5bad94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226366190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3226366190 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2725738299
Short name T126
Test name
Test status
Simulation time 19063631 ps
CPU time 1.35 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 214228 kb
Host smart-50265090-7809-4681-8267-9e2dac5782a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725738299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.2725738299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.916333755
Short name T1140
Test name
Test status
Simulation time 42964872 ps
CPU time 0.72 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 206564 kb
Host smart-47ab9270-e780-4dfd-a5af-db6ba57c45dc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916333755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.916333755 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3473869667
Short name T1197
Test name
Test status
Simulation time 170955978 ps
CPU time 2.2 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 214988 kb
Host smart-f1033da3-a8bf-48d5-be6e-840cea520649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473869667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.3473869667 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.547263116
Short name T1114
Test name
Test status
Simulation time 20567016 ps
CPU time 0.98 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 215132 kb
Host smart-593c6555-09fc-433b-872a-dcec83fc29e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547263116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_e
rrors.547263116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3889005644
Short name T1160
Test name
Test status
Simulation time 91598875 ps
CPU time 2.22 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 215260 kb
Host smart-11afbcaa-9011-4596-9c83-aeb506362620
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889005644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.3889005644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.1211862714
Short name T1118
Test name
Test status
Simulation time 35723382 ps
CPU time 2.17 seconds
Started Mar 28 12:36:49 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 214988 kb
Host smart-d5059aa4-66ca-4a78-91ea-50fe0680c5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211862714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1211862714 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.2040163952
Short name T1164
Test name
Test status
Simulation time 48076696 ps
CPU time 0.75 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 206560 kb
Host smart-5fd77825-7979-4b88-aeac-5eba10130255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040163952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2040163952 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.4126407252
Short name T1113
Test name
Test status
Simulation time 14899916 ps
CPU time 0.78 seconds
Started Mar 28 12:36:56 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 206504 kb
Host smart-79ee3e98-ff2f-4898-8170-6e036fcf30d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126407252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.4126407252 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.210756416
Short name T1165
Test name
Test status
Simulation time 22595628 ps
CPU time 0.8 seconds
Started Mar 28 12:36:50 PM PDT 24
Finished Mar 28 12:36:53 PM PDT 24
Peak memory 206544 kb
Host smart-897d568f-3905-4e25-97d5-908ff1593343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210756416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.210756416 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.2857774839
Short name T156
Test name
Test status
Simulation time 21941927 ps
CPU time 0.78 seconds
Started Mar 28 12:36:55 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 206508 kb
Host smart-f0cc6a6f-adbf-4b0a-b78d-5dfc6cb59069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857774839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2857774839 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.782349017
Short name T1117
Test name
Test status
Simulation time 14360663 ps
CPU time 0.85 seconds
Started Mar 28 12:36:55 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 206524 kb
Host smart-f01087f9-623d-43cb-b293-95a8ef651fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782349017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.782349017 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.1789018612
Short name T1237
Test name
Test status
Simulation time 13552161 ps
CPU time 0.77 seconds
Started Mar 28 12:36:55 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 206504 kb
Host smart-d13fa408-c3bd-48f8-a789-f51f7a3eda8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789018612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1789018612 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.757355450
Short name T1143
Test name
Test status
Simulation time 21377326 ps
CPU time 0.74 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206456 kb
Host smart-e0a6ba03-ab26-48d7-8f1e-fe8b23a12f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757355450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.757355450 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.3637733224
Short name T155
Test name
Test status
Simulation time 43747025 ps
CPU time 0.77 seconds
Started Mar 28 12:36:55 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 206504 kb
Host smart-206d5f90-1d3a-42f3-a537-eb8d820b08bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637733224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3637733224 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.2344048797
Short name T139
Test name
Test status
Simulation time 15547956 ps
CPU time 0.77 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:37:04 PM PDT 24
Peak memory 206548 kb
Host smart-2fefbda8-f2ee-4365-b4c4-26f292d3bad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344048797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2344048797 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.1424589711
Short name T1243
Test name
Test status
Simulation time 40987821 ps
CPU time 0.75 seconds
Started Mar 28 12:36:44 PM PDT 24
Finished Mar 28 12:36:46 PM PDT 24
Peak memory 206600 kb
Host smart-64853bc1-e6d1-4312-9faa-ef88e4c86f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424589711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1424589711 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3044815357
Short name T177
Test name
Test status
Simulation time 28780800 ps
CPU time 1.43 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 214968 kb
Host smart-4b043843-85c7-4919-a981-bd9a3996d63d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044815357 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3044815357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.4011112480
Short name T141
Test name
Test status
Simulation time 89944137 ps
CPU time 0.95 seconds
Started Mar 28 12:36:43 PM PDT 24
Finished Mar 28 12:36:44 PM PDT 24
Peak memory 206480 kb
Host smart-20dce0f1-9d2d-4062-8653-9c39d377c3f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011112480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.4011112480 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.3936566883
Short name T157
Test name
Test status
Simulation time 15285218 ps
CPU time 0.77 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206472 kb
Host smart-15aee95a-914a-4a56-8cb6-6f86985fd556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936566883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3936566883 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3896765607
Short name T1182
Test name
Test status
Simulation time 49432194 ps
CPU time 2.12 seconds
Started Mar 28 12:36:43 PM PDT 24
Finished Mar 28 12:36:46 PM PDT 24
Peak memory 214856 kb
Host smart-c6b6ae73-75ea-4bf4-ac36-2f8742a5b719
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896765607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.3896765607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3666027368
Short name T1223
Test name
Test status
Simulation time 36635981 ps
CPU time 1.2 seconds
Started Mar 28 12:36:43 PM PDT 24
Finished Mar 28 12:36:45 PM PDT 24
Peak memory 215324 kb
Host smart-9496edaa-16f5-4069-af1b-5969c2b5a8d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666027368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.3666027368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1704831966
Short name T93
Test name
Test status
Simulation time 44566666 ps
CPU time 1.72 seconds
Started Mar 28 12:36:54 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 223096 kb
Host smart-c7a11350-43ba-4786-b3c3-f1c7c444d26c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704831966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.1704831966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.425372574
Short name T1120
Test name
Test status
Simulation time 87722276 ps
CPU time 2.4 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 214988 kb
Host smart-aea65c92-b053-4fbd-ad9f-9edfc5799ade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425372574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.425372574 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1759834931
Short name T169
Test name
Test status
Simulation time 211477169 ps
CPU time 2.76 seconds
Started Mar 28 12:36:43 PM PDT 24
Finished Mar 28 12:36:47 PM PDT 24
Peak memory 215000 kb
Host smart-73d621c0-c654-4d5d-b7c7-520120212e16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759834931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.17598
34931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3933378542
Short name T137
Test name
Test status
Simulation time 80099736 ps
CPU time 2.28 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 222972 kb
Host smart-2b98ea2d-b7a8-46af-ade9-e2ab1bfae849
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933378542 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3933378542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1675029034
Short name T1091
Test name
Test status
Simulation time 50955105 ps
CPU time 0.94 seconds
Started Mar 28 12:36:54 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206568 kb
Host smart-2b71d909-94b3-4857-b09b-45d3fa47ea07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675029034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1675029034 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3876115084
Short name T1132
Test name
Test status
Simulation time 261799564 ps
CPU time 1.65 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 214904 kb
Host smart-24eba981-cde8-4925-b90e-a0572b3b8697
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876115084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.3876115084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2357015460
Short name T91
Test name
Test status
Simulation time 44596078 ps
CPU time 1.06 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215284 kb
Host smart-7e71c1d1-b45d-429d-9be7-e041d8f17ddf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357015460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.2357015460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3055573386
Short name T1198
Test name
Test status
Simulation time 60359587 ps
CPU time 2.35 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:53 PM PDT 24
Peak memory 215080 kb
Host smart-e63fe7e9-27d5-4ce0-bb82-6b5b4794b9f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055573386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.3055573386 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.661390346
Short name T1244
Test name
Test status
Simulation time 582582845 ps
CPU time 2.89 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 214924 kb
Host smart-2b4e07fc-273d-4c30-a5c4-d72832cbf246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661390346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.661390346 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.258189934
Short name T106
Test name
Test status
Simulation time 235408011 ps
CPU time 2.33 seconds
Started Mar 28 12:36:50 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 214884 kb
Host smart-513aee48-128e-4816-8f05-a44530496d97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258189934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.258189
934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3317802771
Short name T1230
Test name
Test status
Simulation time 236750085 ps
CPU time 2.34 seconds
Started Mar 28 12:36:53 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 223136 kb
Host smart-9e35d4e5-ff0f-4c5c-924d-b0d05a4c2668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317802771 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3317802771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2534810041
Short name T1241
Test name
Test status
Simulation time 91886924 ps
CPU time 1 seconds
Started Mar 28 12:36:39 PM PDT 24
Finished Mar 28 12:36:40 PM PDT 24
Peak memory 206540 kb
Host smart-f5c84f12-0ca7-4fdf-9bb7-3ed6314dc9b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534810041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2534810041 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.3056580397
Short name T1111
Test name
Test status
Simulation time 15196110 ps
CPU time 0.77 seconds
Started Mar 28 12:36:54 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206484 kb
Host smart-8598a43e-1c82-49b8-aef3-d983ee409247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056580397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3056580397 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2489697490
Short name T1146
Test name
Test status
Simulation time 288511206 ps
CPU time 2.17 seconds
Started Mar 28 12:36:54 PM PDT 24
Finished Mar 28 12:37:06 PM PDT 24
Peak memory 214992 kb
Host smart-ec982b98-378b-4e03-86d1-96c627335789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489697490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2489697490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1538037230
Short name T1191
Test name
Test status
Simulation time 29010947 ps
CPU time 1.12 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 215232 kb
Host smart-8ee9732c-fbcf-447a-8eed-348eb70ac181
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538037230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.1538037230 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2361902847
Short name T1212
Test name
Test status
Simulation time 153325733 ps
CPU time 2.29 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 214864 kb
Host smart-155ce879-78de-4ce8-8548-4cf474d71ea8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361902847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.2361902847 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.3732437538
Short name T1166
Test name
Test status
Simulation time 1473149574 ps
CPU time 2.85 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 214968 kb
Host smart-54067c79-fbca-4a5b-bd0c-5a14b5b493d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732437538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3732437538 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2316232879
Short name T160
Test name
Test status
Simulation time 159373595 ps
CPU time 4.01 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:58 PM PDT 24
Peak memory 214776 kb
Host smart-3ad3de0a-5d2d-43ef-ab17-57592c654b90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316232879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.23162
32879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2030246641
Short name T135
Test name
Test status
Simulation time 54078623 ps
CPU time 1.58 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 223112 kb
Host smart-385e9578-0b14-443a-83de-5c7c2f3a13a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030246641 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.2030246641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.324838116
Short name T1156
Test name
Test status
Simulation time 24877289 ps
CPU time 1.03 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206508 kb
Host smart-95d83c94-352e-445a-9dee-c95cac7713fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324838116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.324838116 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.382772244
Short name T108
Test name
Test status
Simulation time 24947487 ps
CPU time 0.79 seconds
Started Mar 28 12:36:45 PM PDT 24
Finished Mar 28 12:36:46 PM PDT 24
Peak memory 206576 kb
Host smart-f3d84727-2ca0-4447-9d91-4839950c3c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382772244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.382772244 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1962014806
Short name T1202
Test name
Test status
Simulation time 844198840 ps
CPU time 2.34 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 214948 kb
Host smart-a64a1bbf-eb5b-499d-ad74-17f0cd3bfc14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962014806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.1962014806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3927793415
Short name T1240
Test name
Test status
Simulation time 128252832 ps
CPU time 1.23 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 215340 kb
Host smart-4358bab4-2bb6-42b2-a2f3-ea7bc259c0b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927793415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.3927793415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1484594154
Short name T96
Test name
Test status
Simulation time 505734679 ps
CPU time 1.76 seconds
Started Mar 28 12:36:50 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 215276 kb
Host smart-10d0c74a-6dc0-4475-8630-71375fdc2e29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484594154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.1484594154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3147154825
Short name T1090
Test name
Test status
Simulation time 469159318 ps
CPU time 2.4 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 214948 kb
Host smart-d01a7e42-ebbf-41e8-9a85-aa5169b92ee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147154825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3147154825 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2908235317
Short name T163
Test name
Test status
Simulation time 382841460 ps
CPU time 4.83 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:59 PM PDT 24
Peak memory 206648 kb
Host smart-e45f8e89-08c9-4b15-948b-13f30a935bc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908235317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.29082
35317 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2790290049
Short name T1234
Test name
Test status
Simulation time 128684878 ps
CPU time 1.47 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 221648 kb
Host smart-df51ff0b-7649-4d79-844a-60e43144763d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790290049 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2790290049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1171040118
Short name T1209
Test name
Test status
Simulation time 17251796 ps
CPU time 0.9 seconds
Started Mar 28 12:36:51 PM PDT 24
Finished Mar 28 12:36:55 PM PDT 24
Peak memory 206532 kb
Host smart-6b5c9940-91cc-4cdd-b6e2-f51af435e7c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171040118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1171040118 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.3341255352
Short name T1154
Test name
Test status
Simulation time 10938302 ps
CPU time 0.73 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:54 PM PDT 24
Peak memory 206452 kb
Host smart-1fe1ee21-fa5d-4d86-9a73-3ca0b3b1d3ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341255352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3341255352 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.344803385
Short name T1206
Test name
Test status
Simulation time 265940993 ps
CPU time 1.54 seconds
Started Mar 28 12:36:47 PM PDT 24
Finished Mar 28 12:36:52 PM PDT 24
Peak memory 214904 kb
Host smart-3122047e-7fee-4950-9fd1-b39e7106ecdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344803385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_
outstanding.344803385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1881040701
Short name T1225
Test name
Test status
Simulation time 45716454 ps
CPU time 1.43 seconds
Started Mar 28 12:36:48 PM PDT 24
Finished Mar 28 12:36:51 PM PDT 24
Peak memory 215300 kb
Host smart-135a3a7c-99d5-427f-9f4a-30afaf7b9379
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881040701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.1881040701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3673102981
Short name T1193
Test name
Test status
Simulation time 287745913 ps
CPU time 1.94 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215248 kb
Host smart-0f98278a-a686-4484-8996-915a35ad6c7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673102981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.3673102981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.4126250360
Short name T1245
Test name
Test status
Simulation time 30695909 ps
CPU time 2.21 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:56 PM PDT 24
Peak memory 215016 kb
Host smart-831ce659-80ce-4b2c-bfd0-0b0fdceb3d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126250360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.4126250360 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.257307733
Short name T172
Test name
Test status
Simulation time 520595764 ps
CPU time 2.92 seconds
Started Mar 28 12:36:52 PM PDT 24
Finished Mar 28 12:36:57 PM PDT 24
Peak memory 214896 kb
Host smart-d2c1e3b8-9330-4a23-a748-84bee78b6091
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257307733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.257307
733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.3259422429
Short name T465
Test name
Test status
Simulation time 128038114 ps
CPU time 0.84 seconds
Started Mar 28 01:50:13 PM PDT 24
Finished Mar 28 01:50:14 PM PDT 24
Peak memory 205516 kb
Host smart-af32100c-eeb8-49fb-a916-a1f7e9175695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259422429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3259422429 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.1291305254
Short name T595
Test name
Test status
Simulation time 7897923925 ps
CPU time 75.73 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:51:25 PM PDT 24
Peak memory 229104 kb
Host smart-bdb7286b-618d-438a-a839-af333cc8fd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291305254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1291305254 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.872420239
Short name T645
Test name
Test status
Simulation time 16126039136 ps
CPU time 64.64 seconds
Started Mar 28 01:50:12 PM PDT 24
Finished Mar 28 01:51:18 PM PDT 24
Peak memory 225220 kb
Host smart-e6f8ddb7-476d-4fdd-a4e2-51ce8d807e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872420239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.872420239 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.872165589
Short name T450
Test name
Test status
Simulation time 9485916123 ps
CPU time 326.43 seconds
Started Mar 28 01:50:11 PM PDT 24
Finished Mar 28 01:55:37 PM PDT 24
Peak memory 227860 kb
Host smart-3a79dd15-c46d-4115-ba8b-251b7aaa89ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872165589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.872165589 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.1315783492
Short name T820
Test name
Test status
Simulation time 5154052948 ps
CPU time 34.55 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 01:50:45 PM PDT 24
Peak memory 221996 kb
Host smart-111f2e83-2c59-4d48-a583-ea3c7b72a8f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1315783492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1315783492 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.3848415860
Short name T675
Test name
Test status
Simulation time 884318983 ps
CPU time 4.73 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:50:14 PM PDT 24
Peak memory 216012 kb
Host smart-d886f3bc-f10b-43ce-aef9-c71bca7f5228
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3848415860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3848415860 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.3010494948
Short name T120
Test name
Test status
Simulation time 4114104112 ps
CPU time 28.58 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 01:50:37 PM PDT 24
Peak memory 216124 kb
Host smart-9a7f17a5-0d1a-4aa7-b646-5b788ef774fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010494948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3010494948 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.4186406542
Short name T100
Test name
Test status
Simulation time 897977783 ps
CPU time 21.71 seconds
Started Mar 28 01:50:07 PM PDT 24
Finished Mar 28 01:50:29 PM PDT 24
Peak memory 218684 kb
Host smart-5ebbacf6-d3d7-4848-b765-2c2a4ebcdee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186406542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.4186406542 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.2355271428
Short name T86
Test name
Test status
Simulation time 3859132691 ps
CPU time 313.22 seconds
Started Mar 28 01:50:12 PM PDT 24
Finished Mar 28 01:55:25 PM PDT 24
Peak memory 265228 kb
Host smart-315504d8-222f-48b2-b51d-56e7ea246161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355271428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.2355271428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.3655620379
Short name T942
Test name
Test status
Simulation time 1588142993 ps
CPU time 4.58 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:50:14 PM PDT 24
Peak memory 207720 kb
Host smart-b677f911-0afd-4ee7-a023-011167387c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655620379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3655620379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.562355623
Short name T84
Test name
Test status
Simulation time 51270456 ps
CPU time 1.34 seconds
Started Mar 28 01:50:12 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 215992 kb
Host smart-beb6d059-6f9f-42dc-b1d4-8c4cd5948d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562355623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.562355623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.1082328999
Short name T936
Test name
Test status
Simulation time 162084271791 ps
CPU time 928.34 seconds
Started Mar 28 01:50:13 PM PDT 24
Finished Mar 28 02:05:42 PM PDT 24
Peak memory 297776 kb
Host smart-a5bd7c88-0611-43f8-b65b-6c34bb6d2c8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082328999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.1082328999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.4128110227
Short name T47
Test name
Test status
Simulation time 76770606186 ps
CPU time 256.45 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 01:54:26 PM PDT 24
Peak memory 246596 kb
Host smart-c089dc7e-d6c2-47e3-8765-6e3093dbfd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128110227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.4128110227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.1373785300
Short name T10
Test name
Test status
Simulation time 22871265610 ps
CPU time 29.72 seconds
Started Mar 28 01:50:11 PM PDT 24
Finished Mar 28 01:50:41 PM PDT 24
Peak memory 244144 kb
Host smart-d4e7dd91-039b-4b92-ba68-c5538776f02b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373785300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1373785300 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.2394459092
Short name T216
Test name
Test status
Simulation time 731484010 ps
CPU time 56.54 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:51:06 PM PDT 24
Peak memory 223172 kb
Host smart-c194e539-09d9-4025-a6e0-217a9b97de8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394459092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2394459092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.934185413
Short name T661
Test name
Test status
Simulation time 835889923 ps
CPU time 10.73 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 01:50:20 PM PDT 24
Peak memory 218244 kb
Host smart-b6b0f645-33bd-418d-8891-e329b3cf4d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934185413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.934185413 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.3893618567
Short name T364
Test name
Test status
Simulation time 174021521312 ps
CPU time 1260.45 seconds
Started Mar 28 01:50:12 PM PDT 24
Finished Mar 28 02:11:14 PM PDT 24
Peak memory 367044 kb
Host smart-75785bee-830a-4739-9d7e-acedecd92ae3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3893618567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3893618567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.1227682516
Short name T951
Test name
Test status
Simulation time 288997605 ps
CPU time 4.78 seconds
Started Mar 28 01:50:07 PM PDT 24
Finished Mar 28 01:50:12 PM PDT 24
Peak memory 216112 kb
Host smart-66302e04-1615-4ceb-a143-c2b2572751d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227682516 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.1227682516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.779042707
Short name T1088
Test name
Test status
Simulation time 69130762 ps
CPU time 4.05 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 216092 kb
Host smart-6ed01564-06b0-4645-9c42-5daadfa435f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779042707 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.kmac_test_vectors_kmac_xof.779042707 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.1281960771
Short name T210
Test name
Test status
Simulation time 67193651213 ps
CPU time 1875.18 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 02:21:25 PM PDT 24
Peak memory 390616 kb
Host smart-693c877b-5100-46d3-8724-5c05f7145fca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1281960771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1281960771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.155526344
Short name T499
Test name
Test status
Simulation time 433843573574 ps
CPU time 1859.64 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 02:21:09 PM PDT 24
Peak memory 372532 kb
Host smart-e7c347b7-dd2c-4033-ae6e-5ff2da130a03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=155526344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.155526344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.1196246190
Short name T597
Test name
Test status
Simulation time 13210256519 ps
CPU time 983.95 seconds
Started Mar 28 01:50:05 PM PDT 24
Finished Mar 28 02:06:30 PM PDT 24
Peak memory 326364 kb
Host smart-44e2ea57-066c-4a98-be46-41d37cab7f1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1196246190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1196246190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.1456659357
Short name T1047
Test name
Test status
Simulation time 368543346095 ps
CPU time 989.71 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 02:06:40 PM PDT 24
Peak memory 297944 kb
Host smart-84e16d0b-6461-4b5c-a564-25151179d1b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1456659357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1456659357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.1131829875
Short name T420
Test name
Test status
Simulation time 181009028927 ps
CPU time 4705 seconds
Started Mar 28 01:50:07 PM PDT 24
Finished Mar 28 03:08:33 PM PDT 24
Peak memory 648884 kb
Host smart-f727dab4-516c-4eff-8325-46c0df87de42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1131829875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1131829875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.2864438324
Short name T684
Test name
Test status
Simulation time 1205811583618 ps
CPU time 4432.31 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 03:04:02 PM PDT 24
Peak memory 564060 kb
Host smart-da411601-26de-4414-b8e0-f1336a962282
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2864438324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2864438324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.1392408329
Short name T658
Test name
Test status
Simulation time 20979889 ps
CPU time 0.88 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 01:50:12 PM PDT 24
Peak memory 205548 kb
Host smart-c46c1dee-b8cc-44ce-a59c-608aa8ba7f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392408329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1392408329 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.4076760327
Short name T119
Test name
Test status
Simulation time 3767053713 ps
CPU time 218.14 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 01:53:46 PM PDT 24
Peak memory 244316 kb
Host smart-e8d85a54-426e-408a-8fb0-888ac93125a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076760327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.4076760327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.2190952435
Short name T408
Test name
Test status
Simulation time 14479849242 ps
CPU time 109.46 seconds
Started Mar 28 01:50:12 PM PDT 24
Finished Mar 28 01:52:02 PM PDT 24
Peak memory 232636 kb
Host smart-dc55f332-d467-440f-97ed-e175fd7c77ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190952435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.2190952435 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.4259193157
Short name T954
Test name
Test status
Simulation time 6248405333 ps
CPU time 547.21 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:59:17 PM PDT 24
Peak memory 231300 kb
Host smart-5622d2bc-9818-426d-9a4f-96a1ed7fda05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259193157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.4259193157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3100925818
Short name T923
Test name
Test status
Simulation time 421552131 ps
CPU time 30.91 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:50:40 PM PDT 24
Peak memory 219908 kb
Host smart-8bf38b1c-6220-4467-b8d2-f0c83d78fd75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3100925818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3100925818 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.3458642949
Short name T934
Test name
Test status
Simulation time 94003092 ps
CPU time 6.34 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 224056 kb
Host smart-c18f5409-d520-4cd9-9f6a-b3925d7714b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3458642949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3458642949 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.2952852015
Short name T442
Test name
Test status
Simulation time 6654796226 ps
CPU time 35.24 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 01:50:43 PM PDT 24
Peak memory 216140 kb
Host smart-7b5dcac7-5c95-4280-a6e8-f671369fa7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952852015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2952852015 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.2418415632
Short name T990
Test name
Test status
Simulation time 8115651430 ps
CPU time 77.3 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 01:51:25 PM PDT 24
Peak memory 228804 kb
Host smart-302a91dd-cb1f-40a4-ae98-55950ca0fb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418415632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2418415632 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.1414665630
Short name T669
Test name
Test status
Simulation time 10152352713 ps
CPU time 284.64 seconds
Started Mar 28 01:50:11 PM PDT 24
Finished Mar 28 01:54:57 PM PDT 24
Peak memory 257108 kb
Host smart-0fc5f69d-a75b-444c-adc5-ed9483c1e7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414665630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1414665630 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.119410774
Short name T827
Test name
Test status
Simulation time 1993709232 ps
CPU time 3.43 seconds
Started Mar 28 01:50:12 PM PDT 24
Finished Mar 28 01:50:17 PM PDT 24
Peak memory 207756 kb
Host smart-f2f0f06c-5dfb-4060-8979-99735c7eaf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119410774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.119410774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.1393629424
Short name T932
Test name
Test status
Simulation time 34214645 ps
CPU time 1.22 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 01:50:10 PM PDT 24
Peak memory 215976 kb
Host smart-4efdc061-c05d-4bd9-bb0d-efc5543e2ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393629424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1393629424 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.4038234038
Short name T614
Test name
Test status
Simulation time 339789165885 ps
CPU time 1064.51 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 02:07:54 PM PDT 24
Peak memory 301080 kb
Host smart-d0cf5704-164d-4140-8d93-3ceb16d7bf2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038234038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.4038234038 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.4194114570
Short name T965
Test name
Test status
Simulation time 25875077707 ps
CPU time 334.23 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 01:55:44 PM PDT 24
Peak memory 247008 kb
Host smart-dd83a9c7-f80f-4e1a-9727-3f393a7fdf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194114570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.4194114570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.1902030774
Short name T68
Test name
Test status
Simulation time 1593212275 ps
CPU time 27.46 seconds
Started Mar 28 01:50:07 PM PDT 24
Finished Mar 28 01:50:35 PM PDT 24
Peak memory 242212 kb
Host smart-009413dc-c138-404a-a51c-0a0f029b69f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902030774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1902030774 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.3536673340
Short name T508
Test name
Test status
Simulation time 27511379983 ps
CPU time 304.52 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 01:55:15 PM PDT 24
Peak memory 242700 kb
Host smart-b04a50ad-60d6-4cfe-a38c-76ea09e98c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536673340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.3536673340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.376871714
Short name T729
Test name
Test status
Simulation time 465970263 ps
CPU time 11.03 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:50:20 PM PDT 24
Peak memory 222332 kb
Host smart-c06c3f15-4cd5-4c5d-ae97-e749561dc576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376871714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.376871714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.3857424695
Short name T24
Test name
Test status
Simulation time 1747235671 ps
CPU time 98.65 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 01:51:49 PM PDT 24
Peak memory 249188 kb
Host smart-10041ac2-d7dd-4943-b7ea-8fc676a367c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3857424695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3857424695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.946415935
Short name T257
Test name
Test status
Simulation time 171359688 ps
CPU time 4.4 seconds
Started Mar 28 01:50:12 PM PDT 24
Finished Mar 28 01:50:17 PM PDT 24
Peak memory 216136 kb
Host smart-bca0ce51-5e55-4355-a852-06953ac7ed2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946415935 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.kmac_test_vectors_kmac.946415935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2596642617
Short name T186
Test name
Test status
Simulation time 702521954 ps
CPU time 4.46 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 01:50:15 PM PDT 24
Peak memory 216196 kb
Host smart-821e5bfa-64d3-4ac3-b537-a74b72ac202d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596642617 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2596642617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.278537903
Short name T476
Test name
Test status
Simulation time 187546688216 ps
CPU time 1867.45 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 02:21:16 PM PDT 24
Peak memory 366880 kb
Host smart-41edc530-a744-422a-8db3-ff98032997ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=278537903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.278537903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.454411677
Short name T454
Test name
Test status
Simulation time 233262161447 ps
CPU time 1839.78 seconds
Started Mar 28 01:50:12 PM PDT 24
Finished Mar 28 02:20:52 PM PDT 24
Peak memory 371740 kb
Host smart-44956b0e-845b-4424-9247-b1d67481a234
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=454411677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.454411677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.3072146
Short name T334
Test name
Test status
Simulation time 28230468179 ps
CPU time 1129.16 seconds
Started Mar 28 01:50:08 PM PDT 24
Finished Mar 28 02:08:58 PM PDT 24
Peak memory 333284 kb
Host smart-6bbf97b6-0ea8-4de2-9b87-047bb46e30ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3072146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3072146 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.2535977393
Short name T200
Test name
Test status
Simulation time 64623217795 ps
CPU time 921.1 seconds
Started Mar 28 01:50:12 PM PDT 24
Finished Mar 28 02:05:33 PM PDT 24
Peak memory 292768 kb
Host smart-6834e622-7bca-4a60-996b-11410892ab49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2535977393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2535977393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.3941036981
Short name T497
Test name
Test status
Simulation time 513504126839 ps
CPU time 5351.16 seconds
Started Mar 28 01:50:10 PM PDT 24
Finished Mar 28 03:19:23 PM PDT 24
Peak memory 650788 kb
Host smart-a09e5d70-b580-445b-9625-8515a386336d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3941036981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3941036981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.2417243151
Short name T299
Test name
Test status
Simulation time 215921553506 ps
CPU time 4365.84 seconds
Started Mar 28 01:50:11 PM PDT 24
Finished Mar 28 03:02:58 PM PDT 24
Peak memory 557500 kb
Host smart-0ca6c0f0-d2ed-4a7b-94d2-1b1a38b2bee1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2417243151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2417243151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_burst_write.1343660685
Short name T534
Test name
Test status
Simulation time 8356759671 ps
CPU time 690.49 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 02:02:35 PM PDT 24
Peak memory 232908 kb
Host smart-e405affc-68d6-4480-8f7a-6ff3ea2bd00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343660685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1343660685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.3526440112
Short name T900
Test name
Test status
Simulation time 7209579175 ps
CPU time 40.76 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 01:52:02 PM PDT 24
Peak memory 225112 kb
Host smart-46543719-dc65-4fca-8187-fd58039c7413
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3526440112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3526440112 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.1975324668
Short name T947
Test name
Test status
Simulation time 876962061 ps
CPU time 32.28 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 01:51:53 PM PDT 24
Peak memory 224100 kb
Host smart-5129e9d3-f4c2-47bb-ab83-5410cee88bc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1975324668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1975324668 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.1595102236
Short name T902
Test name
Test status
Simulation time 9573398483 ps
CPU time 62.51 seconds
Started Mar 28 01:51:20 PM PDT 24
Finished Mar 28 01:52:23 PM PDT 24
Peak memory 227412 kb
Host smart-f7882f71-4c2f-4f49-9949-200d82104e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595102236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1595102236 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.3276325320
Short name T753
Test name
Test status
Simulation time 652895608 ps
CPU time 52.73 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 01:52:14 PM PDT 24
Peak memory 240624 kb
Host smart-bcc6c146-223a-4feb-b658-e6383e519341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276325320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3276325320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.3735726019
Short name T938
Test name
Test status
Simulation time 326671628 ps
CPU time 2.14 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 01:51:23 PM PDT 24
Peak memory 207260 kb
Host smart-b1633a74-d9c8-4165-afbc-e9c4c55e1ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735726019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3735726019 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.2253075528
Short name T710
Test name
Test status
Simulation time 36846424 ps
CPU time 1.43 seconds
Started Mar 28 01:51:22 PM PDT 24
Finished Mar 28 01:51:24 PM PDT 24
Peak memory 218492 kb
Host smart-b4ada230-eaf0-426c-aec6-0a313ed6cef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253075528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2253075528 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.13158403
Short name T286
Test name
Test status
Simulation time 79697952946 ps
CPU time 358.03 seconds
Started Mar 28 01:51:09 PM PDT 24
Finished Mar 28 01:57:07 PM PDT 24
Peak memory 252192 kb
Host smart-7e0e7b6b-6381-427e-9b8f-c3125be50e4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13158403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and
_output.13158403 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.2988072508
Short name T949
Test name
Test status
Simulation time 3304463251 ps
CPU time 38.58 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:51:43 PM PDT 24
Peak memory 222216 kb
Host smart-f0ab758f-eca4-4cd6-980a-5c85ab166cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988072508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2988072508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.1308591117
Short name T993
Test name
Test status
Simulation time 2497873898 ps
CPU time 31.11 seconds
Started Mar 28 01:51:09 PM PDT 24
Finished Mar 28 01:51:40 PM PDT 24
Peak memory 218892 kb
Host smart-a4917667-8df5-42a1-bd01-c24e5b6dc1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308591117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1308591117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.3227812108
Short name T470
Test name
Test status
Simulation time 7693816241 ps
CPU time 171.52 seconds
Started Mar 28 01:51:22 PM PDT 24
Finished Mar 28 01:54:14 PM PDT 24
Peak memory 230332 kb
Host smart-c64f59da-8fd8-43e2-8979-b9502bc7194d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3227812108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3227812108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.2507555196
Short name T893
Test name
Test status
Simulation time 256282644 ps
CPU time 3.86 seconds
Started Mar 28 01:51:23 PM PDT 24
Finished Mar 28 01:51:27 PM PDT 24
Peak memory 216092 kb
Host smart-2cffcb19-5355-441f-9b21-6bfa000f996a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507555196 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.2507555196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.491284286
Short name T1085
Test name
Test status
Simulation time 1484136275 ps
CPU time 4.38 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:51:23 PM PDT 24
Peak memory 216176 kb
Host smart-ae1283a1-af3a-44b0-98f8-44eb6c5ad0f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491284286 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.kmac_test_vectors_kmac_xof.491284286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.2834381093
Short name T924
Test name
Test status
Simulation time 37927622771 ps
CPU time 1566.88 seconds
Started Mar 28 01:51:09 PM PDT 24
Finished Mar 28 02:17:16 PM PDT 24
Peak memory 387808 kb
Host smart-0883013c-55bb-411c-a8f9-e24da3463706
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2834381093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.2834381093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.1959618771
Short name T205
Test name
Test status
Simulation time 157669733523 ps
CPU time 1756.08 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 02:20:25 PM PDT 24
Peak memory 392892 kb
Host smart-fe817534-d674-4622-a959-77cd39f90983
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1959618771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.1959618771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.238955836
Short name T1042
Test name
Test status
Simulation time 50203101252 ps
CPU time 1156.71 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 02:10:27 PM PDT 24
Peak memory 333952 kb
Host smart-bd121320-c0d5-42f3-8bf8-1aa11c927669
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=238955836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.238955836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.3537862271
Short name T608
Test name
Test status
Simulation time 815227599715 ps
CPU time 1251.91 seconds
Started Mar 28 01:51:04 PM PDT 24
Finished Mar 28 02:11:56 PM PDT 24
Peak memory 295996 kb
Host smart-3b576bf5-0f1b-4d5f-8b04-2fd033e055d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3537862271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.3537862271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.226824067
Short name T724
Test name
Test status
Simulation time 51822653772 ps
CPU time 4108.85 seconds
Started Mar 28 01:51:22 PM PDT 24
Finished Mar 28 02:59:52 PM PDT 24
Peak memory 649012 kb
Host smart-a0ef7033-606f-46b2-9fe9-0b8a2f09fb0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=226824067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.226824067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.549848917
Short name T715
Test name
Test status
Simulation time 43597325898 ps
CPU time 3518.67 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 02:50:00 PM PDT 24
Peak memory 568856 kb
Host smart-d77d008d-cfcb-470b-885b-7aa0c3d935aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=549848917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.549848917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.4222080857
Short name T667
Test name
Test status
Simulation time 29518719 ps
CPU time 0.79 seconds
Started Mar 28 01:51:25 PM PDT 24
Finished Mar 28 01:51:26 PM PDT 24
Peak memory 205540 kb
Host smart-463cda74-86bd-492b-9141-2736a0f2ded0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222080857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.4222080857 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.3422712282
Short name T979
Test name
Test status
Simulation time 6107009501 ps
CPU time 104.01 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:53:03 PM PDT 24
Peak memory 230428 kb
Host smart-56b9e585-88cb-4075-8f80-eb092fcaf664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422712282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3422712282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.1077973900
Short name T996
Test name
Test status
Simulation time 493023806 ps
CPU time 40.26 seconds
Started Mar 28 01:51:22 PM PDT 24
Finished Mar 28 01:52:02 PM PDT 24
Peak memory 236640 kb
Host smart-4dee89fd-9d3f-4bb5-b0eb-664447102a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077973900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.1077973900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.221469338
Short name T256
Test name
Test status
Simulation time 96982019 ps
CPU time 1.95 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 01:51:23 PM PDT 24
Peak memory 215964 kb
Host smart-780d3385-bdb3-4b5c-8a58-f5bfde3d8862
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=221469338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.221469338 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.326965754
Short name T43
Test name
Test status
Simulation time 216113825 ps
CPU time 17.07 seconds
Started Mar 28 01:51:18 PM PDT 24
Finished Mar 28 01:51:36 PM PDT 24
Peak memory 224148 kb
Host smart-e3186633-b90f-4eb0-ada9-11034cf6d935
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=326965754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.326965754 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.2444656947
Short name T398
Test name
Test status
Simulation time 2544470302 ps
CPU time 57.17 seconds
Started Mar 28 01:51:22 PM PDT 24
Finished Mar 28 01:52:20 PM PDT 24
Peak memory 225644 kb
Host smart-55ad7dad-8453-4831-a629-9c0f69a32ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444656947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.2444656947 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.2115494001
Short name T328
Test name
Test status
Simulation time 1064901344 ps
CPU time 27.35 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 01:51:48 PM PDT 24
Peak memory 235688 kb
Host smart-22d992b6-26e8-4b31-b38a-531efe513855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115494001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2115494001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.631242867
Short name T350
Test name
Test status
Simulation time 769091759 ps
CPU time 4.04 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 01:51:25 PM PDT 24
Peak memory 207796 kb
Host smart-05572148-cdd2-47d3-bfb6-c4dd59ec7e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631242867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.631242867 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.2430020032
Short name T48
Test name
Test status
Simulation time 2795095446 ps
CPU time 18.39 seconds
Started Mar 28 01:51:25 PM PDT 24
Finished Mar 28 01:51:43 PM PDT 24
Peak memory 221380 kb
Host smart-f3fca575-6743-4072-a5fd-d61c72f618ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430020032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2430020032 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1805968810
Short name T547
Test name
Test status
Simulation time 1871839128 ps
CPU time 156.15 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 01:53:57 PM PDT 24
Peak memory 240632 kb
Host smart-7894b267-00d9-4a7d-9527-6b84dc8cda7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805968810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1805968810 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.2648394601
Short name T518
Test name
Test status
Simulation time 4284340170 ps
CPU time 362.35 seconds
Started Mar 28 01:51:23 PM PDT 24
Finished Mar 28 01:57:26 PM PDT 24
Peak memory 247924 kb
Host smart-abbc17f2-250b-47ea-b845-43243c9bc6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648394601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2648394601 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.3363769415
Short name T343
Test name
Test status
Simulation time 4028110942 ps
CPU time 63.72 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:52:23 PM PDT 24
Peak memory 217560 kb
Host smart-2b771203-6cff-483e-9232-c0d53e22282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363769415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3363769415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.3644922577
Short name T371
Test name
Test status
Simulation time 251102377310 ps
CPU time 236.63 seconds
Started Mar 28 01:51:20 PM PDT 24
Finished Mar 28 01:55:16 PM PDT 24
Peak memory 267312 kb
Host smart-e9cb08d4-2d8a-49f3-8684-077785850179
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3644922577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3644922577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_stress_all_with_rand_reset.4218081018
Short name T114
Test name
Test status
Simulation time 100566912409 ps
CPU time 660.8 seconds
Started Mar 28 01:51:22 PM PDT 24
Finished Mar 28 02:02:23 PM PDT 24
Peak memory 249512 kb
Host smart-c15241bf-44ef-4ce8-953e-141417efc8bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4218081018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all_with_rand_reset.4218081018 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.4163368849
Short name T569
Test name
Test status
Simulation time 254202558 ps
CPU time 4.23 seconds
Started Mar 28 01:51:20 PM PDT 24
Finished Mar 28 01:51:24 PM PDT 24
Peak memory 216064 kb
Host smart-7c3f410d-f701-4cf2-b4ba-11c89fc91185
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163368849 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.4163368849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.2910056677
Short name T118
Test name
Test status
Simulation time 382859594 ps
CPU time 4.32 seconds
Started Mar 28 01:51:24 PM PDT 24
Finished Mar 28 01:51:29 PM PDT 24
Peak memory 216136 kb
Host smart-53a6ef93-88e0-4ceb-8d21-d32ca15027d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910056677 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.2910056677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.240937459
Short name T196
Test name
Test status
Simulation time 133577702683 ps
CPU time 1657.92 seconds
Started Mar 28 01:51:24 PM PDT 24
Finished Mar 28 02:19:02 PM PDT 24
Peak memory 389728 kb
Host smart-aa9cba2b-7dad-4d6f-978a-277dd55504bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=240937459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.240937459 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.605343037
Short name T248
Test name
Test status
Simulation time 17982745573 ps
CPU time 1468.73 seconds
Started Mar 28 01:51:20 PM PDT 24
Finished Mar 28 02:15:49 PM PDT 24
Peak memory 375424 kb
Host smart-a1c4c1c5-0ae6-46e2-8307-0dbeaf0cae4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=605343037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.605343037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.2787953717
Short name T203
Test name
Test status
Simulation time 244476549429 ps
CPU time 1368.23 seconds
Started Mar 28 01:51:22 PM PDT 24
Finished Mar 28 02:14:11 PM PDT 24
Peak memory 325696 kb
Host smart-2398ddea-3d3e-41fa-87c6-fa72ebf8d040
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2787953717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.2787953717 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.1348452457
Short name T387
Test name
Test status
Simulation time 18828079195 ps
CPU time 783.83 seconds
Started Mar 28 01:51:20 PM PDT 24
Finished Mar 28 02:04:24 PM PDT 24
Peak memory 293620 kb
Host smart-c4d154bc-1012-4df7-880f-5e142c363d6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1348452457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.1348452457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.162736160
Short name T654
Test name
Test status
Simulation time 269688351835 ps
CPU time 5197.77 seconds
Started Mar 28 01:51:22 PM PDT 24
Finished Mar 28 03:18:01 PM PDT 24
Peak memory 648772 kb
Host smart-68fa38ee-aaf8-49f7-8839-c7bdf8748455
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=162736160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.162736160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.1485493763
Short name T1009
Test name
Test status
Simulation time 91735203593 ps
CPU time 3347.18 seconds
Started Mar 28 01:51:21 PM PDT 24
Finished Mar 28 02:47:09 PM PDT 24
Peak memory 557568 kb
Host smart-9a0485ab-6365-4964-b86e-3ddc85cb0741
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1485493763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.1485493763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.4202365381
Short name T388
Test name
Test status
Simulation time 23475974 ps
CPU time 0.79 seconds
Started Mar 28 01:51:37 PM PDT 24
Finished Mar 28 01:51:38 PM PDT 24
Peak memory 205612 kb
Host smart-ed85bcb4-5158-4b45-af2d-41cbe132d9f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202365381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.4202365381 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.2541810150
Short name T74
Test name
Test status
Simulation time 17519063896 ps
CPU time 253.85 seconds
Started Mar 28 01:51:40 PM PDT 24
Finished Mar 28 01:55:54 PM PDT 24
Peak memory 243348 kb
Host smart-47212026-7893-4d4d-8460-33da3f4e905d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541810150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2541810150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.1047654844
Short name T441
Test name
Test status
Simulation time 7498282565 ps
CPU time 584.26 seconds
Started Mar 28 01:51:35 PM PDT 24
Finished Mar 28 02:01:19 PM PDT 24
Peak memory 232744 kb
Host smart-2f30d9df-c15c-429f-8dc0-160f213d99a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047654844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1047654844 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.1246340835
Short name T851
Test name
Test status
Simulation time 480596740 ps
CPU time 31.94 seconds
Started Mar 28 01:51:38 PM PDT 24
Finished Mar 28 01:52:10 PM PDT 24
Peak memory 224004 kb
Host smart-03deb060-4f13-484b-9f3e-d7f5d884c5b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1246340835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1246340835 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.1405994721
Short name T477
Test name
Test status
Simulation time 277216684 ps
CPU time 9.2 seconds
Started Mar 28 01:51:38 PM PDT 24
Finished Mar 28 01:51:47 PM PDT 24
Peak memory 218952 kb
Host smart-676862ff-65ad-4a6d-ba46-4f62f550ae4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1405994721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1405994721 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_error.1363802698
Short name T821
Test name
Test status
Simulation time 8308245891 ps
CPU time 169.33 seconds
Started Mar 28 01:51:39 PM PDT 24
Finished Mar 28 01:54:28 PM PDT 24
Peak memory 248904 kb
Host smart-92f1099b-c385-4bd8-8aee-e4b158b089ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363802698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1363802698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.678694489
Short name T59
Test name
Test status
Simulation time 892905405 ps
CPU time 4.87 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 01:51:41 PM PDT 24
Peak memory 207648 kb
Host smart-69b7bfa1-05c8-4bee-b10d-be3ebc0d2654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678694489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.678694489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.1086181215
Short name T32
Test name
Test status
Simulation time 173959672 ps
CPU time 1.36 seconds
Started Mar 28 01:51:37 PM PDT 24
Finished Mar 28 01:51:38 PM PDT 24
Peak memory 216940 kb
Host smart-af8e4e5a-3f98-4f00-88d7-e8ae9f7b508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086181215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1086181215 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.2505017148
Short name T502
Test name
Test status
Simulation time 85095491703 ps
CPU time 2248.78 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 02:28:49 PM PDT 24
Peak memory 439992 kb
Host smart-f16fe347-b1ae-4b01-a58c-5503f8d923cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505017148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.2505017148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.3740410492
Short name T694
Test name
Test status
Simulation time 25358924685 ps
CPU time 259.75 seconds
Started Mar 28 01:51:23 PM PDT 24
Finished Mar 28 01:55:43 PM PDT 24
Peak memory 239744 kb
Host smart-c71c7f1a-0762-4912-8e8a-31783ffb1172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740410492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3740410492 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.1039663829
Short name T746
Test name
Test status
Simulation time 79472079 ps
CPU time 1.43 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:51:21 PM PDT 24
Peak memory 219316 kb
Host smart-e5b31c78-8840-4521-96c9-5b2ca99913d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039663829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1039663829 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.4233611386
Short name T298
Test name
Test status
Simulation time 176798703869 ps
CPU time 589.53 seconds
Started Mar 28 01:51:37 PM PDT 24
Finished Mar 28 02:01:27 PM PDT 24
Peak memory 287380 kb
Host smart-905a113d-fc49-4721-811e-12b75742f1fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4233611386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.4233611386 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_stress_all_with_rand_reset.1812551468
Short name T110
Test name
Test status
Simulation time 62257393306 ps
CPU time 516.13 seconds
Started Mar 28 01:51:39 PM PDT 24
Finished Mar 28 02:00:15 PM PDT 24
Peak memory 266592 kb
Host smart-2616ed95-a954-415c-9c05-99e24cbe3333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812551468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all_with_rand_reset.1812551468 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.3515715830
Short name T193
Test name
Test status
Simulation time 190259947 ps
CPU time 5.01 seconds
Started Mar 28 01:51:40 PM PDT 24
Finished Mar 28 01:51:45 PM PDT 24
Peak memory 216092 kb
Host smart-94ce4028-9876-4c86-87f0-98892b09883f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515715830 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.3515715830 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.4169942260
Short name T609
Test name
Test status
Simulation time 123069554 ps
CPU time 4.15 seconds
Started Mar 28 01:51:37 PM PDT 24
Finished Mar 28 01:51:41 PM PDT 24
Peak memory 216116 kb
Host smart-1713e419-018c-4eda-87cf-e23e1f2130b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169942260 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.4169942260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.956939725
Short name T302
Test name
Test status
Simulation time 39743743953 ps
CPU time 1577.83 seconds
Started Mar 28 01:51:37 PM PDT 24
Finished Mar 28 02:17:56 PM PDT 24
Peak memory 389216 kb
Host smart-a87a232d-e1ce-4605-8857-85141b6a05ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=956939725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.956939725 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.443572933
Short name T439
Test name
Test status
Simulation time 345057969188 ps
CPU time 1695.69 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 02:19:52 PM PDT 24
Peak memory 374232 kb
Host smart-048dfa07-03fe-4a2f-8b13-8c058fea2486
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=443572933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.443572933 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.68025732
Short name T1014
Test name
Test status
Simulation time 61283031108 ps
CPU time 1104.02 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 02:10:00 PM PDT 24
Peak memory 332424 kb
Host smart-321d207a-2c1d-4cd2-a820-b8a98cd1a56d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=68025732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.68025732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.3581981277
Short name T926
Test name
Test status
Simulation time 68331508144 ps
CPU time 908.45 seconds
Started Mar 28 01:51:37 PM PDT 24
Finished Mar 28 02:06:45 PM PDT 24
Peak memory 299656 kb
Host smart-e2ffa2c1-fc19-49e7-8881-4ce5a54cd066
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3581981277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.3581981277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.1349500733
Short name T209
Test name
Test status
Simulation time 266674706310 ps
CPU time 4269.68 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 03:02:46 PM PDT 24
Peak memory 646756 kb
Host smart-4c377ca5-598b-4a22-834a-c2b745b8276f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1349500733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.1349500733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.3491638670
Short name T695
Test name
Test status
Simulation time 1168615020600 ps
CPU time 4212.35 seconds
Started Mar 28 01:51:38 PM PDT 24
Finished Mar 28 03:01:51 PM PDT 24
Peak memory 556292 kb
Host smart-c593d4f7-6469-487e-a73c-de03ee66c7fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3491638670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.3491638670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.1600606683
Short name T484
Test name
Test status
Simulation time 13255672 ps
CPU time 0.76 seconds
Started Mar 28 01:51:54 PM PDT 24
Finished Mar 28 01:51:55 PM PDT 24
Peak memory 205544 kb
Host smart-1dba4c7c-ed57-4b34-882a-5ea95854bb72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600606683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1600606683 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_burst_write.3081069832
Short name T633
Test name
Test status
Simulation time 11622990078 ps
CPU time 401.94 seconds
Started Mar 28 01:51:39 PM PDT 24
Finished Mar 28 01:58:21 PM PDT 24
Peak memory 227792 kb
Host smart-315dffc6-e4bc-4adb-9d31-e93144461caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081069832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.3081069832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.714944848
Short name T215
Test name
Test status
Simulation time 20842773868 ps
CPU time 36.52 seconds
Started Mar 28 01:52:00 PM PDT 24
Finished Mar 28 01:52:36 PM PDT 24
Peak memory 224188 kb
Host smart-e44caa6e-8422-4165-bff1-db68f94a7994
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=714944848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.714944848 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.2150319346
Short name T679
Test name
Test status
Simulation time 1007046501 ps
CPU time 25.33 seconds
Started Mar 28 01:51:55 PM PDT 24
Finished Mar 28 01:52:21 PM PDT 24
Peak memory 219392 kb
Host smart-d8c4b8ad-1cd0-49b3-8af3-e404de0db032
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2150319346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2150319346 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.219471897
Short name T275
Test name
Test status
Simulation time 16817047733 ps
CPU time 115.73 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 01:53:32 PM PDT 24
Peak memory 232916 kb
Host smart-e695e2c8-8274-46f7-b5fd-877bf1b84a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219471897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.219471897 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2246301062
Short name T809
Test name
Test status
Simulation time 45081695097 ps
CPU time 319.27 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 01:56:55 PM PDT 24
Peak memory 256612 kb
Host smart-671944a8-d480-4c4c-b87f-7132a0721bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246301062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2246301062 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.3436534788
Short name T479
Test name
Test status
Simulation time 2687817612 ps
CPU time 1.75 seconds
Started Mar 28 01:51:40 PM PDT 24
Finished Mar 28 01:51:42 PM PDT 24
Peak memory 207692 kb
Host smart-25a7d8d2-910d-4360-8bbb-762537287623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436534788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3436534788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.3782411407
Short name T4
Test name
Test status
Simulation time 93178772 ps
CPU time 1.31 seconds
Started Mar 28 01:51:53 PM PDT 24
Finished Mar 28 01:51:55 PM PDT 24
Peak memory 220928 kb
Host smart-cce9c1bf-bc4b-4e54-a987-9874c5e4bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782411407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3782411407 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.2976665263
Short name T566
Test name
Test status
Simulation time 95504806040 ps
CPU time 2314.65 seconds
Started Mar 28 01:51:35 PM PDT 24
Finished Mar 28 02:30:10 PM PDT 24
Peak memory 426008 kb
Host smart-45ebddc7-a628-49ae-853c-1c5b8056449b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976665263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.2976665263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3713349432
Short name T832
Test name
Test status
Simulation time 11959412926 ps
CPU time 306.62 seconds
Started Mar 28 01:51:38 PM PDT 24
Finished Mar 28 01:56:45 PM PDT 24
Peak memory 245564 kb
Host smart-578b1462-a843-4944-a21c-2338b0924d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713349432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3713349432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.3777008283
Short name T957
Test name
Test status
Simulation time 128269814 ps
CPU time 3.83 seconds
Started Mar 28 01:51:33 PM PDT 24
Finished Mar 28 01:51:37 PM PDT 24
Peak memory 216080 kb
Host smart-9f0d38db-531c-4440-8d38-60bedd6c4a1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777008283 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.3777008283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.1615228115
Short name T817
Test name
Test status
Simulation time 243404960 ps
CPU time 3.91 seconds
Started Mar 28 01:51:38 PM PDT 24
Finished Mar 28 01:51:42 PM PDT 24
Peak memory 216160 kb
Host smart-5a444849-4522-4f41-a59a-559cc7f404c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615228115 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.1615228115 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.4159420812
Short name T63
Test name
Test status
Simulation time 65812506396 ps
CPU time 1876.78 seconds
Started Mar 28 01:51:43 PM PDT 24
Finished Mar 28 02:23:00 PM PDT 24
Peak memory 390304 kb
Host smart-c760bc32-664e-42ce-8c23-1855eefd9ba9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4159420812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.4159420812 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.2170940513
Short name T918
Test name
Test status
Simulation time 161800469762 ps
CPU time 1403.07 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 02:15:00 PM PDT 24
Peak memory 375964 kb
Host smart-d127a954-73ec-4581-946d-5af0734bb959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2170940513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2170940513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.1671528678
Short name T417
Test name
Test status
Simulation time 74450866515 ps
CPU time 1584.17 seconds
Started Mar 28 01:51:38 PM PDT 24
Finished Mar 28 02:18:03 PM PDT 24
Peak memory 340068 kb
Host smart-648cb159-5967-4271-be64-e0409e2c680f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1671528678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.1671528678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.906005947
Short name T250
Test name
Test status
Simulation time 33733301621 ps
CPU time 936.9 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 02:07:13 PM PDT 24
Peak memory 293892 kb
Host smart-96939eb0-6844-4321-831a-832fbc851835
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=906005947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.906005947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.3691251499
Short name T198
Test name
Test status
Simulation time 519594062318 ps
CPU time 5316.45 seconds
Started Mar 28 01:51:34 PM PDT 24
Finished Mar 28 03:20:12 PM PDT 24
Peak memory 663416 kb
Host smart-ade6fe33-1426-4c46-99e4-da51445739dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3691251499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.3691251499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.1800658902
Short name T1056
Test name
Test status
Simulation time 151619148059 ps
CPU time 4356.12 seconds
Started Mar 28 01:51:36 PM PDT 24
Finished Mar 28 03:04:13 PM PDT 24
Peak memory 571260 kb
Host smart-a6b0cfd7-d998-4512-ac71-6c4ad8ed8349
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1800658902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.1800658902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.1130593538
Short name T592
Test name
Test status
Simulation time 14813875 ps
CPU time 0.77 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 01:51:58 PM PDT 24
Peak memory 205576 kb
Host smart-dad3c7fa-9790-4b37-9be2-886eadfd7417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130593538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1130593538 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.2236477754
Short name T351
Test name
Test status
Simulation time 12488185335 ps
CPU time 121.94 seconds
Started Mar 28 01:51:54 PM PDT 24
Finished Mar 28 01:53:57 PM PDT 24
Peak memory 233448 kb
Host smart-6c0670c0-b1fb-4137-acb3-a56bae5548d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236477754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2236477754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.2205039111
Short name T178
Test name
Test status
Simulation time 2542784888 ps
CPU time 185 seconds
Started Mar 28 01:51:56 PM PDT 24
Finished Mar 28 01:55:02 PM PDT 24
Peak memory 225332 kb
Host smart-cbf297ea-23fa-4337-9abf-d98ba2845c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205039111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2205039111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.1398408176
Short name T806
Test name
Test status
Simulation time 192574563 ps
CPU time 13.24 seconds
Started Mar 28 01:51:58 PM PDT 24
Finished Mar 28 01:52:11 PM PDT 24
Peak memory 216980 kb
Host smart-fd610351-2f18-4324-88f8-38a5214a28d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1398408176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1398408176 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.2561029883
Short name T355
Test name
Test status
Simulation time 2806844167 ps
CPU time 28.18 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 01:52:25 PM PDT 24
Peak memory 225220 kb
Host smart-967c355d-0a5d-4f92-8365-d9583420bc29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2561029883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2561029883 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.345045909
Short name T491
Test name
Test status
Simulation time 13928120250 ps
CPU time 215.41 seconds
Started Mar 28 01:51:56 PM PDT 24
Finished Mar 28 01:55:32 PM PDT 24
Peak memory 240356 kb
Host smart-1cf7f426-a500-48bf-837e-d5b1e3105f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345045909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.345045909 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.1349457369
Short name T935
Test name
Test status
Simulation time 15237204946 ps
CPU time 164.12 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 01:54:41 PM PDT 24
Peak memory 249000 kb
Host smart-fc616f18-c509-4dfd-a219-422c3e4aedde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349457369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1349457369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.2490151909
Short name T980
Test name
Test status
Simulation time 1400542081 ps
CPU time 4.13 seconds
Started Mar 28 01:51:56 PM PDT 24
Finished Mar 28 01:52:00 PM PDT 24
Peak memory 207656 kb
Host smart-db785abb-2e6f-4ce6-aa2b-d1d97036b5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490151909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2490151909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.2471272875
Short name T587
Test name
Test status
Simulation time 69889872 ps
CPU time 1.27 seconds
Started Mar 28 01:51:58 PM PDT 24
Finished Mar 28 01:51:59 PM PDT 24
Peak memory 216056 kb
Host smart-149e3d5c-7db9-48a6-96e0-1258a16a981c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471272875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2471272875 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.3503839743
Short name T2
Test name
Test status
Simulation time 48046105051 ps
CPU time 444.9 seconds
Started Mar 28 01:51:53 PM PDT 24
Finished Mar 28 01:59:18 PM PDT 24
Peak memory 256936 kb
Host smart-9ac0e4e0-bd94-460d-93e2-5c0a7d8b5255
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503839743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.3503839743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.599754124
Short name T472
Test name
Test status
Simulation time 3167213719 ps
CPU time 88.7 seconds
Started Mar 28 01:51:54 PM PDT 24
Finished Mar 28 01:53:23 PM PDT 24
Peak memory 226392 kb
Host smart-8f6ddc0f-f553-4c61-b024-13bc09c753fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599754124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.599754124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.1891289099
Short name T929
Test name
Test status
Simulation time 166511320 ps
CPU time 9.26 seconds
Started Mar 28 01:51:54 PM PDT 24
Finished Mar 28 01:52:03 PM PDT 24
Peak memory 218288 kb
Host smart-9a41f0d6-5c54-4306-ae62-7fa0015fc398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891289099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1891289099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.2516986805
Short name T422
Test name
Test status
Simulation time 65582137888 ps
CPU time 245 seconds
Started Mar 28 01:52:00 PM PDT 24
Finished Mar 28 01:56:05 PM PDT 24
Peak memory 268440 kb
Host smart-052c32ac-1e38-43e1-99c8-ee7d535275a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2516986805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2516986805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.3442367733
Short name T199
Test name
Test status
Simulation time 76867120 ps
CPU time 4.01 seconds
Started Mar 28 01:51:54 PM PDT 24
Finished Mar 28 01:51:58 PM PDT 24
Peak memory 216100 kb
Host smart-45b8135d-669e-45cb-bec3-688a3ab48ead
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442367733 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.3442367733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.1342435268
Short name T636
Test name
Test status
Simulation time 131928225 ps
CPU time 3.89 seconds
Started Mar 28 01:51:55 PM PDT 24
Finished Mar 28 01:51:59 PM PDT 24
Peak memory 216184 kb
Host smart-c5436459-b3c9-4b29-bef2-73cbaece49e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342435268 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.1342435268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.4007464043
Short name T16
Test name
Test status
Simulation time 195200936579 ps
CPU time 1995.07 seconds
Started Mar 28 01:51:56 PM PDT 24
Finished Mar 28 02:25:11 PM PDT 24
Peak memory 379468 kb
Host smart-974044b5-f484-414d-8540-2c36932914e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4007464043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.4007464043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.4161477121
Short name T967
Test name
Test status
Simulation time 92754474482 ps
CPU time 1720.41 seconds
Started Mar 28 01:51:53 PM PDT 24
Finished Mar 28 02:20:34 PM PDT 24
Peak memory 375064 kb
Host smart-ade3160c-c7fe-4ba4-869c-8cf8a246a0e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4161477121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.4161477121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.1719760804
Short name T565
Test name
Test status
Simulation time 14296264660 ps
CPU time 1183.41 seconds
Started Mar 28 01:51:55 PM PDT 24
Finished Mar 28 02:11:39 PM PDT 24
Peak memory 334156 kb
Host smart-bd162967-6a23-4027-93c9-73c9de6f7cf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1719760804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.1719760804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.2047259477
Short name T795
Test name
Test status
Simulation time 531818771040 ps
CPU time 1008.24 seconds
Started Mar 28 01:51:55 PM PDT 24
Finished Mar 28 02:08:44 PM PDT 24
Peak memory 296396 kb
Host smart-194a39b8-149f-4720-a247-ec8a538e9153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2047259477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.2047259477 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.2151157700
Short name T206
Test name
Test status
Simulation time 175036541625 ps
CPU time 4884.99 seconds
Started Mar 28 01:51:55 PM PDT 24
Finished Mar 28 03:13:20 PM PDT 24
Peak memory 657988 kb
Host smart-89da839d-6653-48e0-8147-36f91b71671e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2151157700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.2151157700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.2404912311
Short name T968
Test name
Test status
Simulation time 306259052310 ps
CPU time 4100.29 seconds
Started Mar 28 01:51:56 PM PDT 24
Finished Mar 28 03:00:17 PM PDT 24
Peak memory 571728 kb
Host smart-e81a85c5-872f-4922-a8e4-3d52fcf6227f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2404912311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.2404912311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.1842142118
Short name T40
Test name
Test status
Simulation time 16498784 ps
CPU time 0.77 seconds
Started Mar 28 01:52:26 PM PDT 24
Finished Mar 28 01:52:28 PM PDT 24
Peak memory 205548 kb
Host smart-0996899a-73d6-4e69-a2ac-b88405ff1904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842142118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1842142118 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.2126572414
Short name T492
Test name
Test status
Simulation time 23747323336 ps
CPU time 181.2 seconds
Started Mar 28 01:51:56 PM PDT 24
Finished Mar 28 01:54:57 PM PDT 24
Peak memory 239640 kb
Host smart-2ad27922-baeb-4e33-b23d-afbb6da3ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126572414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2126572414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.3702530327
Short name T748
Test name
Test status
Simulation time 1904774358 ps
CPU time 37.86 seconds
Started Mar 28 01:52:13 PM PDT 24
Finished Mar 28 01:52:51 PM PDT 24
Peak memory 224140 kb
Host smart-2dd5af9f-83b3-4029-9f76-49e160d492b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3702530327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3702530327 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.430473119
Short name T568
Test name
Test status
Simulation time 2066910216 ps
CPU time 23.38 seconds
Started Mar 28 01:52:13 PM PDT 24
Finished Mar 28 01:52:37 PM PDT 24
Peak memory 224144 kb
Host smart-f72aff86-fdc0-446c-aa2c-300854a8f3ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=430473119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.430473119 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_error.40326881
Short name T554
Test name
Test status
Simulation time 4205820918 ps
CPU time 324.77 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 01:57:22 PM PDT 24
Peak memory 265320 kb
Host smart-eaddb7a8-9db2-40ba-9021-5ee5fe822d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40326881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.40326881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.601935276
Short name T744
Test name
Test status
Simulation time 1125736044 ps
CPU time 2.16 seconds
Started Mar 28 01:52:10 PM PDT 24
Finished Mar 28 01:52:12 PM PDT 24
Peak memory 207364 kb
Host smart-745449b3-9812-45bf-aff7-be1c964f746e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601935276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.601935276 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.3349837038
Short name T35
Test name
Test status
Simulation time 259578407 ps
CPU time 1.29 seconds
Started Mar 28 01:52:15 PM PDT 24
Finished Mar 28 01:52:17 PM PDT 24
Peak memory 217328 kb
Host smart-8cfd761f-99bc-49ca-b2b4-d96bea196100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349837038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3349837038 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.1487229342
Short name T1067
Test name
Test status
Simulation time 37067617157 ps
CPU time 487.38 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 02:00:05 PM PDT 24
Peak memory 269920 kb
Host smart-9a67801e-5daa-496a-92a9-aa706de90ade
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487229342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.1487229342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.3424210225
Short name T1079
Test name
Test status
Simulation time 4686308815 ps
CPU time 339.54 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 01:57:37 PM PDT 24
Peak memory 252028 kb
Host smart-091416fb-662e-40f0-94a1-c22ac8561731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424210225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3424210225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.1217804214
Short name T883
Test name
Test status
Simulation time 1155920420 ps
CPU time 25.59 seconds
Started Mar 28 01:51:49 PM PDT 24
Finished Mar 28 01:52:15 PM PDT 24
Peak memory 222132 kb
Host smart-ba1b9cb8-688d-44f8-8121-76c0e5bbc0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217804214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1217804214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.3258379927
Short name T287
Test name
Test status
Simulation time 56860937148 ps
CPU time 362.52 seconds
Started Mar 28 01:52:15 PM PDT 24
Finished Mar 28 01:58:18 PM PDT 24
Peak memory 248320 kb
Host smart-7de7beba-59b6-4224-bbdb-2c17425e1899
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3258379927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3258379927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1771385608
Short name T671
Test name
Test status
Simulation time 1035957427 ps
CPU time 5.55 seconds
Started Mar 28 01:51:58 PM PDT 24
Finished Mar 28 01:52:03 PM PDT 24
Peak memory 215968 kb
Host smart-b91f5743-5c51-409f-b347-1c41678fc455
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771385608 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1771385608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.522254894
Short name T858
Test name
Test status
Simulation time 689918988 ps
CPU time 4.71 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 01:52:02 PM PDT 24
Peak memory 215996 kb
Host smart-d51b5d45-52ca-44ef-97a8-3f2d48ad9e3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522254894 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.kmac_test_vectors_kmac_xof.522254894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.352431497
Short name T397
Test name
Test status
Simulation time 110632517219 ps
CPU time 1673.12 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 02:19:51 PM PDT 24
Peak memory 391952 kb
Host smart-b91ff47d-50b5-4e81-9fb0-212f3b65d9de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=352431497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.352431497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.1541449545
Short name T983
Test name
Test status
Simulation time 184873436667 ps
CPU time 1830.86 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 02:22:28 PM PDT 24
Peak memory 378444 kb
Host smart-e7db6030-d227-402e-b192-a8441e6d7d81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1541449545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.1541449545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.1135993297
Short name T434
Test name
Test status
Simulation time 99574702168 ps
CPU time 1413.4 seconds
Started Mar 28 01:51:57 PM PDT 24
Finished Mar 28 02:15:31 PM PDT 24
Peak memory 333448 kb
Host smart-314fefd7-9657-4d9e-8488-743c282b91d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1135993297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.1135993297 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2960648026
Short name T981
Test name
Test status
Simulation time 32834487645 ps
CPU time 858.04 seconds
Started Mar 28 01:51:58 PM PDT 24
Finished Mar 28 02:06:17 PM PDT 24
Peak memory 292768 kb
Host smart-b6eeb028-e9f8-44b2-ae17-26547fffd90f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2960648026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2960648026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.1975200255
Short name T1061
Test name
Test status
Simulation time 245509094401 ps
CPU time 5040.63 seconds
Started Mar 28 01:51:59 PM PDT 24
Finished Mar 28 03:16:01 PM PDT 24
Peak memory 653816 kb
Host smart-79b52644-f5d0-4a4b-a1ef-37c65db4d46e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1975200255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1975200255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.3900809485
Short name T372
Test name
Test status
Simulation time 606436440977 ps
CPU time 4475.62 seconds
Started Mar 28 01:52:01 PM PDT 24
Finished Mar 28 03:06:37 PM PDT 24
Peak memory 563540 kb
Host smart-075f7811-09b3-4797-9997-7011ed5aba34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3900809485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.3900809485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.3204892131
Short name T471
Test name
Test status
Simulation time 27029443 ps
CPU time 0.77 seconds
Started Mar 28 01:52:30 PM PDT 24
Finished Mar 28 01:52:31 PM PDT 24
Peak memory 205580 kb
Host smart-de2dc52e-3566-40b6-a52e-fcb0448f1843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204892131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3204892131 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_burst_write.3153950034
Short name T635
Test name
Test status
Simulation time 3545232050 ps
CPU time 92.16 seconds
Started Mar 28 01:52:17 PM PDT 24
Finished Mar 28 01:53:49 PM PDT 24
Peak memory 223984 kb
Host smart-848cbefe-4029-46d0-bdf7-cacab000f014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153950034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3153950034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.1844307096
Short name T711
Test name
Test status
Simulation time 1385055632 ps
CPU time 35.07 seconds
Started Mar 28 01:52:15 PM PDT 24
Finished Mar 28 01:52:50 PM PDT 24
Peak memory 224188 kb
Host smart-69bea1ca-c5eb-4a88-b277-8111cc940337
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1844307096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1844307096 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.2020083692
Short name T418
Test name
Test status
Simulation time 1549105720 ps
CPU time 22.84 seconds
Started Mar 28 01:52:11 PM PDT 24
Finished Mar 28 01:52:34 PM PDT 24
Peak memory 217312 kb
Host smart-a0620cf7-7daa-44f7-96f8-8adedd11f4e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2020083692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2020083692 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.1279135752
Short name T941
Test name
Test status
Simulation time 2654843761 ps
CPU time 154.26 seconds
Started Mar 28 01:52:14 PM PDT 24
Finished Mar 28 01:54:49 PM PDT 24
Peak memory 235924 kb
Host smart-9dda94fc-a4fd-46dd-8e9e-a369f2d78673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279135752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1279135752 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.809298132
Short name T931
Test name
Test status
Simulation time 65484080845 ps
CPU time 303.73 seconds
Started Mar 28 01:52:10 PM PDT 24
Finished Mar 28 01:57:14 PM PDT 24
Peak memory 257052 kb
Host smart-ac364246-1871-4a1d-b6af-0e6b8b786cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809298132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.809298132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.4103999034
Short name T361
Test name
Test status
Simulation time 497821685 ps
CPU time 2.99 seconds
Started Mar 28 01:52:26 PM PDT 24
Finished Mar 28 01:52:29 PM PDT 24
Peak memory 207616 kb
Host smart-ed2cb703-78ac-4911-b25e-d48b205d5cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103999034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.4103999034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.3656605335
Short name T998
Test name
Test status
Simulation time 480967944 ps
CPU time 1.46 seconds
Started Mar 28 01:52:17 PM PDT 24
Finished Mar 28 01:52:18 PM PDT 24
Peak memory 216040 kb
Host smart-11f17cbc-e5ba-4595-9cee-a2011eb57388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656605335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3656605335 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1604751051
Short name T260
Test name
Test status
Simulation time 266526138476 ps
CPU time 1026.54 seconds
Started Mar 28 01:52:09 PM PDT 24
Finished Mar 28 02:09:16 PM PDT 24
Peak memory 314992 kb
Host smart-eb9ed7df-4610-40a2-86a3-4a376fdc244b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604751051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1604751051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.2337320015
Short name T907
Test name
Test status
Simulation time 29279432695 ps
CPU time 108.95 seconds
Started Mar 28 01:52:11 PM PDT 24
Finished Mar 28 01:54:00 PM PDT 24
Peak memory 229464 kb
Host smart-acd85043-068d-4366-90e5-2837957314f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337320015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2337320015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.1360703568
Short name T224
Test name
Test status
Simulation time 502232307 ps
CPU time 8.93 seconds
Started Mar 28 01:52:14 PM PDT 24
Finished Mar 28 01:52:23 PM PDT 24
Peak memory 224276 kb
Host smart-fdc8c7b6-d4d9-4ae3-8f8e-dc7c54ba8062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360703568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1360703568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.1691974918
Short name T876
Test name
Test status
Simulation time 1326356963 ps
CPU time 4.75 seconds
Started Mar 28 01:52:14 PM PDT 24
Finished Mar 28 01:52:19 PM PDT 24
Peak memory 216024 kb
Host smart-2cbfb2c1-0bce-48da-87f1-2854222a1833
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691974918 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.1691974918 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.2630475312
Short name T991
Test name
Test status
Simulation time 68646460 ps
CPU time 3.93 seconds
Started Mar 28 01:52:10 PM PDT 24
Finished Mar 28 01:52:14 PM PDT 24
Peak memory 209204 kb
Host smart-3a51f605-cb4f-453b-a081-02d161a50532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630475312 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.2630475312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.1708520961
Short name T304
Test name
Test status
Simulation time 75354190664 ps
CPU time 1585.42 seconds
Started Mar 28 01:52:10 PM PDT 24
Finished Mar 28 02:18:36 PM PDT 24
Peak memory 393268 kb
Host smart-1df617df-cb58-4f4c-9002-4acc816ce246
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1708520961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.1708520961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.557459194
Short name T955
Test name
Test status
Simulation time 21645100388 ps
CPU time 1591.01 seconds
Started Mar 28 01:52:09 PM PDT 24
Finished Mar 28 02:18:40 PM PDT 24
Peak memory 379308 kb
Host smart-7334774b-0f1f-4ac5-b34d-091ec3802a23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=557459194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.557459194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.2512416857
Short name T626
Test name
Test status
Simulation time 80163034341 ps
CPU time 1161.51 seconds
Started Mar 28 01:52:13 PM PDT 24
Finished Mar 28 02:11:35 PM PDT 24
Peak memory 335184 kb
Host smart-5e4f5827-7ce6-4429-a6ee-559963973d1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2512416857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.2512416857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.208511748
Short name T984
Test name
Test status
Simulation time 9819901123 ps
CPU time 840.69 seconds
Started Mar 28 01:52:15 PM PDT 24
Finished Mar 28 02:06:16 PM PDT 24
Peak memory 295828 kb
Host smart-0113b77d-0fc6-4604-b012-eb5307b017dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=208511748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.208511748 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.458341927
Short name T480
Test name
Test status
Simulation time 93917616571 ps
CPU time 4034.62 seconds
Started Mar 28 01:52:27 PM PDT 24
Finished Mar 28 02:59:42 PM PDT 24
Peak memory 648776 kb
Host smart-c8633e5a-eb5a-45c0-bcf4-6702048c5f49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=458341927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.458341927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.987979956
Short name T531
Test name
Test status
Simulation time 252288027491 ps
CPU time 3621.7 seconds
Started Mar 28 01:52:13 PM PDT 24
Finished Mar 28 02:52:35 PM PDT 24
Peak memory 553356 kb
Host smart-9ab5534c-eec1-4adc-99a1-84e33e03f482
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=987979956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.987979956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.4094932648
Short name T410
Test name
Test status
Simulation time 49970193 ps
CPU time 0.81 seconds
Started Mar 28 01:52:53 PM PDT 24
Finished Mar 28 01:52:54 PM PDT 24
Peak memory 205576 kb
Host smart-9daab9e9-1913-46ff-ace2-d44db2a1af5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094932648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.4094932648 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.2643856064
Short name T859
Test name
Test status
Simulation time 24776294164 ps
CPU time 236.86 seconds
Started Mar 28 01:52:58 PM PDT 24
Finished Mar 28 01:56:54 PM PDT 24
Peak memory 242680 kb
Host smart-996a97cc-a03b-4b2c-9f83-48b5d35508a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643856064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2643856064 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.1285690242
Short name T560
Test name
Test status
Simulation time 35699445972 ps
CPU time 887.18 seconds
Started Mar 28 01:52:27 PM PDT 24
Finished Mar 28 02:07:14 PM PDT 24
Peak memory 232244 kb
Host smart-cd52f2c8-f6d2-479b-be76-c40c85458b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285690242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1285690242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.860018483
Short name T563
Test name
Test status
Simulation time 5464302306 ps
CPU time 33.1 seconds
Started Mar 28 01:52:54 PM PDT 24
Finished Mar 28 01:53:27 PM PDT 24
Peak memory 224032 kb
Host smart-ff44ee37-255e-4a07-aa0a-bf9cdb5c6511
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=860018483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.860018483 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.3587690362
Short name T259
Test name
Test status
Simulation time 169021706 ps
CPU time 11.91 seconds
Started Mar 28 01:52:54 PM PDT 24
Finished Mar 28 01:53:06 PM PDT 24
Peak memory 217556 kb
Host smart-d9303f66-0eb1-485d-8aa3-08c31eb4c793
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3587690362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3587690362 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.2699622952
Short name T764
Test name
Test status
Simulation time 22757064158 ps
CPU time 291.96 seconds
Started Mar 28 01:52:58 PM PDT 24
Finished Mar 28 01:57:50 PM PDT 24
Peak memory 249472 kb
Host smart-08e5511c-a17c-4970-a9ae-3e6e9bbeb564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699622952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2699622952 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.3637448828
Short name T1015
Test name
Test status
Simulation time 15271537275 ps
CPU time 300.92 seconds
Started Mar 28 01:52:54 PM PDT 24
Finished Mar 28 01:57:56 PM PDT 24
Peak memory 257096 kb
Host smart-d654ce52-254c-4a16-91b7-2a4940c567e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637448828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3637448828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.3377541096
Short name T615
Test name
Test status
Simulation time 1187849291 ps
CPU time 4.49 seconds
Started Mar 28 01:53:00 PM PDT 24
Finished Mar 28 01:53:04 PM PDT 24
Peak memory 207560 kb
Host smart-099b7617-a488-44f7-a1c8-aeefdd171465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377541096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3377541096 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.1639222784
Short name T685
Test name
Test status
Simulation time 28604145 ps
CPU time 1.17 seconds
Started Mar 28 01:52:55 PM PDT 24
Finished Mar 28 01:52:56 PM PDT 24
Peak memory 216008 kb
Host smart-5a26ee00-e78f-4cf3-9d6f-58777f7538b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639222784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1639222784 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.151348766
Short name T864
Test name
Test status
Simulation time 47440392662 ps
CPU time 2204.45 seconds
Started Mar 28 01:52:27 PM PDT 24
Finished Mar 28 02:29:12 PM PDT 24
Peak memory 442284 kb
Host smart-d4f62eec-6d66-4ddd-91c3-238716369315
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151348766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_an
d_output.151348766 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.1507436727
Short name T945
Test name
Test status
Simulation time 44438887656 ps
CPU time 239.97 seconds
Started Mar 28 01:52:29 PM PDT 24
Finished Mar 28 01:56:29 PM PDT 24
Peak memory 237744 kb
Host smart-0d61fdef-3acd-4532-abca-e33c674d7614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507436727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1507436727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.2470262250
Short name T845
Test name
Test status
Simulation time 1212565970 ps
CPU time 28.35 seconds
Started Mar 28 01:52:28 PM PDT 24
Finished Mar 28 01:52:56 PM PDT 24
Peak memory 217408 kb
Host smart-fe8cb87c-d1f2-4e8e-be0b-cba05006820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470262250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2470262250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.605102978
Short name T38
Test name
Test status
Simulation time 25933864867 ps
CPU time 252.55 seconds
Started Mar 28 01:52:55 PM PDT 24
Finished Mar 28 01:57:07 PM PDT 24
Peak memory 241636 kb
Host smart-d5f3c8df-6e6e-4d86-9cba-8dcd35381fbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=605102978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.605102978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.838228325
Short name T370
Test name
Test status
Simulation time 205746547 ps
CPU time 4.37 seconds
Started Mar 28 01:52:31 PM PDT 24
Finished Mar 28 01:52:36 PM PDT 24
Peak memory 215980 kb
Host smart-682c6f6f-1a90-428c-978e-d6469a17f211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838228325 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.kmac_test_vectors_kmac.838228325 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.914029180
Short name T994
Test name
Test status
Simulation time 267350685 ps
CPU time 4.16 seconds
Started Mar 28 01:52:27 PM PDT 24
Finished Mar 28 01:52:32 PM PDT 24
Peak memory 216112 kb
Host smart-b312ecd2-826e-4a01-84f0-c5bfc08ddeda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914029180 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.kmac_test_vectors_kmac_xof.914029180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.56269849
Short name T703
Test name
Test status
Simulation time 270970587637 ps
CPU time 1818.05 seconds
Started Mar 28 01:52:29 PM PDT 24
Finished Mar 28 02:22:47 PM PDT 24
Peak memory 393404 kb
Host smart-6935a557-86a4-4fbf-9afd-a158187a94d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=56269849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.56269849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3753755649
Short name T1043
Test name
Test status
Simulation time 512090557096 ps
CPU time 1951.67 seconds
Started Mar 28 01:52:31 PM PDT 24
Finished Mar 28 02:25:03 PM PDT 24
Peak memory 377736 kb
Host smart-4901bbba-fa32-47d3-a456-a6bbe60421ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3753755649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3753755649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.1471449058
Short name T712
Test name
Test status
Simulation time 14134615580 ps
CPU time 1062.77 seconds
Started Mar 28 01:52:30 PM PDT 24
Finished Mar 28 02:10:13 PM PDT 24
Peak memory 331252 kb
Host smart-f22fba81-96b7-4133-b385-575f04c5571a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1471449058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1471449058 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.1814534245
Short name T836
Test name
Test status
Simulation time 32751059284 ps
CPU time 881.51 seconds
Started Mar 28 01:52:27 PM PDT 24
Finished Mar 28 02:07:10 PM PDT 24
Peak memory 294220 kb
Host smart-40746eb5-3897-4c55-9fa7-4eca78f68e4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1814534245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.1814534245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.74109121
Short name T228
Test name
Test status
Simulation time 71239396110 ps
CPU time 3801.12 seconds
Started Mar 28 01:52:30 PM PDT 24
Finished Mar 28 02:55:51 PM PDT 24
Peak memory 645072 kb
Host smart-09fe7d10-8f7e-40eb-858c-d3a6ad925ece
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=74109121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.74109121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.2247010140
Short name T474
Test name
Test status
Simulation time 89995381842 ps
CPU time 3519.73 seconds
Started Mar 28 01:52:27 PM PDT 24
Finished Mar 28 02:51:08 PM PDT 24
Peak memory 559744 kb
Host smart-bd5f57f3-45fe-4bca-aef0-d7551d824fba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2247010140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.2247010140 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.1940874583
Short name T429
Test name
Test status
Simulation time 15185182 ps
CPU time 0.79 seconds
Started Mar 28 01:53:20 PM PDT 24
Finished Mar 28 01:53:21 PM PDT 24
Peak memory 205552 kb
Host smart-6e866a32-630a-458b-857e-bbe8462b5475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940874583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1940874583 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.3245866657
Short name T311
Test name
Test status
Simulation time 27725137338 ps
CPU time 257.96 seconds
Started Mar 28 01:53:17 PM PDT 24
Finished Mar 28 01:57:36 PM PDT 24
Peak memory 241856 kb
Host smart-97ce5a2b-45d2-400a-acf9-2015311689d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245866657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.3245866657 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.4077046499
Short name T37
Test name
Test status
Simulation time 1079942023 ps
CPU time 90.6 seconds
Started Mar 28 01:52:54 PM PDT 24
Finished Mar 28 01:54:25 PM PDT 24
Peak memory 224256 kb
Host smart-d166292d-0b75-4f43-a265-94e6089f2c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077046499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.4077046499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.3394933656
Short name T1007
Test name
Test status
Simulation time 2881263389 ps
CPU time 11.66 seconds
Started Mar 28 01:53:19 PM PDT 24
Finished Mar 28 01:53:31 PM PDT 24
Peak memory 216008 kb
Host smart-dc42036b-0114-422a-91a4-dabca534da2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394933656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3394933656 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2585697325
Short name T604
Test name
Test status
Simulation time 2808570297 ps
CPU time 18.59 seconds
Started Mar 28 01:53:18 PM PDT 24
Finished Mar 28 01:53:37 PM PDT 24
Peak memory 222984 kb
Host smart-3c43660c-5b53-4e9b-874b-0ef971e2c9a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2585697325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2585697325 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.4287485157
Short name T1072
Test name
Test status
Simulation time 5721890717 ps
CPU time 293.5 seconds
Started Mar 28 01:53:15 PM PDT 24
Finished Mar 28 01:58:09 PM PDT 24
Peak memory 247388 kb
Host smart-be04c099-81b4-4dbf-bb35-e2f603099abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287485157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.4287485157 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_key_error.3137849024
Short name T433
Test name
Test status
Simulation time 580685068 ps
CPU time 2.59 seconds
Started Mar 28 01:53:17 PM PDT 24
Finished Mar 28 01:53:20 PM PDT 24
Peak memory 207516 kb
Host smart-7e8c8eb4-c0c4-46ed-b091-6394008419c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137849024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3137849024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.168873476
Short name T423
Test name
Test status
Simulation time 83961885506 ps
CPU time 2105.22 seconds
Started Mar 28 01:52:58 PM PDT 24
Finished Mar 28 02:28:03 PM PDT 24
Peak memory 435744 kb
Host smart-a388a727-d41a-4138-b8eb-9768ee8b88bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168873476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_an
d_output.168873476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.2874529663
Short name T66
Test name
Test status
Simulation time 26093224990 ps
CPU time 374.23 seconds
Started Mar 28 01:52:57 PM PDT 24
Finished Mar 28 01:59:12 PM PDT 24
Peak memory 249560 kb
Host smart-41e5ba8a-d1dd-450c-b8a7-5cfabba80762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874529663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2874529663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.4022553787
Short name T181
Test name
Test status
Simulation time 13987146223 ps
CPU time 57.27 seconds
Started Mar 28 01:52:57 PM PDT 24
Finished Mar 28 01:53:55 PM PDT 24
Peak memory 222328 kb
Host smart-83884f88-5a0c-4034-bd1d-fa21fddcbbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022553787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.4022553787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.1206354346
Short name T670
Test name
Test status
Simulation time 15734145378 ps
CPU time 316.41 seconds
Started Mar 28 01:53:17 PM PDT 24
Finished Mar 28 01:58:33 PM PDT 24
Peak memory 265440 kb
Host smart-d3b0e06f-f292-45a7-bccd-a058cb56ab11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1206354346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1206354346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.2750413480
Short name T269
Test name
Test status
Simulation time 264452433 ps
CPU time 4.16 seconds
Started Mar 28 01:53:16 PM PDT 24
Finished Mar 28 01:53:20 PM PDT 24
Peak memory 216136 kb
Host smart-c6c6e7fa-2037-470e-9a65-9cd43defe88d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750413480 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.2750413480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.972196083
Short name T581
Test name
Test status
Simulation time 1686959303 ps
CPU time 4.39 seconds
Started Mar 28 01:53:15 PM PDT 24
Finished Mar 28 01:53:20 PM PDT 24
Peak memory 216120 kb
Host smart-35726ccd-c981-43ee-b8e1-862998ee8c26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972196083 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.kmac_test_vectors_kmac_xof.972196083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.2100947342
Short name T274
Test name
Test status
Simulation time 18518905607 ps
CPU time 1574.26 seconds
Started Mar 28 01:52:56 PM PDT 24
Finished Mar 28 02:19:11 PM PDT 24
Peak memory 379352 kb
Host smart-3c451c97-d098-4431-ad6f-23721b4ce45b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2100947342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.2100947342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.2539733158
Short name T850
Test name
Test status
Simulation time 250961061332 ps
CPU time 1649.09 seconds
Started Mar 28 01:52:54 PM PDT 24
Finished Mar 28 02:20:23 PM PDT 24
Peak memory 369168 kb
Host smart-7657453d-fa3a-41d3-97d6-26ef48367da4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2539733158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.2539733158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3330831313
Short name T866
Test name
Test status
Simulation time 256313383779 ps
CPU time 1425.63 seconds
Started Mar 28 01:53:00 PM PDT 24
Finished Mar 28 02:16:46 PM PDT 24
Peak memory 337848 kb
Host smart-cd9c8026-28ae-476e-8af8-5ee34cbeebf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3330831313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3330831313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.2195324526
Short name T725
Test name
Test status
Simulation time 52972471809 ps
CPU time 753.79 seconds
Started Mar 28 01:53:16 PM PDT 24
Finished Mar 28 02:05:50 PM PDT 24
Peak memory 296056 kb
Host smart-2b024e31-e146-4ed5-bd03-94f7e95aa45a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2195324526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.2195324526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.230654293
Short name T188
Test name
Test status
Simulation time 175243843668 ps
CPU time 4667.39 seconds
Started Mar 28 01:53:16 PM PDT 24
Finished Mar 28 03:11:04 PM PDT 24
Peak memory 649692 kb
Host smart-6ab6938d-ed98-4021-b428-e5cf2b8cf17b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=230654293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.230654293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.2430414439
Short name T503
Test name
Test status
Simulation time 96984801052 ps
CPU time 3455.36 seconds
Started Mar 28 01:53:15 PM PDT 24
Finished Mar 28 02:50:51 PM PDT 24
Peak memory 548252 kb
Host smart-56b88ba7-2eb7-48a0-899e-80fd338aad99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2430414439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.2430414439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.2861143268
Short name T322
Test name
Test status
Simulation time 42975822 ps
CPU time 0.79 seconds
Started Mar 28 01:53:37 PM PDT 24
Finished Mar 28 01:53:38 PM PDT 24
Peak memory 205572 kb
Host smart-3f997d10-ee52-4e78-9209-dcd3abaa4b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861143268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2861143268 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.1344315566
Short name T843
Test name
Test status
Simulation time 1571507780 ps
CPU time 19.85 seconds
Started Mar 28 01:53:19 PM PDT 24
Finished Mar 28 01:53:39 PM PDT 24
Peak memory 219352 kb
Host smart-8e71605d-9226-4df9-96d0-afdc01e7b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344315566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1344315566 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.3774211635
Short name T235
Test name
Test status
Simulation time 5885104912 ps
CPU time 470.71 seconds
Started Mar 28 01:53:16 PM PDT 24
Finished Mar 28 02:01:07 PM PDT 24
Peak memory 231652 kb
Host smart-62d1bbf2-5a9d-4ec3-80e1-0cd05b6698d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774211635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3774211635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.423930440
Short name T493
Test name
Test status
Simulation time 3397031876 ps
CPU time 36.48 seconds
Started Mar 28 01:53:35 PM PDT 24
Finished Mar 28 01:54:12 PM PDT 24
Peak memory 224164 kb
Host smart-0278bb3d-8b6c-403a-86b7-ddfa047a7a79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=423930440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.423930440 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.3117833987
Short name T953
Test name
Test status
Simulation time 4084134303 ps
CPU time 29.46 seconds
Started Mar 28 01:53:35 PM PDT 24
Finished Mar 28 01:54:05 PM PDT 24
Peak memory 220332 kb
Host smart-b7716938-318d-4d73-bca7-b880d742f39e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3117833987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3117833987 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.2368202941
Short name T797
Test name
Test status
Simulation time 80899829933 ps
CPU time 302.04 seconds
Started Mar 28 01:53:19 PM PDT 24
Finished Mar 28 01:58:22 PM PDT 24
Peak memory 246436 kb
Host smart-c341174c-121a-4a1d-b5c9-7b46feabb7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368202941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2368202941 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.583336128
Short name T742
Test name
Test status
Simulation time 4594322569 ps
CPU time 323.1 seconds
Started Mar 28 01:53:20 PM PDT 24
Finished Mar 28 01:58:43 PM PDT 24
Peak memory 257020 kb
Host smart-8b72691f-7ffe-4855-9ab9-f7ca4b4b39fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583336128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.583336128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.1983704303
Short name T700
Test name
Test status
Simulation time 5032933242 ps
CPU time 6.84 seconds
Started Mar 28 01:53:39 PM PDT 24
Finished Mar 28 01:53:46 PM PDT 24
Peak memory 207740 kb
Host smart-3f174944-385b-4734-a56c-3e1358581e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983704303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1983704303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.2887017562
Short name T34
Test name
Test status
Simulation time 41792477 ps
CPU time 1.26 seconds
Started Mar 28 01:53:41 PM PDT 24
Finished Mar 28 01:53:42 PM PDT 24
Peak memory 216108 kb
Host smart-fceec45f-2d2a-47d6-8a3b-485a4cdf528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887017562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2887017562 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.3992717167
Short name T325
Test name
Test status
Simulation time 337224139007 ps
CPU time 1412.79 seconds
Started Mar 28 01:53:20 PM PDT 24
Finished Mar 28 02:16:53 PM PDT 24
Peak memory 373912 kb
Host smart-43f884b0-18f6-4e29-9dfc-6bf84e70c57e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992717167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.3992717167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.978684085
Short name T693
Test name
Test status
Simulation time 15859666495 ps
CPU time 373.62 seconds
Started Mar 28 01:53:17 PM PDT 24
Finished Mar 28 01:59:31 PM PDT 24
Peak memory 251044 kb
Host smart-2198c956-1f4f-4fa0-a166-0b87958e2068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978684085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.978684085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.872316878
Short name T784
Test name
Test status
Simulation time 6199490877 ps
CPU time 53.11 seconds
Started Mar 28 01:53:18 PM PDT 24
Finished Mar 28 01:54:12 PM PDT 24
Peak memory 217416 kb
Host smart-0950038b-6f2d-4f33-88ae-9a6edd72ddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872316878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.872316878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all_with_rand_reset.4172286618
Short name T113
Test name
Test status
Simulation time 134059560309 ps
CPU time 1667.94 seconds
Started Mar 28 01:53:42 PM PDT 24
Finished Mar 28 02:21:30 PM PDT 24
Peak memory 317752 kb
Host smart-fcce5454-ebfc-495b-b280-f3554e3fff6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172286618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.4172286618 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.688848453
Short name T329
Test name
Test status
Simulation time 251471459 ps
CPU time 5.31 seconds
Started Mar 28 01:53:19 PM PDT 24
Finished Mar 28 01:53:24 PM PDT 24
Peak memory 216128 kb
Host smart-a76c594d-e482-440f-9494-07ec3fb14e75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688848453 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.kmac_test_vectors_kmac.688848453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.2559376417
Short name T630
Test name
Test status
Simulation time 1112378204 ps
CPU time 5.06 seconds
Started Mar 28 01:53:21 PM PDT 24
Finished Mar 28 01:53:26 PM PDT 24
Peak memory 216052 kb
Host smart-1f9e8bcd-baeb-49ff-bc9a-78a70a2ae65e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559376417 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.2559376417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.50899627
Short name T500
Test name
Test status
Simulation time 83111627123 ps
CPU time 1626.48 seconds
Started Mar 28 01:53:17 PM PDT 24
Finished Mar 28 02:20:24 PM PDT 24
Peak memory 373448 kb
Host smart-ad776b2f-7ce6-4abb-a5ae-797c1274e324
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=50899627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.50899627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.3344384562
Short name T863
Test name
Test status
Simulation time 18286717428 ps
CPU time 1598.36 seconds
Started Mar 28 01:53:20 PM PDT 24
Finished Mar 28 02:19:58 PM PDT 24
Peak memory 392800 kb
Host smart-1fd69238-8cbb-4631-bb30-4d67419af71e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3344384562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.3344384562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.2248054350
Short name T183
Test name
Test status
Simulation time 125226222943 ps
CPU time 1343.3 seconds
Started Mar 28 01:53:16 PM PDT 24
Finished Mar 28 02:15:40 PM PDT 24
Peak memory 331876 kb
Host smart-949cc2ea-eaf2-4db5-b94d-687b057c7448
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2248054350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.2248054350 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.3712007494
Short name T610
Test name
Test status
Simulation time 43117306412 ps
CPU time 925.78 seconds
Started Mar 28 01:53:17 PM PDT 24
Finished Mar 28 02:08:43 PM PDT 24
Peak memory 293176 kb
Host smart-7fc1c5a4-e588-4204-a78d-5ba78137f9be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3712007494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.3712007494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.1784178684
Short name T456
Test name
Test status
Simulation time 179975996417 ps
CPU time 4733.52 seconds
Started Mar 28 01:53:18 PM PDT 24
Finished Mar 28 03:12:12 PM PDT 24
Peak memory 655164 kb
Host smart-2a489b4f-2652-49f7-868f-bd0f2a06d410
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1784178684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.1784178684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.3778706815
Short name T751
Test name
Test status
Simulation time 91063499327 ps
CPU time 3793.38 seconds
Started Mar 28 01:53:21 PM PDT 24
Finished Mar 28 02:56:35 PM PDT 24
Peak memory 570336 kb
Host smart-29e3978a-b6ca-43ce-9a80-a324d3b5c1a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3778706815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.3778706815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.449629459
Short name T620
Test name
Test status
Simulation time 61722196 ps
CPU time 0.83 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:50:26 PM PDT 24
Peak memory 205568 kb
Host smart-15bd692d-38bb-4f5b-acdb-ba5e97f5ecce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449629459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.449629459 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.1739259856
Short name T149
Test name
Test status
Simulation time 11490139563 ps
CPU time 253.21 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 01:54:37 PM PDT 24
Peak memory 242740 kb
Host smart-76f04d53-e1fc-4c08-8482-252454cf3688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739259856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1739259856 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.3082370573
Short name T532
Test name
Test status
Simulation time 49186169173 ps
CPU time 290.62 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 01:55:19 PM PDT 24
Peak memory 242576 kb
Host smart-945bd5e2-335c-4638-872b-8cc8e3de9aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082370573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3082370573 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.3695459824
Short name T1068
Test name
Test status
Simulation time 16510210737 ps
CPU time 499.25 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:58:45 PM PDT 24
Peak memory 231324 kb
Host smart-5329d85b-772b-42f6-8f1d-214858a56c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695459824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3695459824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.119733780
Short name T374
Test name
Test status
Simulation time 1559571080 ps
CPU time 41.87 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:51:07 PM PDT 24
Peak memory 224108 kb
Host smart-1e18c989-4d1b-4dc3-937a-384ff26a35a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=119733780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.119733780 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.1002084406
Short name T221
Test name
Test status
Simulation time 7523637929 ps
CPU time 21.88 seconds
Started Mar 28 01:50:28 PM PDT 24
Finished Mar 28 01:50:51 PM PDT 24
Peak memory 218732 kb
Host smart-fa2e37a9-e0eb-4b44-8eab-ac5efa143acf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1002084406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1002084406 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.3346248442
Short name T651
Test name
Test status
Simulation time 4652246648 ps
CPU time 38.23 seconds
Started Mar 28 01:50:23 PM PDT 24
Finished Mar 28 01:51:02 PM PDT 24
Peak memory 224312 kb
Host smart-5fb1cf63-1076-4a21-ba8b-455434980f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346248442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3346248442 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3250080516
Short name T611
Test name
Test status
Simulation time 39812785847 ps
CPU time 325.59 seconds
Started Mar 28 01:50:23 PM PDT 24
Finished Mar 28 01:55:49 PM PDT 24
Peak memory 244624 kb
Host smart-ae710348-cdb0-40c4-9e6e-eb7d04181b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250080516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3250080516 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.3526180729
Short name T727
Test name
Test status
Simulation time 7765240680 ps
CPU time 287.95 seconds
Started Mar 28 01:50:28 PM PDT 24
Finished Mar 28 01:55:17 PM PDT 24
Peak memory 265356 kb
Host smart-ac16e63c-b192-4ca8-a6ef-8544a44a2cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526180729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3526180729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.2922654542
Short name T1078
Test name
Test status
Simulation time 1033452183 ps
CPU time 5.76 seconds
Started Mar 28 01:50:26 PM PDT 24
Finished Mar 28 01:50:31 PM PDT 24
Peak memory 207616 kb
Host smart-2ff0e11a-e79b-40c2-b420-046702f7ec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922654542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2922654542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.2940317385
Short name T607
Test name
Test status
Simulation time 171455834 ps
CPU time 1.28 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:50:27 PM PDT 24
Peak memory 215984 kb
Host smart-e27e6f1b-5865-4342-87e1-8a61add69a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940317385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2940317385 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.3674861386
Short name T225
Test name
Test status
Simulation time 79144016738 ps
CPU time 1652.15 seconds
Started Mar 28 01:50:06 PM PDT 24
Finished Mar 28 02:17:39 PM PDT 24
Peak memory 411928 kb
Host smart-db0dac9b-4f5a-4a98-90bf-c6abab63e6dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674861386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.3674861386 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.3027606975
Short name T309
Test name
Test status
Simulation time 917248456 ps
CPU time 58.19 seconds
Started Mar 28 01:50:28 PM PDT 24
Finished Mar 28 01:51:27 PM PDT 24
Peak memory 225716 kb
Host smart-2b975d0b-57f8-4102-87ea-9cc187b2cc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027606975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3027606975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.2107144573
Short name T67
Test name
Test status
Simulation time 38918792156 ps
CPU time 49.72 seconds
Started Mar 28 01:50:23 PM PDT 24
Finished Mar 28 01:51:13 PM PDT 24
Peak memory 253956 kb
Host smart-12769ed6-e323-4654-a904-881c55f7c4fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107144573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2107144573 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.3716100475
Short name T594
Test name
Test status
Simulation time 7533567390 ps
CPU time 195.63 seconds
Started Mar 28 01:50:07 PM PDT 24
Finished Mar 28 01:53:23 PM PDT 24
Peak memory 236020 kb
Host smart-fff09177-0877-4b00-983b-87130942320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716100475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3716100475 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.69492536
Short name T179
Test name
Test status
Simulation time 3575763042 ps
CPU time 38.96 seconds
Started Mar 28 01:50:09 PM PDT 24
Finished Mar 28 01:50:48 PM PDT 24
Peak memory 221608 kb
Host smart-57da4356-6f3a-454a-9e51-da2de1ab71de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69492536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.69492536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2814227664
Short name T515
Test name
Test status
Simulation time 200930563 ps
CPU time 12.4 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:50:38 PM PDT 24
Peak memory 219516 kb
Host smart-c300b94c-0d4b-4e89-b641-68fe510bd1c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2814227664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2814227664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.4230727483
Short name T1021
Test name
Test status
Simulation time 499834984 ps
CPU time 4.67 seconds
Started Mar 28 01:50:23 PM PDT 24
Finished Mar 28 01:50:28 PM PDT 24
Peak memory 209240 kb
Host smart-2cd0c629-9dfc-40d9-bebd-ce7a41f6bb3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230727483 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.4230727483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.3278110818
Short name T824
Test name
Test status
Simulation time 296567736 ps
CPU time 3.65 seconds
Started Mar 28 01:50:29 PM PDT 24
Finished Mar 28 01:50:34 PM PDT 24
Peak memory 216172 kb
Host smart-466c9389-3edb-4903-ba87-3a0d2fe599e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278110818 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3278110818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.2528413955
Short name T321
Test name
Test status
Simulation time 205312674650 ps
CPU time 2149.42 seconds
Started Mar 28 01:50:23 PM PDT 24
Finished Mar 28 02:26:13 PM PDT 24
Peak memory 405952 kb
Host smart-f1e80928-ab10-444e-96eb-9d6b03f19d76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2528413955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2528413955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.2459383013
Short name T901
Test name
Test status
Simulation time 240138131124 ps
CPU time 2007.68 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 02:23:52 PM PDT 24
Peak memory 373680 kb
Host smart-52eec5d7-73b4-440b-9a8f-00934c7cdd3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2459383013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2459383013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.2743597516
Short name T405
Test name
Test status
Simulation time 185370650693 ps
CPU time 1508.52 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 02:15:33 PM PDT 24
Peak memory 332460 kb
Host smart-2fbf4053-b799-4de8-8d05-5b26fcd62139
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2743597516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2743597516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.2270142227
Short name T540
Test name
Test status
Simulation time 220914166335 ps
CPU time 976.59 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 02:06:41 PM PDT 24
Peak memory 294272 kb
Host smart-2cb35ccd-cd4b-4fdd-a4e4-2c2bc840103f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2270142227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2270142227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.3637300492
Short name T677
Test name
Test status
Simulation time 336774010653 ps
CPU time 5155.37 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 03:16:20 PM PDT 24
Peak memory 649124 kb
Host smart-f5d9ef94-d7de-4ae6-9046-a75f4b24f4f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3637300492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3637300492 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.3172904576
Short name T655
Test name
Test status
Simulation time 875847905088 ps
CPU time 4771.17 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 03:09:56 PM PDT 24
Peak memory 571072 kb
Host smart-fd9b6943-0d50-4a9f-a91c-eed584c97bcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3172904576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3172904576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.3529675930
Short name T738
Test name
Test status
Simulation time 70323957 ps
CPU time 0.75 seconds
Started Mar 28 01:53:55 PM PDT 24
Finished Mar 28 01:53:56 PM PDT 24
Peak memory 205544 kb
Host smart-d8bd405a-94e1-4ae4-8f27-2e463ff8e241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529675930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3529675930 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.2836328725
Short name T244
Test name
Test status
Simulation time 53061452917 ps
CPU time 351.68 seconds
Started Mar 28 01:53:38 PM PDT 24
Finished Mar 28 01:59:30 PM PDT 24
Peak memory 249440 kb
Host smart-e01cd050-c525-46a3-afac-0d9c06348dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836328725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2836328725 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.636680147
Short name T678
Test name
Test status
Simulation time 10850548530 ps
CPU time 84.26 seconds
Started Mar 28 01:53:42 PM PDT 24
Finished Mar 28 01:55:07 PM PDT 24
Peak memory 224248 kb
Host smart-0bae209e-0d2b-45ea-afe9-05e8e39554b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636680147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.636680147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.3215927601
Short name T375
Test name
Test status
Simulation time 21023668494 ps
CPU time 111.84 seconds
Started Mar 28 01:53:52 PM PDT 24
Finished Mar 28 01:55:44 PM PDT 24
Peak memory 230476 kb
Host smart-253fb9fb-893e-47b4-bf62-4aff0f067765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215927601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3215927601 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.1527437009
Short name T85
Test name
Test status
Simulation time 3372523234 ps
CPU time 119.97 seconds
Started Mar 28 01:53:53 PM PDT 24
Finished Mar 28 01:55:53 PM PDT 24
Peak memory 240748 kb
Host smart-a800d6b0-2ca3-48d5-b464-a5f1e2bfe974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527437009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1527437009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.2423055410
Short name T1070
Test name
Test status
Simulation time 181269514 ps
CPU time 1.28 seconds
Started Mar 28 01:53:52 PM PDT 24
Finished Mar 28 01:53:53 PM PDT 24
Peak memory 207656 kb
Host smart-f8b2f3dd-f7d3-4785-a64d-5ea514a2695c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423055410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2423055410 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.3102997508
Short name T579
Test name
Test status
Simulation time 26909027303 ps
CPU time 2399.42 seconds
Started Mar 28 01:53:37 PM PDT 24
Finished Mar 28 02:33:37 PM PDT 24
Peak memory 470184 kb
Host smart-6cbf0908-8da5-483b-b02a-5cb097363e60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102997508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.3102997508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.3855137396
Short name T956
Test name
Test status
Simulation time 12385842831 ps
CPU time 329.13 seconds
Started Mar 28 01:53:34 PM PDT 24
Finished Mar 28 01:59:04 PM PDT 24
Peak memory 246672 kb
Host smart-f8c332d3-5a64-4977-9557-31ab386d1605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855137396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3855137396 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.1368117193
Short name T542
Test name
Test status
Simulation time 2979794437 ps
CPU time 22.18 seconds
Started Mar 28 01:53:35 PM PDT 24
Finished Mar 28 01:53:58 PM PDT 24
Peak memory 218412 kb
Host smart-a0c4f325-3b55-42d2-9e8f-25221db1d460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368117193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1368117193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.3901237381
Short name T964
Test name
Test status
Simulation time 23916679490 ps
CPU time 1907.88 seconds
Started Mar 28 01:53:52 PM PDT 24
Finished Mar 28 02:25:40 PM PDT 24
Peak memory 439468 kb
Host smart-a2a76ad7-7f76-45d9-8aaf-80b58c1db853
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3901237381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3901237381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.1227908181
Short name T365
Test name
Test status
Simulation time 171843752 ps
CPU time 4.72 seconds
Started Mar 28 01:53:40 PM PDT 24
Finished Mar 28 01:53:45 PM PDT 24
Peak memory 216092 kb
Host smart-4c65b2d5-c0bc-424f-a48d-f14ab08b5635
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227908181 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.1227908181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.218164498
Short name T266
Test name
Test status
Simulation time 252181568 ps
CPU time 4.08 seconds
Started Mar 28 01:53:40 PM PDT 24
Finished Mar 28 01:53:44 PM PDT 24
Peak memory 216116 kb
Host smart-d7ff895f-c754-4943-8168-4ca93e087358
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218164498 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.kmac_test_vectors_kmac_xof.218164498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.3108430224
Short name T245
Test name
Test status
Simulation time 67584844736 ps
CPU time 1956.81 seconds
Started Mar 28 01:53:37 PM PDT 24
Finished Mar 28 02:26:14 PM PDT 24
Peak memory 400688 kb
Host smart-23db0ebd-e5a4-49dd-b0e0-d765ac75e581
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3108430224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3108430224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.2820762166
Short name T649
Test name
Test status
Simulation time 19056534539 ps
CPU time 1545.86 seconds
Started Mar 28 01:53:42 PM PDT 24
Finished Mar 28 02:19:28 PM PDT 24
Peak memory 372784 kb
Host smart-737bd984-7b55-4fbe-95d6-b120074986e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2820762166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.2820762166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.468408643
Short name T65
Test name
Test status
Simulation time 9547771335 ps
CPU time 768.65 seconds
Started Mar 28 01:53:39 PM PDT 24
Finished Mar 28 02:06:28 PM PDT 24
Peak memory 296284 kb
Host smart-92333f80-e114-47af-abeb-2de3fc52b05c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=468408643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.468408643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.1488615401
Short name T656
Test name
Test status
Simulation time 466783029196 ps
CPU time 4117.01 seconds
Started Mar 28 01:53:34 PM PDT 24
Finished Mar 28 03:02:13 PM PDT 24
Peak memory 660068 kb
Host smart-747b5f4f-74bf-4248-b8a8-98a9df823714
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1488615401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.1488615401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.394913347
Short name T121
Test name
Test status
Simulation time 56023591908 ps
CPU time 3576.3 seconds
Started Mar 28 01:53:33 PM PDT 24
Finished Mar 28 02:53:11 PM PDT 24
Peak memory 559412 kb
Host smart-2937e3fd-8616-4884-8fcf-4d269948001f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=394913347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.394913347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.2567418378
Short name T264
Test name
Test status
Simulation time 16236721 ps
CPU time 0.81 seconds
Started Mar 28 01:54:10 PM PDT 24
Finished Mar 28 01:54:11 PM PDT 24
Peak memory 205624 kb
Host smart-62288e3e-e63a-4bf7-9b37-c6943ff82857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567418378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2567418378 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.202383862
Short name T520
Test name
Test status
Simulation time 14774988293 ps
CPU time 46.72 seconds
Started Mar 28 01:54:11 PM PDT 24
Finished Mar 28 01:54:58 PM PDT 24
Peak memory 224324 kb
Host smart-60d2d268-b281-415c-80f0-31bf4197b1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202383862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.202383862 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.4195770686
Short name T681
Test name
Test status
Simulation time 735173899 ps
CPU time 60.85 seconds
Started Mar 28 01:53:52 PM PDT 24
Finished Mar 28 01:54:53 PM PDT 24
Peak memory 220408 kb
Host smart-f681afa5-beb8-4a73-a466-16b3d7bdae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195770686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.4195770686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.2561719958
Short name T362
Test name
Test status
Simulation time 31346171553 ps
CPU time 273.2 seconds
Started Mar 28 01:54:11 PM PDT 24
Finished Mar 28 01:58:44 PM PDT 24
Peak memory 245556 kb
Host smart-b1c6d139-05c5-4928-a02a-8b1c438695d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561719958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2561719958 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.1756156431
Short name T972
Test name
Test status
Simulation time 6004351217 ps
CPU time 236.2 seconds
Started Mar 28 01:54:13 PM PDT 24
Finished Mar 28 01:58:10 PM PDT 24
Peak memory 248952 kb
Host smart-88a66033-fcee-4a5d-ab0f-55960304fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756156431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1756156431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.2774689592
Short name T310
Test name
Test status
Simulation time 496805446 ps
CPU time 3.07 seconds
Started Mar 28 01:54:11 PM PDT 24
Finished Mar 28 01:54:14 PM PDT 24
Peak memory 207600 kb
Host smart-1c9de865-bac2-4642-a452-f11128a5ce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774689592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2774689592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.1628988051
Short name T481
Test name
Test status
Simulation time 1423410759 ps
CPU time 7.24 seconds
Started Mar 28 01:54:07 PM PDT 24
Finished Mar 28 01:54:15 PM PDT 24
Peak memory 217104 kb
Host smart-d30c83a2-feea-47b8-85da-208cc6cb9d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628988051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1628988051 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.893414974
Short name T459
Test name
Test status
Simulation time 73320320650 ps
CPU time 479.92 seconds
Started Mar 28 01:53:55 PM PDT 24
Finished Mar 28 02:01:55 PM PDT 24
Peak memory 260028 kb
Host smart-794b0107-376f-4839-96a9-73a46486db52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893414974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_an
d_output.893414974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.3203644999
Short name T407
Test name
Test status
Simulation time 7787375391 ps
CPU time 220.25 seconds
Started Mar 28 01:53:52 PM PDT 24
Finished Mar 28 01:57:33 PM PDT 24
Peak memory 240480 kb
Host smart-f80687d5-a156-4727-ae11-db7edaf1ec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203644999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3203644999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.2461122211
Short name T363
Test name
Test status
Simulation time 29454854307 ps
CPU time 61.51 seconds
Started Mar 28 01:53:53 PM PDT 24
Finished Mar 28 01:54:55 PM PDT 24
Peak memory 216464 kb
Host smart-ef830b00-00b5-40d0-8127-28bafd734f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461122211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2461122211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.2850256429
Short name T705
Test name
Test status
Simulation time 32787565295 ps
CPU time 446.89 seconds
Started Mar 28 01:54:10 PM PDT 24
Finished Mar 28 02:01:37 PM PDT 24
Peak memory 289468 kb
Host smart-564b2b77-2a20-457b-bf05-b3ab2cf43d31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2850256429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2850256429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3761127366
Short name T191
Test name
Test status
Simulation time 332607735 ps
CPU time 4.59 seconds
Started Mar 28 01:54:09 PM PDT 24
Finished Mar 28 01:54:14 PM PDT 24
Peak memory 216124 kb
Host smart-a777a9da-78ad-41d3-9115-6bb989d989d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761127366 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3761127366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.3340406401
Short name T872
Test name
Test status
Simulation time 242214069 ps
CPU time 4.18 seconds
Started Mar 28 01:54:11 PM PDT 24
Finished Mar 28 01:54:15 PM PDT 24
Peak memory 209084 kb
Host smart-76f84f10-036f-4a7f-90e7-3269333693c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340406401 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.3340406401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.1267906594
Short name T606
Test name
Test status
Simulation time 133618400876 ps
CPU time 1554.01 seconds
Started Mar 28 01:53:52 PM PDT 24
Finished Mar 28 02:19:46 PM PDT 24
Peak memory 389188 kb
Host smart-ed006f2c-832e-40f1-b57e-62da122d79e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1267906594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.1267906594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.3979352060
Short name T1049
Test name
Test status
Simulation time 81971088180 ps
CPU time 1495.11 seconds
Started Mar 28 01:53:51 PM PDT 24
Finished Mar 28 02:18:46 PM PDT 24
Peak memory 388036 kb
Host smart-8911dccc-1e37-4a3d-8bda-be1d024c3b88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3979352060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3979352060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.3642163911
Short name T400
Test name
Test status
Simulation time 65945119090 ps
CPU time 1515.98 seconds
Started Mar 28 01:54:11 PM PDT 24
Finished Mar 28 02:19:27 PM PDT 24
Peak memory 345604 kb
Host smart-84f9cf59-c47e-4077-b918-cec08f8ab300
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3642163911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3642163911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.1331063481
Short name T147
Test name
Test status
Simulation time 46402286526 ps
CPU time 946.74 seconds
Started Mar 28 01:54:11 PM PDT 24
Finished Mar 28 02:09:58 PM PDT 24
Peak memory 294912 kb
Host smart-8315a5a2-3851-48df-8c0a-851cdf1301be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1331063481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.1331063481 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.3740926398
Short name T701
Test name
Test status
Simulation time 129597311582 ps
CPU time 4136.45 seconds
Started Mar 28 01:54:10 PM PDT 24
Finished Mar 28 03:03:07 PM PDT 24
Peak memory 645056 kb
Host smart-854d23e0-dd92-45da-bfd6-274c4cca9195
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3740926398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.3740926398 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.584510702
Short name T911
Test name
Test status
Simulation time 153444280381 ps
CPU time 3606.81 seconds
Started Mar 28 01:54:10 PM PDT 24
Finished Mar 28 02:54:17 PM PDT 24
Peak memory 556156 kb
Host smart-122382f6-05b8-42a1-b5f2-29b258bd684c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=584510702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.584510702 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.2195442768
Short name T324
Test name
Test status
Simulation time 36815486 ps
CPU time 0.73 seconds
Started Mar 28 01:54:56 PM PDT 24
Finished Mar 28 01:54:57 PM PDT 24
Peak memory 205580 kb
Host smart-a981d82d-96ec-4254-9db3-7b4de3069adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195442768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2195442768 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.946969940
Short name T279
Test name
Test status
Simulation time 43441637749 ps
CPU time 291.83 seconds
Started Mar 28 01:54:31 PM PDT 24
Finished Mar 28 01:59:23 PM PDT 24
Peak memory 245472 kb
Host smart-aabf4b57-c923-4a6d-99ec-2b91a29a8b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946969940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.946969940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.1237817669
Short name T432
Test name
Test status
Simulation time 68100608722 ps
CPU time 532.56 seconds
Started Mar 28 01:54:33 PM PDT 24
Finished Mar 28 02:03:26 PM PDT 24
Peak memory 240672 kb
Host smart-1eb8e80b-fc08-47eb-b4bf-7528ce1d6a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237817669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1237817669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.3946700411
Short name T1060
Test name
Test status
Simulation time 35434117322 ps
CPU time 139.23 seconds
Started Mar 28 01:54:32 PM PDT 24
Finished Mar 28 01:56:52 PM PDT 24
Peak memory 233228 kb
Host smart-db62176a-79ca-4b0e-9aa5-f845af15aaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946700411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3946700411 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2615224508
Short name T577
Test name
Test status
Simulation time 18480894373 ps
CPU time 200.96 seconds
Started Mar 28 01:54:32 PM PDT 24
Finished Mar 28 01:57:54 PM PDT 24
Peak memory 252476 kb
Host smart-97845e67-cd77-4100-9744-22ed67ba3f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615224508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2615224508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.3875386895
Short name T759
Test name
Test status
Simulation time 772437983 ps
CPU time 2.48 seconds
Started Mar 28 01:54:29 PM PDT 24
Finished Mar 28 01:54:32 PM PDT 24
Peak memory 207424 kb
Host smart-ed07d237-c691-42e9-8d8d-4b49504630e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875386895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3875386895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.4185374074
Short name T335
Test name
Test status
Simulation time 502999786 ps
CPU time 3.59 seconds
Started Mar 28 01:54:55 PM PDT 24
Finished Mar 28 01:54:59 PM PDT 24
Peak memory 220552 kb
Host smart-841a06b6-eab0-4f96-b65e-2b77d4317438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185374074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.4185374074 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.810370272
Short name T253
Test name
Test status
Simulation time 123887170401 ps
CPU time 313.86 seconds
Started Mar 28 01:54:12 PM PDT 24
Finished Mar 28 01:59:26 PM PDT 24
Peak memory 247344 kb
Host smart-00331edd-b8d8-4a61-ba5b-7f8404fea3a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810370272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_an
d_output.810370272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.3576304226
Short name T884
Test name
Test status
Simulation time 3842050174 ps
CPU time 92.85 seconds
Started Mar 28 01:54:09 PM PDT 24
Finished Mar 28 01:55:42 PM PDT 24
Peak memory 229680 kb
Host smart-3aee08df-d5e9-4eac-ab7f-f63b5756738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576304226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3576304226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.1629377404
Short name T752
Test name
Test status
Simulation time 4174595899 ps
CPU time 54.91 seconds
Started Mar 28 01:54:10 PM PDT 24
Finished Mar 28 01:55:05 PM PDT 24
Peak memory 224328 kb
Host smart-dcdbc912-eec6-4da4-a3ba-c08ec6578028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629377404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1629377404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.753775811
Short name T360
Test name
Test status
Simulation time 11134178133 ps
CPU time 161.1 seconds
Started Mar 28 01:54:57 PM PDT 24
Finished Mar 28 01:57:38 PM PDT 24
Peak memory 251868 kb
Host smart-8bf9b6cc-79ce-4025-abe7-d24c1e90a64e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=753775811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.753775811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.387700339
Short name T358
Test name
Test status
Simulation time 68108332 ps
CPU time 3.62 seconds
Started Mar 28 01:54:30 PM PDT 24
Finished Mar 28 01:54:34 PM PDT 24
Peak memory 216076 kb
Host smart-f3574a88-c8db-48ee-90af-e3e25536fe61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387700339 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.kmac_test_vectors_kmac.387700339 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3820051708
Short name T403
Test name
Test status
Simulation time 2207833273 ps
CPU time 5.78 seconds
Started Mar 28 01:54:30 PM PDT 24
Finished Mar 28 01:54:36 PM PDT 24
Peak memory 216156 kb
Host smart-6df88509-2f2c-4023-bceb-211ae4bc56fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820051708 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3820051708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.2920851578
Short name T1073
Test name
Test status
Simulation time 353005988098 ps
CPU time 2131.77 seconds
Started Mar 28 01:54:30 PM PDT 24
Finished Mar 28 02:30:02 PM PDT 24
Peak memory 398376 kb
Host smart-c2455bcf-57b4-466a-9da0-1ed1610671ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2920851578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.2920851578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.2753039183
Short name T504
Test name
Test status
Simulation time 66782947716 ps
CPU time 1523.49 seconds
Started Mar 28 01:54:33 PM PDT 24
Finished Mar 28 02:19:57 PM PDT 24
Peak memory 387364 kb
Host smart-27c67c52-f7db-4f99-b481-e3b5f0020444
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2753039183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.2753039183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.4148979552
Short name T696
Test name
Test status
Simulation time 192634433275 ps
CPU time 1280.23 seconds
Started Mar 28 01:54:30 PM PDT 24
Finished Mar 28 02:15:50 PM PDT 24
Peak memory 330940 kb
Host smart-75b7329b-ffcb-4276-aad9-4c4cae3e072b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4148979552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.4148979552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.2470404772
Short name T201
Test name
Test status
Simulation time 17704957435 ps
CPU time 780.5 seconds
Started Mar 28 01:54:31 PM PDT 24
Finished Mar 28 02:07:31 PM PDT 24
Peak memory 289348 kb
Host smart-02f3ea8d-6b10-4044-9f9d-24c71c57729c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2470404772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.2470404772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.986758159
Short name T773
Test name
Test status
Simulation time 526392411618 ps
CPU time 5234.63 seconds
Started Mar 28 01:54:30 PM PDT 24
Finished Mar 28 03:21:45 PM PDT 24
Peak memory 655580 kb
Host smart-c5fac633-711e-4540-9d89-d5beda6a892e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=986758159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.986758159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.3114051185
Short name T939
Test name
Test status
Simulation time 178034623595 ps
CPU time 3546.62 seconds
Started Mar 28 01:54:29 PM PDT 24
Finished Mar 28 02:53:36 PM PDT 24
Peak memory 550948 kb
Host smart-3c343388-d5d5-4125-be44-f51b6b5cdd87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3114051185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3114051185 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.3886249752
Short name T944
Test name
Test status
Simulation time 38424064 ps
CPU time 0.76 seconds
Started Mar 28 01:55:27 PM PDT 24
Finished Mar 28 01:55:28 PM PDT 24
Peak memory 205560 kb
Host smart-cd0d7a87-e68d-44a0-9ee4-8e7404325832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886249752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3886249752 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.2423718137
Short name T853
Test name
Test status
Simulation time 2771669783 ps
CPU time 104.46 seconds
Started Mar 28 01:54:57 PM PDT 24
Finished Mar 28 01:56:41 PM PDT 24
Peak memory 232016 kb
Host smart-0e6d79d6-c4ce-449a-9af3-8e8729583719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423718137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2423718137 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.800240818
Short name T686
Test name
Test status
Simulation time 8542963293 ps
CPU time 211.02 seconds
Started Mar 28 01:54:55 PM PDT 24
Finished Mar 28 01:58:26 PM PDT 24
Peak memory 224940 kb
Host smart-7123c599-b3ab-4fcb-ac8c-f65756a315b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800240818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.800240818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.2465339074
Short name T462
Test name
Test status
Simulation time 642048528 ps
CPU time 10.24 seconds
Started Mar 28 01:54:58 PM PDT 24
Finished Mar 28 01:55:09 PM PDT 24
Peak memory 216140 kb
Host smart-ea87c456-f1d3-4ade-9161-001e08d4203c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465339074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2465339074 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.2360649651
Short name T580
Test name
Test status
Simulation time 3173350552 ps
CPU time 176.22 seconds
Started Mar 28 01:55:25 PM PDT 24
Finished Mar 28 01:58:22 PM PDT 24
Peak memory 248932 kb
Host smart-d5a274d1-b969-444a-8fc9-a59a943ce03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360649651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2360649651 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.1630896223
Short name T122
Test name
Test status
Simulation time 4967302852 ps
CPU time 5.04 seconds
Started Mar 28 01:55:26 PM PDT 24
Finished Mar 28 01:55:31 PM PDT 24
Peak memory 207784 kb
Host smart-ceadff92-3c19-4554-a631-e5676e33dc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630896223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1630896223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.1734046804
Short name T811
Test name
Test status
Simulation time 39089046 ps
CPU time 1.27 seconds
Started Mar 28 01:55:26 PM PDT 24
Finished Mar 28 01:55:27 PM PDT 24
Peak memory 216040 kb
Host smart-82c5903f-5ae8-4b2b-bd00-e595dcb796ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734046804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1734046804 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.2852273303
Short name T399
Test name
Test status
Simulation time 6387294785 ps
CPU time 592.1 seconds
Started Mar 28 01:54:56 PM PDT 24
Finished Mar 28 02:04:48 PM PDT 24
Peak memory 278984 kb
Host smart-be336c89-2e7e-4bf6-ba90-eb24ab2aee81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852273303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.2852273303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.3156157852
Short name T867
Test name
Test status
Simulation time 22088758253 ps
CPU time 424.14 seconds
Started Mar 28 01:54:56 PM PDT 24
Finished Mar 28 02:02:00 PM PDT 24
Peak memory 250268 kb
Host smart-d20dd698-b6e9-47d5-b131-5fd1197ca72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156157852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3156157852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.2809870864
Short name T919
Test name
Test status
Simulation time 21164216362 ps
CPU time 58.64 seconds
Started Mar 28 01:54:57 PM PDT 24
Finished Mar 28 01:55:56 PM PDT 24
Peak memory 222240 kb
Host smart-d732b918-4b2b-4df0-b6bd-014cd72eedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809870864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2809870864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.2315869399
Short name T576
Test name
Test status
Simulation time 7557281071 ps
CPU time 74.61 seconds
Started Mar 28 01:55:25 PM PDT 24
Finished Mar 28 01:56:39 PM PDT 24
Peak memory 225036 kb
Host smart-cd8422ab-a00d-42c1-b7a5-b9ffe20ef1d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2315869399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2315869399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.82634567
Short name T232
Test name
Test status
Simulation time 173066468 ps
CPU time 4.85 seconds
Started Mar 28 01:54:57 PM PDT 24
Finished Mar 28 01:55:02 PM PDT 24
Peak memory 216088 kb
Host smart-79003718-deac-4bce-8ba6-704c39cdc509
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82634567 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.kmac_test_vectors_kmac.82634567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.1268051806
Short name T511
Test name
Test status
Simulation time 180215367 ps
CPU time 4.7 seconds
Started Mar 28 01:54:56 PM PDT 24
Finished Mar 28 01:55:01 PM PDT 24
Peak memory 216184 kb
Host smart-c60c6e84-aee2-4b5c-bd93-fe035a0cce4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268051806 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.1268051806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.3452711283
Short name T234
Test name
Test status
Simulation time 132481593129 ps
CPU time 1872.12 seconds
Started Mar 28 01:54:57 PM PDT 24
Finished Mar 28 02:26:09 PM PDT 24
Peak memory 392668 kb
Host smart-ab581205-8677-440b-a4ae-5306665ffa4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3452711283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.3452711283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.496089519
Short name T721
Test name
Test status
Simulation time 18330755169 ps
CPU time 1512.95 seconds
Started Mar 28 01:54:56 PM PDT 24
Finished Mar 28 02:20:10 PM PDT 24
Peak memory 375772 kb
Host smart-4ab627bc-3816-4f5c-a268-424e0bb0d707
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=496089519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.496089519 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.2711350580
Short name T406
Test name
Test status
Simulation time 58787977830 ps
CPU time 1310.78 seconds
Started Mar 28 01:54:55 PM PDT 24
Finished Mar 28 02:16:46 PM PDT 24
Peak memory 329520 kb
Host smart-c982146e-558d-4854-bb34-b7a64eb538c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2711350580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2711350580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.542992881
Short name T946
Test name
Test status
Simulation time 9490612339 ps
CPU time 778.93 seconds
Started Mar 28 01:54:55 PM PDT 24
Finished Mar 28 02:07:54 PM PDT 24
Peak memory 295100 kb
Host smart-e6ee470e-1ec6-4baa-b081-c721f900b61f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=542992881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.542992881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.2807248397
Short name T453
Test name
Test status
Simulation time 1076647529797 ps
CPU time 5754.33 seconds
Started Mar 28 01:54:57 PM PDT 24
Finished Mar 28 03:30:52 PM PDT 24
Peak memory 657160 kb
Host smart-8f4e3446-9499-453a-b829-cab5cc5228fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2807248397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.2807248397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.818469394
Short name T699
Test name
Test status
Simulation time 423761519221 ps
CPU time 4265.85 seconds
Started Mar 28 01:54:55 PM PDT 24
Finished Mar 28 03:06:02 PM PDT 24
Peak memory 559948 kb
Host smart-e4d129ee-2709-4aa8-9ce1-211a6e4d45bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=818469394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.818469394 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.2822162359
Short name T688
Test name
Test status
Simulation time 14923413 ps
CPU time 0.79 seconds
Started Mar 28 01:55:49 PM PDT 24
Finished Mar 28 01:55:50 PM PDT 24
Peak memory 205548 kb
Host smart-53e50bdd-4117-467d-a018-b9c8f0236c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822162359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2822162359 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.3850518525
Short name T1051
Test name
Test status
Simulation time 11072363789 ps
CPU time 106.41 seconds
Started Mar 28 01:55:50 PM PDT 24
Finished Mar 28 01:57:37 PM PDT 24
Peak memory 231172 kb
Host smart-5891b1fe-d1a0-449f-a193-b596cf2efdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850518525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3850518525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.3298333787
Short name T657
Test name
Test status
Simulation time 2220086667 ps
CPU time 187.57 seconds
Started Mar 28 01:55:29 PM PDT 24
Finished Mar 28 01:58:36 PM PDT 24
Peak memory 224956 kb
Host smart-bdc0afaf-e172-4391-b20e-85b7eecaa2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298333787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3298333787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.3922730343
Short name T376
Test name
Test status
Simulation time 19688233545 ps
CPU time 203.3 seconds
Started Mar 28 01:55:48 PM PDT 24
Finished Mar 28 01:59:12 PM PDT 24
Peak memory 238672 kb
Host smart-0a679ede-f8f8-4228-8585-77708bc2073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922730343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3922730343 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.471874650
Short name T390
Test name
Test status
Simulation time 11049071716 ps
CPU time 217.56 seconds
Started Mar 28 01:55:53 PM PDT 24
Finished Mar 28 01:59:30 PM PDT 24
Peak memory 248892 kb
Host smart-38162292-0167-4443-b37d-9a668e84af0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471874650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.471874650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.2158321252
Short name T988
Test name
Test status
Simulation time 8530814863 ps
CPU time 5.01 seconds
Started Mar 28 01:55:50 PM PDT 24
Finished Mar 28 01:55:55 PM PDT 24
Peak memory 207748 kb
Host smart-1cf14bc5-8736-4910-a4d5-9fdc3b9e95cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158321252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2158321252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.854186821
Short name T702
Test name
Test status
Simulation time 1137295990 ps
CPU time 27.66 seconds
Started Mar 28 01:55:48 PM PDT 24
Finished Mar 28 01:56:16 PM PDT 24
Peak memory 232512 kb
Host smart-d6c36518-d748-4b7f-b9af-40ec2f1d0820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854186821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.854186821 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.3959937494
Short name T457
Test name
Test status
Simulation time 230817324784 ps
CPU time 1271.14 seconds
Started Mar 28 01:55:25 PM PDT 24
Finished Mar 28 02:16:37 PM PDT 24
Peak memory 331460 kb
Host smart-37fe2722-7b68-40c6-b1d2-506fbe4bf42c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959937494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.3959937494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.3956738197
Short name T277
Test name
Test status
Simulation time 4201123120 ps
CPU time 83.09 seconds
Started Mar 28 01:55:27 PM PDT 24
Finished Mar 28 01:56:50 PM PDT 24
Peak memory 226300 kb
Host smart-874fdffe-c182-41c9-8656-c0dc0bfc1f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956738197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3956738197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.3864615912
Short name T647
Test name
Test status
Simulation time 2357223263 ps
CPU time 37.87 seconds
Started Mar 28 01:55:27 PM PDT 24
Finished Mar 28 01:56:06 PM PDT 24
Peak memory 219204 kb
Host smart-96993598-70db-46fd-8bf6-c03219036e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864615912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3864615912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.3792316462
Short name T64
Test name
Test status
Simulation time 258495123 ps
CPU time 4.65 seconds
Started Mar 28 01:55:48 PM PDT 24
Finished Mar 28 01:55:53 PM PDT 24
Peak memory 216208 kb
Host smart-71f0a242-66fa-4a41-8653-5c2b768669c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3792316462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3792316462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.904884188
Short name T846
Test name
Test status
Simulation time 383450907 ps
CPU time 4.71 seconds
Started Mar 28 01:55:28 PM PDT 24
Finished Mar 28 01:55:33 PM PDT 24
Peak memory 215936 kb
Host smart-6840b011-1d74-4299-912a-64081b80c1a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904884188 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.kmac_test_vectors_kmac.904884188 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.1118295523
Short name T242
Test name
Test status
Simulation time 182569835 ps
CPU time 5.18 seconds
Started Mar 28 01:55:28 PM PDT 24
Finished Mar 28 01:55:34 PM PDT 24
Peak memory 215948 kb
Host smart-57e6c993-9fff-4f7e-95e8-1990696d79f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118295523 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.1118295523 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.4290655992
Short name T1065
Test name
Test status
Simulation time 338904972833 ps
CPU time 1967.93 seconds
Started Mar 28 01:55:28 PM PDT 24
Finished Mar 28 02:28:16 PM PDT 24
Peak memory 395044 kb
Host smart-44cf999b-4421-4f3b-9c73-f12c624cea64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4290655992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.4290655992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.4181112109
Short name T478
Test name
Test status
Simulation time 344217699940 ps
CPU time 1516.17 seconds
Started Mar 28 01:55:26 PM PDT 24
Finished Mar 28 02:20:44 PM PDT 24
Peak memory 363972 kb
Host smart-e846a20d-318b-4e06-b2cc-5c382477008b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4181112109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.4181112109 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.1807363626
Short name T293
Test name
Test status
Simulation time 14125149855 ps
CPU time 1161.73 seconds
Started Mar 28 01:55:29 PM PDT 24
Finished Mar 28 02:14:51 PM PDT 24
Peak memory 334152 kb
Host smart-f1ec1796-74ef-4d3b-8c54-ac0c8a0c29ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1807363626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.1807363626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.815249631
Short name T882
Test name
Test status
Simulation time 33184621866 ps
CPU time 920.6 seconds
Started Mar 28 01:55:29 PM PDT 24
Finished Mar 28 02:10:49 PM PDT 24
Peak memory 298604 kb
Host smart-d9fe6de5-fe45-4b3c-a5ae-5b4ae11d584f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=815249631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.815249631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.4027140857
Short name T958
Test name
Test status
Simulation time 679068613255 ps
CPU time 4739.9 seconds
Started Mar 28 01:55:28 PM PDT 24
Finished Mar 28 03:14:29 PM PDT 24
Peak memory 637568 kb
Host smart-5bd64168-4d8e-4885-af30-a17986d3b22c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4027140857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.4027140857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_alert_test.1382113076
Short name T402
Test name
Test status
Simulation time 54129462 ps
CPU time 0.81 seconds
Started Mar 28 01:56:12 PM PDT 24
Finished Mar 28 01:56:13 PM PDT 24
Peak memory 205536 kb
Host smart-dce8887f-d997-4483-8a5f-32b3cd97388b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382113076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1382113076 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.1430462931
Short name T353
Test name
Test status
Simulation time 38744505848 ps
CPU time 202.15 seconds
Started Mar 28 01:56:09 PM PDT 24
Finished Mar 28 01:59:31 PM PDT 24
Peak memory 239684 kb
Host smart-eb2a8356-33a6-41c6-802b-d2187feaf0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430462931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1430462931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.2453381955
Short name T80
Test name
Test status
Simulation time 2963503831 ps
CPU time 91.01 seconds
Started Mar 28 01:55:51 PM PDT 24
Finished Mar 28 01:57:22 PM PDT 24
Peak memory 232916 kb
Host smart-ce6546b7-0262-455e-bfc7-391352189620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453381955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2453381955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.4219051248
Short name T920
Test name
Test status
Simulation time 14408130222 ps
CPU time 174.31 seconds
Started Mar 28 01:56:08 PM PDT 24
Finished Mar 28 01:59:02 PM PDT 24
Peak memory 236732 kb
Host smart-24232cd1-3047-4fdb-9b8d-8eb466e3a7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219051248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.4219051248 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.355309330
Short name T392
Test name
Test status
Simulation time 375015577 ps
CPU time 27.86 seconds
Started Mar 28 01:56:08 PM PDT 24
Finished Mar 28 01:56:36 PM PDT 24
Peak memory 236448 kb
Host smart-a2d5dde2-1685-45d9-9561-a65051081eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355309330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.355309330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.1702267599
Short name T718
Test name
Test status
Simulation time 5567275153 ps
CPU time 5.8 seconds
Started Mar 28 01:56:08 PM PDT 24
Finished Mar 28 01:56:14 PM PDT 24
Peak memory 207724 kb
Host smart-e34fd0a9-b085-41e6-853d-f64a4af9fdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702267599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1702267599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.2313953752
Short name T447
Test name
Test status
Simulation time 49697340 ps
CPU time 1.34 seconds
Started Mar 28 01:56:08 PM PDT 24
Finished Mar 28 01:56:09 PM PDT 24
Peak memory 216972 kb
Host smart-d1b5c47c-8e91-4c63-ad1a-12f0c4f44914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313953752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2313953752 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.3958096485
Short name T460
Test name
Test status
Simulation time 22075698822 ps
CPU time 1880.69 seconds
Started Mar 28 01:55:53 PM PDT 24
Finished Mar 28 02:27:14 PM PDT 24
Peak memory 434720 kb
Host smart-da1d1951-5745-48fe-8a14-ba5c8756b1ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958096485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.3958096485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.48518850
Short name T345
Test name
Test status
Simulation time 59179416515 ps
CPU time 413.15 seconds
Started Mar 28 01:55:50 PM PDT 24
Finished Mar 28 02:02:43 PM PDT 24
Peak memory 250120 kb
Host smart-41090e36-5896-4c1a-a7e6-9df7ba749c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48518850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.48518850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.1767320325
Short name T997
Test name
Test status
Simulation time 9897941031 ps
CPU time 46.31 seconds
Started Mar 28 01:55:53 PM PDT 24
Finished Mar 28 01:56:40 PM PDT 24
Peak memory 217080 kb
Host smart-929d05d4-11dd-4475-9027-3fe7fe739f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767320325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1767320325 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.2893399047
Short name T36
Test name
Test status
Simulation time 6980709765 ps
CPU time 568.64 seconds
Started Mar 28 01:56:09 PM PDT 24
Finished Mar 28 02:05:38 PM PDT 24
Peak memory 284736 kb
Host smart-b43b9d5a-9674-4dbf-a005-7697339507a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2893399047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2893399047 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.3525942582
Short name T586
Test name
Test status
Simulation time 176191079 ps
CPU time 4.8 seconds
Started Mar 28 01:56:07 PM PDT 24
Finished Mar 28 01:56:12 PM PDT 24
Peak memory 216112 kb
Host smart-a02dc998-355d-4163-8a4d-27361f4ca434
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525942582 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.3525942582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.126025381
Short name T855
Test name
Test status
Simulation time 130381059 ps
CPU time 4.4 seconds
Started Mar 28 01:56:08 PM PDT 24
Finished Mar 28 01:56:13 PM PDT 24
Peak memory 216140 kb
Host smart-3232fada-77e2-44a7-a5bf-d96627e71000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126025381 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.kmac_test_vectors_kmac_xof.126025381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.3350637387
Short name T982
Test name
Test status
Simulation time 94902233756 ps
CPU time 2073.38 seconds
Started Mar 28 01:55:49 PM PDT 24
Finished Mar 28 02:30:23 PM PDT 24
Peak memory 375980 kb
Host smart-7bf3ca45-4938-4d7f-bc8b-b33b4c7421e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3350637387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3350637387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.1385038114
Short name T881
Test name
Test status
Simulation time 64176199130 ps
CPU time 1837.76 seconds
Started Mar 28 01:55:49 PM PDT 24
Finished Mar 28 02:26:27 PM PDT 24
Peak memory 391788 kb
Host smart-95bbd190-6a3f-4d31-98fe-16343d673abc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1385038114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.1385038114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.3972712316
Short name T583
Test name
Test status
Simulation time 715693396918 ps
CPU time 1774.3 seconds
Started Mar 28 01:55:49 PM PDT 24
Finished Mar 28 02:25:23 PM PDT 24
Peak memory 340776 kb
Host smart-0f6685b9-4ea7-4d38-ac6b-05f2e2a10b4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3972712316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3972712316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.268477519
Short name T246
Test name
Test status
Simulation time 73507468707 ps
CPU time 878 seconds
Started Mar 28 01:55:50 PM PDT 24
Finished Mar 28 02:10:28 PM PDT 24
Peak memory 296564 kb
Host smart-7c0f5469-6409-4feb-ab7c-6e995c23ed62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=268477519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.268477519 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.2687877996
Short name T652
Test name
Test status
Simulation time 51304139136 ps
CPU time 4014.91 seconds
Started Mar 28 01:55:51 PM PDT 24
Finished Mar 28 03:02:46 PM PDT 24
Peak memory 649212 kb
Host smart-c4d596fe-570d-4a1b-92d5-61ff119366af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2687877996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2687877996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.1309994263
Short name T487
Test name
Test status
Simulation time 220309908901 ps
CPU time 4218.16 seconds
Started Mar 28 01:56:09 PM PDT 24
Finished Mar 28 03:06:27 PM PDT 24
Peak memory 558640 kb
Host smart-60f7d63f-e4b7-4b2f-8bf1-f3009f918b9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1309994263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.1309994263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.2146906875
Short name T289
Test name
Test status
Simulation time 16360920 ps
CPU time 0.8 seconds
Started Mar 28 01:56:29 PM PDT 24
Finished Mar 28 01:56:30 PM PDT 24
Peak memory 205548 kb
Host smart-f6e24574-4d58-48cd-a24c-c12174d5a507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146906875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2146906875 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.3626212697
Short name T767
Test name
Test status
Simulation time 3173224149 ps
CPU time 222.39 seconds
Started Mar 28 01:56:33 PM PDT 24
Finished Mar 28 02:00:20 PM PDT 24
Peak memory 242428 kb
Host smart-139b10ca-9fff-49ad-9fcd-de53372cf666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626212697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3626212697 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.4178156660
Short name T129
Test name
Test status
Simulation time 3960262925 ps
CPU time 33.46 seconds
Started Mar 28 01:56:12 PM PDT 24
Finished Mar 28 01:56:46 PM PDT 24
Peak memory 218404 kb
Host smart-2a4cf676-8201-4944-8e8f-167a0d914805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178156660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.4178156660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_error.3780063464
Short name T558
Test name
Test status
Simulation time 11310896573 ps
CPU time 253.33 seconds
Started Mar 28 01:56:32 PM PDT 24
Finished Mar 28 02:00:46 PM PDT 24
Peak memory 250880 kb
Host smart-5d0f8f59-97b3-453f-a1a7-bcf88beb9c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780063464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3780063464 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.4035283755
Short name T722
Test name
Test status
Simulation time 2328682425 ps
CPU time 4.07 seconds
Started Mar 28 01:56:29 PM PDT 24
Finished Mar 28 01:56:33 PM PDT 24
Peak memory 207768 kb
Host smart-2f3b3c3e-b416-46f8-bd4d-913f8bdf74ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035283755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.4035283755 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.1787631481
Short name T295
Test name
Test status
Simulation time 64763235 ps
CPU time 1.36 seconds
Started Mar 28 01:56:28 PM PDT 24
Finished Mar 28 01:56:29 PM PDT 24
Peak memory 215980 kb
Host smart-c107487a-e5f2-4234-9d58-72ebbe7dbde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787631481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1787631481 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.3201742158
Short name T906
Test name
Test status
Simulation time 53180029203 ps
CPU time 1275.48 seconds
Started Mar 28 01:56:13 PM PDT 24
Finished Mar 28 02:17:28 PM PDT 24
Peak memory 320012 kb
Host smart-c7b727df-042b-4464-8213-ab7219972364
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201742158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.3201742158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.216269063
Short name T673
Test name
Test status
Simulation time 46526127195 ps
CPU time 259.21 seconds
Started Mar 28 01:56:14 PM PDT 24
Finished Mar 28 02:00:33 PM PDT 24
Peak memory 239580 kb
Host smart-5f6779ae-56c7-4098-9e27-fc12cb22bd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216269063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.216269063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.2698645896
Short name T483
Test name
Test status
Simulation time 3501883872 ps
CPU time 53.17 seconds
Started Mar 28 01:56:02 PM PDT 24
Finished Mar 28 01:56:56 PM PDT 24
Peak memory 219876 kb
Host smart-d32b43a4-41b8-4459-bdde-67c20564175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698645896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2698645896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.931548480
Short name T707
Test name
Test status
Simulation time 11932632427 ps
CPU time 932.69 seconds
Started Mar 28 01:56:28 PM PDT 24
Finished Mar 28 02:12:01 PM PDT 24
Peak memory 336976 kb
Host smart-3104efc8-62df-4557-8044-92a12a7a1d58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=931548480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.931548480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_stress_all_with_rand_reset.2334590804
Short name T959
Test name
Test status
Simulation time 131805277457 ps
CPU time 1607.21 seconds
Started Mar 28 01:56:34 PM PDT 24
Finished Mar 28 02:23:25 PM PDT 24
Peak memory 373192 kb
Host smart-99a2e3d9-f3e7-4dd8-8693-eb82d88d0d46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334590804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.2334590804 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.491632932
Short name T519
Test name
Test status
Simulation time 172692615 ps
CPU time 4.76 seconds
Started Mar 28 01:56:28 PM PDT 24
Finished Mar 28 01:56:33 PM PDT 24
Peak memory 216052 kb
Host smart-b51f694a-a6af-4958-8c61-247f76f0ff38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491632932 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.kmac_test_vectors_kmac.491632932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.2966300268
Short name T838
Test name
Test status
Simulation time 175316393 ps
CPU time 4.35 seconds
Started Mar 28 01:56:28 PM PDT 24
Finished Mar 28 01:56:32 PM PDT 24
Peak memory 216088 kb
Host smart-489a5966-1c1c-4246-a791-36d623cdf974
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966300268 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.2966300268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.2940746429
Short name T485
Test name
Test status
Simulation time 100813232125 ps
CPU time 2003.7 seconds
Started Mar 28 01:56:12 PM PDT 24
Finished Mar 28 02:29:36 PM PDT 24
Peak memory 391128 kb
Host smart-8f24febf-efa3-4bbb-90f3-cde1c70dc535
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2940746429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.2940746429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.432200273
Short name T618
Test name
Test status
Simulation time 96042590522 ps
CPU time 1881.58 seconds
Started Mar 28 01:56:28 PM PDT 24
Finished Mar 28 02:27:50 PM PDT 24
Peak memory 377400 kb
Host smart-7017e0cd-27a7-4ee2-8fbc-40692f8e135b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=432200273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.432200273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.2047938693
Short name T769
Test name
Test status
Simulation time 13410966082 ps
CPU time 1160.44 seconds
Started Mar 28 01:56:28 PM PDT 24
Finished Mar 28 02:15:48 PM PDT 24
Peak memory 331088 kb
Host smart-0703f2da-c67b-4547-9e93-b1f126ec2fa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2047938693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.2047938693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.3327820875
Short name T197
Test name
Test status
Simulation time 43132898641 ps
CPU time 993.94 seconds
Started Mar 28 01:56:41 PM PDT 24
Finished Mar 28 02:13:16 PM PDT 24
Peak memory 293296 kb
Host smart-b125e848-ae45-472d-b543-c0d22f2bfbe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3327820875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3327820875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.3176851353
Short name T268
Test name
Test status
Simulation time 179686974722 ps
CPU time 4695.71 seconds
Started Mar 28 01:56:28 PM PDT 24
Finished Mar 28 03:14:44 PM PDT 24
Peak memory 643500 kb
Host smart-34abc173-4f71-4c49-acbd-4ed509439e2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3176851353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.3176851353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.385844442
Short name T758
Test name
Test status
Simulation time 44592338749 ps
CPU time 3437.6 seconds
Started Mar 28 01:56:26 PM PDT 24
Finished Mar 28 02:53:44 PM PDT 24
Peak memory 560680 kb
Host smart-0f4e1c01-0d39-46d9-b6ff-f409749255d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=385844442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.385844442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.2761354803
Short name T41
Test name
Test status
Simulation time 24947747 ps
CPU time 0.8 seconds
Started Mar 28 01:56:48 PM PDT 24
Finished Mar 28 01:56:49 PM PDT 24
Peak memory 205424 kb
Host smart-8d6c8994-c853-4fab-8065-c4f707b77aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761354803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2761354803 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.4167412011
Short name T437
Test name
Test status
Simulation time 9587319582 ps
CPU time 240.07 seconds
Started Mar 28 01:56:55 PM PDT 24
Finished Mar 28 02:00:56 PM PDT 24
Peak memory 242576 kb
Host smart-d86fd619-5420-4970-b2f2-f2dce169286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167412011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.4167412011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.2385497740
Short name T776
Test name
Test status
Simulation time 5322992787 ps
CPU time 125.97 seconds
Started Mar 28 01:56:44 PM PDT 24
Finished Mar 28 01:58:52 PM PDT 24
Peak memory 224312 kb
Host smart-8ea21605-b512-40d0-9fe7-360d340a7b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385497740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.2385497740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.728346898
Short name T278
Test name
Test status
Simulation time 14561115970 ps
CPU time 98.82 seconds
Started Mar 28 01:56:45 PM PDT 24
Finished Mar 28 01:58:25 PM PDT 24
Peak memory 227560 kb
Host smart-7eb83a83-7fc6-4c04-8c4c-25ea60bc0cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728346898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.728346898 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.1537712737
Short name T31
Test name
Test status
Simulation time 4326268979 ps
CPU time 91.76 seconds
Started Mar 28 01:56:45 PM PDT 24
Finished Mar 28 01:58:18 PM PDT 24
Peak memory 239044 kb
Host smart-28e9221f-59d9-4745-b822-e48f6feb825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537712737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1537712737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.17591219
Short name T659
Test name
Test status
Simulation time 2095467819 ps
CPU time 4.18 seconds
Started Mar 28 01:56:58 PM PDT 24
Finished Mar 28 01:57:02 PM PDT 24
Peak memory 207660 kb
Host smart-86a16e2e-3207-4bf3-9927-fffe8c7931b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17591219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.17591219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1395287055
Short name T8
Test name
Test status
Simulation time 48354055 ps
CPU time 1.49 seconds
Started Mar 28 01:56:50 PM PDT 24
Finished Mar 28 01:56:52 PM PDT 24
Peak memory 216028 kb
Host smart-5c5799a6-f78e-42ad-a179-84f1fe731979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395287055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1395287055 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.4104782337
Short name T1006
Test name
Test status
Simulation time 9084132805 ps
CPU time 189.29 seconds
Started Mar 28 01:56:29 PM PDT 24
Finished Mar 28 01:59:38 PM PDT 24
Peak memory 240632 kb
Host smart-3181b59e-921d-440b-b37d-c26809d25cfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104782337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.4104782337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.1619314807
Short name T509
Test name
Test status
Simulation time 11907886892 ps
CPU time 226.79 seconds
Started Mar 28 01:56:45 PM PDT 24
Finished Mar 28 02:00:33 PM PDT 24
Peak memory 240032 kb
Host smart-d41dfa54-ec6e-48c2-8837-a6b1a064a8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619314807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1619314807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.2989490854
Short name T740
Test name
Test status
Simulation time 3242795894 ps
CPU time 45.02 seconds
Started Mar 28 01:56:33 PM PDT 24
Finished Mar 28 01:57:23 PM PDT 24
Peak memory 219152 kb
Host smart-97bd48b2-6819-48ff-b7c0-74118fe5f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989490854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2989490854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.2063971367
Short name T621
Test name
Test status
Simulation time 136135215240 ps
CPU time 1544.37 seconds
Started Mar 28 01:56:57 PM PDT 24
Finished Mar 28 02:22:42 PM PDT 24
Peak memory 388248 kb
Host smart-9d53bf3c-b4d0-46f9-8672-446523544807
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2063971367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2063971367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.3845762603
Short name T379
Test name
Test status
Simulation time 245143771 ps
CPU time 4.71 seconds
Started Mar 28 01:56:46 PM PDT 24
Finished Mar 28 01:56:51 PM PDT 24
Peak memory 216076 kb
Host smart-d9c8e989-95c8-4679-be7c-cef54057714a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845762603 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.3845762603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3095682144
Short name T728
Test name
Test status
Simulation time 1007055737 ps
CPU time 5.31 seconds
Started Mar 28 01:56:44 PM PDT 24
Finished Mar 28 01:56:51 PM PDT 24
Peak memory 216128 kb
Host smart-df5b4f35-5575-4377-8a6c-003257dce0c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095682144 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3095682144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.1735080797
Short name T842
Test name
Test status
Simulation time 18795454497 ps
CPU time 1484.47 seconds
Started Mar 28 01:56:58 PM PDT 24
Finished Mar 28 02:21:42 PM PDT 24
Peak memory 377036 kb
Host smart-d5aad817-144a-45be-a74e-891a918640d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1735080797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.1735080797 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.3125793038
Short name T986
Test name
Test status
Simulation time 37023495479 ps
CPU time 1665.49 seconds
Started Mar 28 01:56:47 PM PDT 24
Finished Mar 28 02:24:34 PM PDT 24
Peak memory 397420 kb
Host smart-dc08e8b5-0f20-48f8-b6a9-6f81dcfb9691
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3125793038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3125793038 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.4115508018
Short name T856
Test name
Test status
Simulation time 60912476921 ps
CPU time 1389.77 seconds
Started Mar 28 01:56:45 PM PDT 24
Finished Mar 28 02:19:56 PM PDT 24
Peak memory 335684 kb
Host smart-ebb9e05a-c70e-47cb-b40e-e3e4d25c3423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4115508018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.4115508018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.970605671
Short name T903
Test name
Test status
Simulation time 230083699688 ps
CPU time 994.45 seconds
Started Mar 28 01:56:45 PM PDT 24
Finished Mar 28 02:13:20 PM PDT 24
Peak memory 293304 kb
Host smart-9de88faf-f764-44fd-b6c7-79770fcd8ed0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=970605671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.970605671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.1734795321
Short name T770
Test name
Test status
Simulation time 301738682046 ps
CPU time 3999.2 seconds
Started Mar 28 01:56:45 PM PDT 24
Finished Mar 28 03:03:25 PM PDT 24
Peak memory 659992 kb
Host smart-75a677ad-8dae-4443-bb58-012653f10668
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1734795321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.1734795321 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.3146150391
Short name T426
Test name
Test status
Simulation time 2726456277792 ps
CPU time 4307.68 seconds
Started Mar 28 01:56:48 PM PDT 24
Finished Mar 28 03:08:36 PM PDT 24
Peak memory 567028 kb
Host smart-d1f63a83-ebf9-4d87-9a29-6ac73e588879
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3146150391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.3146150391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.3034546330
Short name T1018
Test name
Test status
Simulation time 56142021 ps
CPU time 0.84 seconds
Started Mar 28 01:57:27 PM PDT 24
Finished Mar 28 01:57:28 PM PDT 24
Peak memory 205572 kb
Host smart-ba7d6788-c7a3-4826-a7e6-b2d4c94f8c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034546330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3034546330 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.3898963637
Short name T239
Test name
Test status
Simulation time 29862906772 ps
CPU time 76.77 seconds
Started Mar 28 01:57:25 PM PDT 24
Finished Mar 28 01:58:42 PM PDT 24
Peak memory 226120 kb
Host smart-81cf7c7d-0703-4117-b31c-7ff14492818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898963637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3898963637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1502615141
Short name T896
Test name
Test status
Simulation time 26895632688 ps
CPU time 409.03 seconds
Started Mar 28 01:57:08 PM PDT 24
Finished Mar 28 02:03:57 PM PDT 24
Peak memory 229676 kb
Host smart-3cdbacdd-b7ea-4450-bf7b-9d85c8fc530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502615141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1502615141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.2174994072
Short name T552
Test name
Test status
Simulation time 4683399849 ps
CPU time 177.85 seconds
Started Mar 28 01:57:26 PM PDT 24
Finished Mar 28 02:00:24 PM PDT 24
Peak memory 239504 kb
Host smart-a6ee7cbd-e38f-4357-9727-507a4c65c1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174994072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.2174994072 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.1618227502
Short name T574
Test name
Test status
Simulation time 7881638543 ps
CPU time 147.19 seconds
Started Mar 28 01:57:26 PM PDT 24
Finished Mar 28 01:59:53 PM PDT 24
Peak memory 257012 kb
Host smart-07196133-8d28-455b-9744-2eeb5ac75cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618227502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1618227502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.2910583129
Short name T21
Test name
Test status
Simulation time 653171972 ps
CPU time 1.73 seconds
Started Mar 28 01:57:27 PM PDT 24
Finished Mar 28 01:57:29 PM PDT 24
Peak memory 207440 kb
Host smart-f8720ce0-a1dd-473f-9d68-9f27b8279e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910583129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2910583129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.3417648747
Short name T789
Test name
Test status
Simulation time 31217322 ps
CPU time 1.14 seconds
Started Mar 28 01:57:27 PM PDT 24
Finished Mar 28 01:57:29 PM PDT 24
Peak memory 216020 kb
Host smart-67e0b04c-a839-4e0a-88af-fc1765960bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417648747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3417648747 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.531054751
Short name T341
Test name
Test status
Simulation time 56860917861 ps
CPU time 855.83 seconds
Started Mar 28 01:57:08 PM PDT 24
Finished Mar 28 02:11:24 PM PDT 24
Peak memory 300384 kb
Host smart-b09d7141-ae61-49f8-8994-518de1b685ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531054751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_an
d_output.531054751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.2196105617
Short name T775
Test name
Test status
Simulation time 18202077447 ps
CPU time 262.46 seconds
Started Mar 28 01:57:08 PM PDT 24
Finished Mar 28 02:01:31 PM PDT 24
Peak memory 239888 kb
Host smart-65439ac6-f4c9-41f6-a592-f80d610f952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196105617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2196105617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.2393292464
Short name T787
Test name
Test status
Simulation time 572132065 ps
CPU time 29.63 seconds
Started Mar 28 01:56:55 PM PDT 24
Finished Mar 28 01:57:25 PM PDT 24
Peak memory 219408 kb
Host smart-872aea1a-618c-45df-9602-d6c06a24f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393292464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2393292464 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.3100054063
Short name T823
Test name
Test status
Simulation time 29372248554 ps
CPU time 463.67 seconds
Started Mar 28 01:57:25 PM PDT 24
Finished Mar 28 02:05:09 PM PDT 24
Peak memory 266892 kb
Host smart-cc4560e9-6eaa-4160-a46e-8e369b6d03f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3100054063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3100054063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_stress_all_with_rand_reset.1462637925
Short name T46
Test name
Test status
Simulation time 82763446019 ps
CPU time 1238.88 seconds
Started Mar 28 01:57:29 PM PDT 24
Finished Mar 28 02:18:08 PM PDT 24
Peak memory 339196 kb
Host smart-b8bd62f9-6897-4588-885f-a82a40cfd16d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462637925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all_with_rand_reset.1462637925 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.1409211368
Short name T799
Test name
Test status
Simulation time 133127672 ps
CPU time 4.32 seconds
Started Mar 28 01:57:10 PM PDT 24
Finished Mar 28 01:57:15 PM PDT 24
Peak memory 216152 kb
Host smart-d69454c3-a0f3-4736-bb86-76b1d7a38f0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409211368 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.1409211368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.277850942
Short name T596
Test name
Test status
Simulation time 370179432 ps
CPU time 5.48 seconds
Started Mar 28 01:57:10 PM PDT 24
Finished Mar 28 01:57:16 PM PDT 24
Peak memory 216092 kb
Host smart-f507af16-0476-4dac-b089-b1e655c06325
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277850942 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.kmac_test_vectors_kmac_xof.277850942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.276790051
Short name T879
Test name
Test status
Simulation time 261017123597 ps
CPU time 1766.89 seconds
Started Mar 28 01:57:08 PM PDT 24
Finished Mar 28 02:26:35 PM PDT 24
Peak memory 394260 kb
Host smart-3459af4e-3ab7-4474-9613-26f164eff5a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=276790051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.276790051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.3471580781
Short name T490
Test name
Test status
Simulation time 71897243382 ps
CPU time 1668.34 seconds
Started Mar 28 01:57:09 PM PDT 24
Finished Mar 28 02:24:58 PM PDT 24
Peak memory 379460 kb
Host smart-e78805ab-1628-460d-bc41-5ba7171b0eea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3471580781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.3471580781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.1262963780
Short name T637
Test name
Test status
Simulation time 72267159015 ps
CPU time 1468.37 seconds
Started Mar 28 01:57:09 PM PDT 24
Finished Mar 28 02:21:37 PM PDT 24
Peak memory 334936 kb
Host smart-367a71e1-36ae-4e16-9416-ce0a10ed58d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1262963780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.1262963780 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.4179870330
Short name T1028
Test name
Test status
Simulation time 63665343342 ps
CPU time 818.39 seconds
Started Mar 28 01:57:09 PM PDT 24
Finished Mar 28 02:10:49 PM PDT 24
Peak memory 296736 kb
Host smart-715f85f7-2f39-4330-8062-44e9c7a55c91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4179870330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.4179870330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.2293597412
Short name T794
Test name
Test status
Simulation time 355181716269 ps
CPU time 4875.55 seconds
Started Mar 28 01:57:09 PM PDT 24
Finished Mar 28 03:18:26 PM PDT 24
Peak memory 642148 kb
Host smart-22ef7a96-6d56-492d-9933-4edcf9d43ac6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2293597412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.2293597412 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.1215332517
Short name T731
Test name
Test status
Simulation time 172012168146 ps
CPU time 3480.95 seconds
Started Mar 28 01:57:09 PM PDT 24
Finished Mar 28 02:55:10 PM PDT 24
Peak memory 556336 kb
Host smart-1c690e19-9d2a-4fa4-9175-30069eb868da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1215332517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.1215332517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.648665679
Short name T894
Test name
Test status
Simulation time 100723239 ps
CPU time 0.83 seconds
Started Mar 28 01:58:07 PM PDT 24
Finished Mar 28 01:58:09 PM PDT 24
Peak memory 205596 kb
Host smart-8b61552a-0b67-45f6-b786-706774007cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648665679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.648665679 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.2245027224
Short name T449
Test name
Test status
Simulation time 5500599007 ps
CPU time 194.08 seconds
Started Mar 28 01:57:49 PM PDT 24
Finished Mar 28 02:01:03 PM PDT 24
Peak memory 241228 kb
Host smart-e356d222-9d8d-46e5-aebc-046b54a0ed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245027224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2245027224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.815279357
Short name T745
Test name
Test status
Simulation time 5523879892 ps
CPU time 460.68 seconds
Started Mar 28 01:57:45 PM PDT 24
Finished Mar 28 02:05:26 PM PDT 24
Peak memory 229736 kb
Host smart-fe5464e0-1860-4dbb-86d5-91f3075170e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815279357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.815279357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.725187995
Short name T28
Test name
Test status
Simulation time 22398010264 ps
CPU time 188.21 seconds
Started Mar 28 01:57:49 PM PDT 24
Finished Mar 28 02:00:57 PM PDT 24
Peak memory 240580 kb
Host smart-2cf169ae-1d02-45ef-af7f-b572ada10531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725187995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.725187995 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.3370808807
Short name T284
Test name
Test status
Simulation time 1979835385 ps
CPU time 145.24 seconds
Started Mar 28 01:57:47 PM PDT 24
Finished Mar 28 02:00:12 PM PDT 24
Peak memory 240696 kb
Host smart-72c0be49-d80e-4ac3-9977-ea2090116761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370808807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3370808807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.2816610325
Short name T54
Test name
Test status
Simulation time 748328426 ps
CPU time 4.31 seconds
Started Mar 28 01:57:47 PM PDT 24
Finished Mar 28 01:57:52 PM PDT 24
Peak memory 207576 kb
Host smart-5ee288e7-1300-4be8-9e7d-e7949d125a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816610325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.2816610325 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.970827513
Short name T217
Test name
Test status
Simulation time 128314671 ps
CPU time 1.32 seconds
Started Mar 28 01:58:06 PM PDT 24
Finished Mar 28 01:58:08 PM PDT 24
Peak memory 218160 kb
Host smart-7489bf3c-d6a4-4474-9e81-2f61fabef3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970827513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.970827513 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1125671362
Short name T921
Test name
Test status
Simulation time 13962523009 ps
CPU time 501.12 seconds
Started Mar 28 01:57:27 PM PDT 24
Finished Mar 28 02:05:48 PM PDT 24
Peak memory 265172 kb
Host smart-a25a56a6-a8cd-49ce-af1a-28a712c09ce7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125671362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1125671362 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.3522949039
Short name T213
Test name
Test status
Simulation time 18472436572 ps
CPU time 250.23 seconds
Started Mar 28 01:57:24 PM PDT 24
Finished Mar 28 02:01:35 PM PDT 24
Peak memory 241560 kb
Host smart-5767bf91-8d55-4524-b213-9c565ff26699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522949039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3522949039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.3605648751
Short name T598
Test name
Test status
Simulation time 18241129838 ps
CPU time 68.86 seconds
Started Mar 28 01:57:25 PM PDT 24
Finished Mar 28 01:58:34 PM PDT 24
Peak memory 219792 kb
Host smart-c1e54743-de73-4487-8d32-47a0561d0b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605648751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3605648751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.2711287289
Short name T76
Test name
Test status
Simulation time 63270415144 ps
CPU time 1461.18 seconds
Started Mar 28 01:58:07 PM PDT 24
Finished Mar 28 02:22:29 PM PDT 24
Peak memory 404936 kb
Host smart-9890ab92-72c2-4368-98ed-edc803933d63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2711287289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2711287289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.1658671683
Short name T393
Test name
Test status
Simulation time 65930933 ps
CPU time 4.17 seconds
Started Mar 28 01:57:46 PM PDT 24
Finished Mar 28 01:57:51 PM PDT 24
Peak memory 216140 kb
Host smart-f03acd4a-6aba-4f7f-813b-e1bb2b78dd49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658671683 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.1658671683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.1199986280
Short name T482
Test name
Test status
Simulation time 269542848 ps
CPU time 4.22 seconds
Started Mar 28 01:57:47 PM PDT 24
Finished Mar 28 01:57:51 PM PDT 24
Peak memory 216104 kb
Host smart-343683ec-8730-4ca3-82ae-04eb7de929ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199986280 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.1199986280 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.2955217917
Short name T873
Test name
Test status
Simulation time 97105515671 ps
CPU time 2031.43 seconds
Started Mar 28 01:57:49 PM PDT 24
Finished Mar 28 02:31:40 PM PDT 24
Peak memory 391884 kb
Host smart-10a2c89f-67a2-4a46-92c1-ad32a34b5922
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2955217917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2955217917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.3015624872
Short name T211
Test name
Test status
Simulation time 59506923835 ps
CPU time 1785.45 seconds
Started Mar 28 01:57:46 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 364668 kb
Host smart-6dc4fd95-c9d3-4537-96ee-78bb7a83fd98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3015624872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3015624872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.2134128641
Short name T720
Test name
Test status
Simulation time 14235153239 ps
CPU time 1155.21 seconds
Started Mar 28 01:57:47 PM PDT 24
Finished Mar 28 02:17:02 PM PDT 24
Peak memory 335796 kb
Host smart-d26b13d3-107f-4050-a3c1-9defcebb4a3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2134128641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.2134128641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.1939521329
Short name T644
Test name
Test status
Simulation time 19696042630 ps
CPU time 860.05 seconds
Started Mar 28 01:57:46 PM PDT 24
Finished Mar 28 02:12:06 PM PDT 24
Peak memory 294468 kb
Host smart-eb2ca512-bde5-4c86-874f-9482341f7b38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1939521329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.1939521329 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.798080567
Short name T270
Test name
Test status
Simulation time 52584449574 ps
CPU time 4344.19 seconds
Started Mar 28 01:57:50 PM PDT 24
Finished Mar 28 03:10:15 PM PDT 24
Peak memory 643316 kb
Host smart-1d8117a6-b428-4ad8-951f-ce4bd5240007
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=798080567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.798080567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.2705738650
Short name T227
Test name
Test status
Simulation time 877421043291 ps
CPU time 4465.17 seconds
Started Mar 28 01:57:48 PM PDT 24
Finished Mar 28 03:12:13 PM PDT 24
Peak memory 572440 kb
Host smart-a2657a81-ff0d-4c37-8823-a7ed5e4d4091
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2705738650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.2705738650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.120017407
Short name T793
Test name
Test status
Simulation time 42867597 ps
CPU time 0.73 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:50:26 PM PDT 24
Peak memory 205560 kb
Host smart-01fa2c68-2272-4c32-9822-a4367e7a816b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120017407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.120017407 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.2604914952
Short name T1030
Test name
Test status
Simulation time 3499770704 ps
CPU time 83.51 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:51:49 PM PDT 24
Peak memory 228160 kb
Host smart-64faefa6-4f80-48da-bb67-607225c9cba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604914952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2604914952 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.3472714818
Short name T443
Test name
Test status
Simulation time 7511795020 ps
CPU time 173.35 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 01:53:22 PM PDT 24
Peak memory 239036 kb
Host smart-749d4f8c-75fc-41a9-aca8-170132598e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472714818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3472714818 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.2883828206
Short name T389
Test name
Test status
Simulation time 36071968815 ps
CPU time 525.88 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 01:59:10 PM PDT 24
Peak memory 230756 kb
Host smart-11cfe7fd-0828-4774-b8e1-34b6b392535a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883828206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2883828206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.4135813032
Short name T318
Test name
Test status
Simulation time 2196853176 ps
CPU time 28.17 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 01:50:53 PM PDT 24
Peak memory 224208 kb
Host smart-93d61ce6-f8e8-47c9-8122-2ec177d43194
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4135813032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.4135813032 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.2335936823
Short name T1001
Test name
Test status
Simulation time 6827754237 ps
CPU time 35.4 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:51:01 PM PDT 24
Peak memory 221412 kb
Host smart-5682781e-720d-41b1-8e5e-3ccba665ae00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2335936823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2335936823 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.1600897702
Short name T719
Test name
Test status
Simulation time 4440419936 ps
CPU time 10.83 seconds
Started Mar 28 01:50:28 PM PDT 24
Finished Mar 28 01:50:40 PM PDT 24
Peak memory 216176 kb
Host smart-f1bc0387-69d1-4e1d-8266-bfa0a32e5025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600897702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1600897702 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.2702528872
Short name T1032
Test name
Test status
Simulation time 3391094380 ps
CPU time 176.22 seconds
Started Mar 28 01:50:26 PM PDT 24
Finished Mar 28 01:53:23 PM PDT 24
Peak memory 241608 kb
Host smart-6edfd7aa-33f5-4cf7-8726-ffa6bfae0f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702528872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2702528872 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.1234421961
Short name T29
Test name
Test status
Simulation time 5783573993 ps
CPU time 35.98 seconds
Started Mar 28 01:50:28 PM PDT 24
Finished Mar 28 01:51:05 PM PDT 24
Peak memory 232496 kb
Host smart-7118aea7-628a-419d-8183-39af0859288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234421961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1234421961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.970042208
Short name T877
Test name
Test status
Simulation time 1031556774 ps
CPU time 2.42 seconds
Started Mar 28 01:50:28 PM PDT 24
Finished Mar 28 01:50:32 PM PDT 24
Peak memory 207440 kb
Host smart-146e9d2f-e106-4d9d-bb09-6165cb97bdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970042208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.970042208 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.3752702753
Short name T1031
Test name
Test status
Simulation time 142489790 ps
CPU time 1.26 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 01:50:26 PM PDT 24
Peak memory 217044 kb
Host smart-64485498-8a90-46ff-ad0e-dc9b7fad69e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752702753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3752702753 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.1946609944
Short name T72
Test name
Test status
Simulation time 49787089572 ps
CPU time 2246.81 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 02:27:55 PM PDT 24
Peak memory 465692 kb
Host smart-6220055d-eca5-42e3-bf58-453364319407
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946609944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.1946609944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.4237769201
Short name T886
Test name
Test status
Simulation time 554368759 ps
CPU time 16.76 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:50:43 PM PDT 24
Peak memory 224540 kb
Host smart-dfc5d030-1b9f-449d-8a6f-bd04107850ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237769201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.4237769201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1831946412
Short name T11
Test name
Test status
Simulation time 2911448864 ps
CPU time 27.57 seconds
Started Mar 28 01:50:28 PM PDT 24
Finished Mar 28 01:50:57 PM PDT 24
Peak memory 250340 kb
Host smart-aa3a6892-41fa-492c-809b-790912a65981
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831946412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1831946412 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.1225233653
Short name T1010
Test name
Test status
Simulation time 5548264831 ps
CPU time 208.55 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 01:53:53 PM PDT 24
Peak memory 239336 kb
Host smart-6b205c9c-b12b-4a4a-9106-b3c16192a642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225233653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1225233653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.399940251
Short name T312
Test name
Test status
Simulation time 453819604 ps
CPU time 21.92 seconds
Started Mar 28 01:50:29 PM PDT 24
Finished Mar 28 01:50:52 PM PDT 24
Peak memory 224288 kb
Host smart-57c6b226-34b0-4e37-ad01-e4faa4ff43bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399940251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.399940251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.40050844
Short name T75
Test name
Test status
Simulation time 161146227677 ps
CPU time 881.76 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 02:05:06 PM PDT 24
Peak memory 316188 kb
Host smart-5d1877a4-4f23-4c88-bb76-5613787a0954
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=40050844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.40050844 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.1149536875
Short name T391
Test name
Test status
Simulation time 177632293 ps
CPU time 4.64 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:50:29 PM PDT 24
Peak memory 216144 kb
Host smart-d49e5a69-5f46-4293-8b2c-b3e6c77b0e99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149536875 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.1149536875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.2536238155
Short name T489
Test name
Test status
Simulation time 127365104 ps
CPU time 3.98 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 01:50:29 PM PDT 24
Peak memory 216048 kb
Host smart-a267b26e-844e-4bc3-a81e-f9405de066f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536238155 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2536238155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2942948444
Short name T501
Test name
Test status
Simulation time 130526797346 ps
CPU time 1856.42 seconds
Started Mar 28 01:50:29 PM PDT 24
Finished Mar 28 02:21:27 PM PDT 24
Peak memory 394240 kb
Host smart-86c394c9-85f3-4f88-bef3-03fe0086f174
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2942948444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2942948444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.771214101
Short name T897
Test name
Test status
Simulation time 147456750835 ps
CPU time 1845.88 seconds
Started Mar 28 01:50:26 PM PDT 24
Finished Mar 28 02:21:12 PM PDT 24
Peak memory 379136 kb
Host smart-57d25237-d296-4bd9-b618-228ea3df4b16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=771214101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.771214101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.2649704114
Short name T937
Test name
Test status
Simulation time 64694735052 ps
CPU time 1408.89 seconds
Started Mar 28 01:50:23 PM PDT 24
Finished Mar 28 02:13:52 PM PDT 24
Peak memory 340592 kb
Host smart-99c726cf-81e3-483b-889b-287fde8116e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2649704114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2649704114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.26173896
Short name T263
Test name
Test status
Simulation time 165382994055 ps
CPU time 939.07 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 02:06:08 PM PDT 24
Peak memory 290956 kb
Host smart-0e877db4-1d19-4b8e-ba9f-852b4d232419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=26173896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.26173896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.1121813550
Short name T79
Test name
Test status
Simulation time 356646970880 ps
CPU time 4756.46 seconds
Started Mar 28 01:50:25 PM PDT 24
Finished Mar 28 03:09:42 PM PDT 24
Peak memory 646132 kb
Host smart-9cdee6b0-e734-4fc3-bba7-636356d36ff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1121813550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1121813550 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.2407754789
Short name T582
Test name
Test status
Simulation time 566498199482 ps
CPU time 4443.42 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 03:04:28 PM PDT 24
Peak memory 572656 kb
Host smart-2e2122ce-4f2e-4674-9995-f7f44da9c13a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2407754789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2407754789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2460710912
Short name T537
Test name
Test status
Simulation time 20950166 ps
CPU time 0.84 seconds
Started Mar 28 01:58:48 PM PDT 24
Finished Mar 28 01:58:50 PM PDT 24
Peak memory 205444 kb
Host smart-c4267b5b-e88e-400c-847b-6f0428027efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460710912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2460710912 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.2023232332
Short name T950
Test name
Test status
Simulation time 3567524649 ps
CPU time 90.86 seconds
Started Mar 28 01:58:28 PM PDT 24
Finished Mar 28 01:59:59 PM PDT 24
Peak memory 229164 kb
Host smart-659b0663-db46-4e76-a80e-6c276b9e078f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023232332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2023232332 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.474143595
Short name T1080
Test name
Test status
Simulation time 3269293721 ps
CPU time 50.16 seconds
Started Mar 28 01:58:06 PM PDT 24
Finished Mar 28 01:58:57 PM PDT 24
Peak memory 219168 kb
Host smart-51f790df-5612-4422-a989-c200711fb4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474143595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.474143595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.1222530140
Short name T99
Test name
Test status
Simulation time 6678795113 ps
CPU time 260.09 seconds
Started Mar 28 01:58:27 PM PDT 24
Finished Mar 28 02:02:48 PM PDT 24
Peak memory 244908 kb
Host smart-bcdf2e32-50ae-4c0d-875b-b562ccfdbebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222530140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1222530140 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.1035455455
Short name T683
Test name
Test status
Simulation time 53129780889 ps
CPU time 363.8 seconds
Started Mar 28 01:58:27 PM PDT 24
Finished Mar 28 02:04:32 PM PDT 24
Peak memory 257108 kb
Host smart-12e85450-7333-4e85-9dd1-a24f565d53df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035455455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1035455455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.1774061398
Short name T55
Test name
Test status
Simulation time 214833239 ps
CPU time 1.67 seconds
Started Mar 28 01:58:27 PM PDT 24
Finished Mar 28 01:58:29 PM PDT 24
Peak memory 207232 kb
Host smart-378a109c-988a-456b-b17c-f857f16e3e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774061398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1774061398 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.385768220
Short name T798
Test name
Test status
Simulation time 49530182 ps
CPU time 1.47 seconds
Started Mar 28 01:58:27 PM PDT 24
Finished Mar 28 01:58:28 PM PDT 24
Peak memory 216048 kb
Host smart-047f7cdd-a941-4862-8747-45b3e3e689c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385768220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.385768220 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.767787420
Short name T857
Test name
Test status
Simulation time 426302466128 ps
CPU time 639.61 seconds
Started Mar 28 01:58:07 PM PDT 24
Finished Mar 28 02:08:47 PM PDT 24
Peak memory 281416 kb
Host smart-5dde9e7d-10f5-4e0d-9ba8-f599bf030555
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767787420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_an
d_output.767787420 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.1172670541
Short name T267
Test name
Test status
Simulation time 31230278783 ps
CPU time 197.63 seconds
Started Mar 28 01:58:10 PM PDT 24
Finished Mar 28 02:01:28 PM PDT 24
Peak memory 237616 kb
Host smart-d93c9da5-cd48-45db-abc4-bb8190a9ec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172670541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1172670541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2830787355
Short name T992
Test name
Test status
Simulation time 3757868710 ps
CPU time 44.59 seconds
Started Mar 28 01:58:07 PM PDT 24
Finished Mar 28 01:58:53 PM PDT 24
Peak memory 217228 kb
Host smart-89a13c28-3dab-45c0-8c0b-c9ebbae35aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830787355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2830787355 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.1536505143
Short name T444
Test name
Test status
Simulation time 18434152807 ps
CPU time 170.47 seconds
Started Mar 28 01:58:56 PM PDT 24
Finished Mar 28 02:01:46 PM PDT 24
Peak memory 245188 kb
Host smart-a9e802b1-b761-4f57-a112-a4d922fbed79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1536505143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1536505143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.143974704
Short name T561
Test name
Test status
Simulation time 1341907664 ps
CPU time 4.49 seconds
Started Mar 28 01:58:26 PM PDT 24
Finished Mar 28 01:58:31 PM PDT 24
Peak memory 216124 kb
Host smart-52665bc2-6663-44d6-a2cf-a84957c99c90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143974704 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.kmac_test_vectors_kmac.143974704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.716466747
Short name T1071
Test name
Test status
Simulation time 742741993 ps
CPU time 5.05 seconds
Started Mar 28 01:58:27 PM PDT 24
Finished Mar 28 01:58:33 PM PDT 24
Peak memory 216116 kb
Host smart-eefb65ed-097b-4510-a3d8-bb1386e4aba8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716466747 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.kmac_test_vectors_kmac_xof.716466747 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.955664721
Short name T837
Test name
Test status
Simulation time 219992355961 ps
CPU time 1989.98 seconds
Started Mar 28 01:58:27 PM PDT 24
Finished Mar 28 02:31:37 PM PDT 24
Peak memory 391264 kb
Host smart-e87643da-f22f-4b79-9882-64dbfe1b921a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=955664721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.955664721 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.669835968
Short name T339
Test name
Test status
Simulation time 135747553035 ps
CPU time 1829.08 seconds
Started Mar 28 01:58:28 PM PDT 24
Finished Mar 28 02:28:58 PM PDT 24
Peak memory 390100 kb
Host smart-983b8be5-0bfa-40bf-b0fc-632e1972ccdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=669835968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.669835968 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.2728793255
Short name T258
Test name
Test status
Simulation time 59116116263 ps
CPU time 1252.72 seconds
Started Mar 28 01:58:26 PM PDT 24
Finished Mar 28 02:19:19 PM PDT 24
Peak memory 334716 kb
Host smart-38abbe20-0430-4f19-ba98-47a1c31339c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2728793255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.2728793255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.484694430
Short name T301
Test name
Test status
Simulation time 19634355922 ps
CPU time 784.41 seconds
Started Mar 28 01:58:32 PM PDT 24
Finished Mar 28 02:11:37 PM PDT 24
Peak memory 293368 kb
Host smart-979ab107-9208-4c9d-8c63-9459ac7b3506
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=484694430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.484694430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.1407950034
Short name T190
Test name
Test status
Simulation time 50841687983 ps
CPU time 4163.03 seconds
Started Mar 28 01:58:27 PM PDT 24
Finished Mar 28 03:07:51 PM PDT 24
Peak memory 650220 kb
Host smart-aefba45c-2564-4fb8-9fe7-bb4376c65ac9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1407950034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.1407950034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.1965475656
Short name T912
Test name
Test status
Simulation time 42917418887 ps
CPU time 3304.06 seconds
Started Mar 28 01:58:27 PM PDT 24
Finished Mar 28 02:53:31 PM PDT 24
Peak memory 554436 kb
Host smart-e2a3716f-a942-4141-8d40-a9aa80579664
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1965475656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.1965475656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.1651597176
Short name T1003
Test name
Test status
Simulation time 27159860 ps
CPU time 0.8 seconds
Started Mar 28 01:59:05 PM PDT 24
Finished Mar 28 01:59:06 PM PDT 24
Peak memory 205444 kb
Host smart-eb4f8c76-6ee5-42f2-9dd0-602f7143759b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651597176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1651597176 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3647464213
Short name T668
Test name
Test status
Simulation time 10449469484 ps
CPU time 249.51 seconds
Started Mar 28 01:59:03 PM PDT 24
Finished Mar 28 02:03:13 PM PDT 24
Peak memory 240560 kb
Host smart-3f012b92-9016-4026-934e-80472c90077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647464213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3647464213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.1765549450
Short name T1037
Test name
Test status
Simulation time 22930399698 ps
CPU time 673.17 seconds
Started Mar 28 01:58:45 PM PDT 24
Finished Mar 28 02:09:59 PM PDT 24
Peak memory 230972 kb
Host smart-ba18cf91-c1d3-4f5c-a806-da7c0a2d1a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765549450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1765549450 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.1615716535
Short name T987
Test name
Test status
Simulation time 3809212475 ps
CPU time 98.81 seconds
Started Mar 28 01:59:04 PM PDT 24
Finished Mar 28 02:00:43 PM PDT 24
Peak memory 240744 kb
Host smart-a7d32044-3522-4a5c-a3c9-68c13f769b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615716535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1615716535 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.390554693
Short name T698
Test name
Test status
Simulation time 29066656565 ps
CPU time 273.69 seconds
Started Mar 28 01:59:05 PM PDT 24
Finished Mar 28 02:03:39 PM PDT 24
Peak memory 257036 kb
Host smart-20f0f574-44c4-4bbc-8f40-35dc94ffe127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390554693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.390554693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.3214725395
Short name T1023
Test name
Test status
Simulation time 3369526165 ps
CPU time 5.14 seconds
Started Mar 28 01:59:04 PM PDT 24
Finished Mar 28 01:59:09 PM PDT 24
Peak memory 207752 kb
Host smart-81da152b-8003-4abe-8865-2e62c8f31e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214725395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3214725395 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.3242813284
Short name T899
Test name
Test status
Simulation time 39426849 ps
CPU time 1.44 seconds
Started Mar 28 01:59:04 PM PDT 24
Finished Mar 28 01:59:05 PM PDT 24
Peak memory 218120 kb
Host smart-f348e6ea-b7ca-486f-acd6-3c126f74e2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242813284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.3242813284 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.3729192019
Short name T730
Test name
Test status
Simulation time 87381021058 ps
CPU time 2637.97 seconds
Started Mar 28 01:58:45 PM PDT 24
Finished Mar 28 02:42:43 PM PDT 24
Peak memory 458144 kb
Host smart-74037081-2be8-43a9-9d6b-6dc0c82f3205
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729192019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.3729192019 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.2649537387
Short name T1077
Test name
Test status
Simulation time 480329603 ps
CPU time 9.36 seconds
Started Mar 28 01:58:48 PM PDT 24
Finished Mar 28 01:58:57 PM PDT 24
Peak memory 224200 kb
Host smart-69987639-6aba-46d6-9f46-555a5e656391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649537387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2649537387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.1184246205
Short name T733
Test name
Test status
Simulation time 4452835875 ps
CPU time 24.91 seconds
Started Mar 28 01:58:46 PM PDT 24
Finished Mar 28 01:59:12 PM PDT 24
Peak memory 224268 kb
Host smart-16f2e4e4-9ca1-4c74-9a9b-1418cae608aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184246205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1184246205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.3061271821
Short name T643
Test name
Test status
Simulation time 17702952457 ps
CPU time 1239.13 seconds
Started Mar 28 01:59:11 PM PDT 24
Finished Mar 28 02:19:50 PM PDT 24
Peak memory 335552 kb
Host smart-a494b93f-2d83-4ee2-81ce-22bee2b61fc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3061271821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3061271821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.757710597
Short name T749
Test name
Test status
Simulation time 243495648 ps
CPU time 5.09 seconds
Started Mar 28 01:59:03 PM PDT 24
Finished Mar 28 01:59:08 PM PDT 24
Peak memory 216156 kb
Host smart-fb7bad13-83f2-456a-bbd2-d30795201992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757710597 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.kmac_test_vectors_kmac.757710597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.4247715076
Short name T813
Test name
Test status
Simulation time 566163148 ps
CPU time 4.3 seconds
Started Mar 28 01:59:04 PM PDT 24
Finished Mar 28 01:59:09 PM PDT 24
Peak memory 216132 kb
Host smart-06487160-45d0-4989-9c9e-cc0742cdcc52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247715076 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.4247715076 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.3715504593
Short name T333
Test name
Test status
Simulation time 197407176558 ps
CPU time 1927.16 seconds
Started Mar 28 01:58:48 PM PDT 24
Finished Mar 28 02:30:56 PM PDT 24
Peak memory 375796 kb
Host smart-282e415d-a797-4e13-baaf-7a0cfbdf30fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3715504593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.3715504593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.2283967234
Short name T62
Test name
Test status
Simulation time 61694435116 ps
CPU time 1799.16 seconds
Started Mar 28 01:58:45 PM PDT 24
Finished Mar 28 02:28:45 PM PDT 24
Peak memory 377648 kb
Host smart-c4c20061-91f4-462b-b234-bcdc32290e12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2283967234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.2283967234 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.3250029598
Short name T261
Test name
Test status
Simulation time 45765956111 ps
CPU time 1269.83 seconds
Started Mar 28 01:58:46 PM PDT 24
Finished Mar 28 02:19:57 PM PDT 24
Peak memory 328648 kb
Host smart-451e4ea2-787c-4735-a888-425838ffc1df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3250029598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.3250029598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.2187135640
Short name T562
Test name
Test status
Simulation time 197216861550 ps
CPU time 1026.44 seconds
Started Mar 28 01:58:45 PM PDT 24
Finished Mar 28 02:15:52 PM PDT 24
Peak memory 289432 kb
Host smart-8892964f-3b02-44be-b842-3377ad4400b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2187135640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.2187135640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.794926654
Short name T1039
Test name
Test status
Simulation time 1025992672922 ps
CPU time 5383.86 seconds
Started Mar 28 01:58:55 PM PDT 24
Finished Mar 28 03:28:40 PM PDT 24
Peak memory 650044 kb
Host smart-b3af6c18-04fb-480e-b95f-1f6fe0967468
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=794926654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.794926654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.89360892
Short name T354
Test name
Test status
Simulation time 43680009799 ps
CPU time 3250.82 seconds
Started Mar 28 01:58:47 PM PDT 24
Finished Mar 28 02:52:59 PM PDT 24
Peak memory 560912 kb
Host smart-05c1e1c3-5ee8-4481-a731-c73e84306605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=89360892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.89360892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.3588160789
Short name T415
Test name
Test status
Simulation time 16030955 ps
CPU time 0.77 seconds
Started Mar 28 01:59:47 PM PDT 24
Finished Mar 28 01:59:48 PM PDT 24
Peak memory 205576 kb
Host smart-85f256a4-8d5f-4df8-8eda-0bf727133010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588160789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3588160789 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.2726129768
Short name T796
Test name
Test status
Simulation time 10427405576 ps
CPU time 172.57 seconds
Started Mar 28 01:59:47 PM PDT 24
Finished Mar 28 02:02:40 PM PDT 24
Peak memory 237088 kb
Host smart-64aecd93-f948-42b1-a4dc-c165d2503db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726129768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2726129768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.1771745108
Short name T159
Test name
Test status
Simulation time 26059256439 ps
CPU time 525.31 seconds
Started Mar 28 01:59:23 PM PDT 24
Finished Mar 28 02:08:09 PM PDT 24
Peak memory 231404 kb
Host smart-d767dd51-1f4e-4f9f-957e-26dd48bdf7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771745108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1771745108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.2531436469
Short name T917
Test name
Test status
Simulation time 17549896902 ps
CPU time 138.41 seconds
Started Mar 28 01:59:46 PM PDT 24
Finished Mar 28 02:02:05 PM PDT 24
Peak memory 233944 kb
Host smart-e228541c-273d-4b24-a791-70de96976518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531436469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2531436469 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.1578836390
Short name T834
Test name
Test status
Simulation time 1968718603 ps
CPU time 144.94 seconds
Started Mar 28 01:59:49 PM PDT 24
Finished Mar 28 02:02:14 PM PDT 24
Peak memory 236744 kb
Host smart-e5153558-c84c-4905-9b2e-7e1c30e727f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578836390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1578836390 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.1484367326
Short name T313
Test name
Test status
Simulation time 803996981 ps
CPU time 1.65 seconds
Started Mar 28 01:59:48 PM PDT 24
Finished Mar 28 01:59:50 PM PDT 24
Peak memory 207444 kb
Host smart-2a4e2735-937f-4392-9f54-cc183002e920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484367326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1484367326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.2257064745
Short name T87
Test name
Test status
Simulation time 85316218 ps
CPU time 1.36 seconds
Started Mar 28 01:59:48 PM PDT 24
Finished Mar 28 01:59:50 PM PDT 24
Peak memory 216004 kb
Host smart-ed8dfd3b-4c38-4e15-9022-46991d877eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257064745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2257064745 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.1412661745
Short name T689
Test name
Test status
Simulation time 167254135715 ps
CPU time 859.74 seconds
Started Mar 28 01:59:23 PM PDT 24
Finished Mar 28 02:13:43 PM PDT 24
Peak memory 298308 kb
Host smart-68165f38-4392-4943-b43a-c41de2af7264
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412661745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.1412661745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.3995671316
Short name T933
Test name
Test status
Simulation time 10358135768 ps
CPU time 172.55 seconds
Started Mar 28 01:59:23 PM PDT 24
Finished Mar 28 02:02:15 PM PDT 24
Peak memory 231680 kb
Host smart-94193847-e2bf-4899-8946-333558c9b736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995671316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3995671316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.635348426
Short name T761
Test name
Test status
Simulation time 8515948602 ps
CPU time 51.49 seconds
Started Mar 28 01:59:23 PM PDT 24
Finished Mar 28 02:00:14 PM PDT 24
Peak memory 219556 kb
Host smart-f8a2619a-1561-403f-a560-f8fcd48068d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635348426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.635348426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.4258663583
Short name T25
Test name
Test status
Simulation time 6827671425 ps
CPU time 645.08 seconds
Started Mar 28 01:59:50 PM PDT 24
Finished Mar 28 02:10:35 PM PDT 24
Peak memory 301220 kb
Host smart-90697646-ee23-4244-8549-60f80a65517f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4258663583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.4258663583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.48667256
Short name T623
Test name
Test status
Simulation time 367733012 ps
CPU time 4.11 seconds
Started Mar 28 01:59:50 PM PDT 24
Finished Mar 28 01:59:54 PM PDT 24
Peak memory 216100 kb
Host smart-6c22bcfb-5251-460a-8039-b7d66ae5fdcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48667256 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.kmac_test_vectors_kmac.48667256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.2683834217
Short name T771
Test name
Test status
Simulation time 1005983767 ps
CPU time 5.81 seconds
Started Mar 28 01:59:48 PM PDT 24
Finished Mar 28 01:59:54 PM PDT 24
Peak memory 216124 kb
Host smart-23427061-7503-4a97-8420-460156f68445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683834217 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.2683834217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.3071243393
Short name T818
Test name
Test status
Simulation time 237477888060 ps
CPU time 2100.56 seconds
Started Mar 28 01:59:24 PM PDT 24
Finished Mar 28 02:34:25 PM PDT 24
Peak memory 376940 kb
Host smart-690ace23-8b08-4321-a3ad-3d6725ac1f9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3071243393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3071243393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.278347581
Short name T348
Test name
Test status
Simulation time 18010124575 ps
CPU time 1523.46 seconds
Started Mar 28 01:59:26 PM PDT 24
Finished Mar 28 02:24:50 PM PDT 24
Peak memory 387216 kb
Host smart-c9e481bd-01e4-42e2-a28c-80aa2a5abff1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=278347581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.278347581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.2103039734
Short name T42
Test name
Test status
Simulation time 43733492958 ps
CPU time 1077.16 seconds
Started Mar 28 01:59:26 PM PDT 24
Finished Mar 28 02:17:24 PM PDT 24
Peak memory 332944 kb
Host smart-78564ad1-adf4-4ab5-a550-013c0db8cf08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2103039734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.2103039734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.1027602681
Short name T440
Test name
Test status
Simulation time 33819311869 ps
CPU time 839.69 seconds
Started Mar 28 01:59:28 PM PDT 24
Finished Mar 28 02:13:28 PM PDT 24
Peak memory 298616 kb
Host smart-9b104df0-0e39-4412-bad0-ca18b767e9c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1027602681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.1027602681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.3161325485
Short name T327
Test name
Test status
Simulation time 209278278568 ps
CPU time 3883.44 seconds
Started Mar 28 01:59:26 PM PDT 24
Finished Mar 28 03:04:10 PM PDT 24
Peak memory 637168 kb
Host smart-726b3c8b-f15b-438e-a398-00cff1905da7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3161325485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3161325485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.1798548354
Short name T772
Test name
Test status
Simulation time 917808384985 ps
CPU time 4285.47 seconds
Started Mar 28 01:59:48 PM PDT 24
Finished Mar 28 03:11:14 PM PDT 24
Peak memory 574132 kb
Host smart-3596d2d8-cddc-4824-83d5-c461bf052456
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1798548354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1798548354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.316213857
Short name T664
Test name
Test status
Simulation time 21788308 ps
CPU time 0.77 seconds
Started Mar 28 02:00:24 PM PDT 24
Finished Mar 28 02:00:25 PM PDT 24
Peak memory 205548 kb
Host smart-dc3d8cd6-df99-48fb-974d-81ceb6c769e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316213857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.316213857 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.460074082
Short name T665
Test name
Test status
Simulation time 5211545381 ps
CPU time 137.82 seconds
Started Mar 28 02:00:09 PM PDT 24
Finished Mar 28 02:02:26 PM PDT 24
Peak memory 233124 kb
Host smart-d0bc8294-6136-418f-b3e7-0f21db6a65da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460074082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.460074082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.1282504131
Short name T1040
Test name
Test status
Simulation time 4530536625 ps
CPU time 378.66 seconds
Started Mar 28 02:00:07 PM PDT 24
Finished Mar 28 02:06:26 PM PDT 24
Peak memory 228740 kb
Host smart-a50900ff-c945-42f8-8515-a5d34e9938be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282504131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.1282504131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.3345711951
Short name T1046
Test name
Test status
Simulation time 16648383854 ps
CPU time 269.37 seconds
Started Mar 28 02:00:07 PM PDT 24
Finished Mar 28 02:04:37 PM PDT 24
Peak memory 246056 kb
Host smart-c401bca1-49b8-4ab7-a2f8-a94e3e0b9460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345711951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3345711951 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.3085283201
Short name T706
Test name
Test status
Simulation time 46596505461 ps
CPU time 408.78 seconds
Started Mar 28 02:00:25 PM PDT 24
Finished Mar 28 02:07:13 PM PDT 24
Peak memory 249672 kb
Host smart-6555fd8e-2035-40aa-ba86-6a8e418f2fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085283201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3085283201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.3669097554
Short name T473
Test name
Test status
Simulation time 895967823 ps
CPU time 4.14 seconds
Started Mar 28 02:00:23 PM PDT 24
Finished Mar 28 02:00:28 PM PDT 24
Peak memory 215940 kb
Host smart-b5c8c5da-2584-4b08-9e15-386a5bcfaa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669097554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3669097554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1712840084
Short name T617
Test name
Test status
Simulation time 711034925 ps
CPU time 1.27 seconds
Started Mar 28 02:00:23 PM PDT 24
Finished Mar 28 02:00:24 PM PDT 24
Peak memory 216040 kb
Host smart-e9e69533-9ab2-4313-9a2a-e80fc4bb6ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712840084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1712840084 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.1199702587
Short name T247
Test name
Test status
Simulation time 54092692029 ps
CPU time 2336.29 seconds
Started Mar 28 02:00:07 PM PDT 24
Finished Mar 28 02:39:04 PM PDT 24
Peak memory 464472 kb
Host smart-2891553c-c20a-4c49-8564-65dc70cafb6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199702587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.1199702587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.251277299
Short name T1048
Test name
Test status
Simulation time 8329452965 ps
CPU time 180.37 seconds
Started Mar 28 02:00:05 PM PDT 24
Finished Mar 28 02:03:06 PM PDT 24
Peak memory 235220 kb
Host smart-b49e6084-2076-46af-9a9c-8f3df02c7bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251277299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.251277299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.2946630261
Short name T291
Test name
Test status
Simulation time 396064853 ps
CPU time 9.29 seconds
Started Mar 28 02:00:06 PM PDT 24
Finished Mar 28 02:00:16 PM PDT 24
Peak memory 219164 kb
Host smart-9b7ccd7e-b372-4eab-b617-4bb0b7a7e1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946630261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2946630261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3379430430
Short name T1082
Test name
Test status
Simulation time 153812592099 ps
CPU time 1736.9 seconds
Started Mar 28 02:00:24 PM PDT 24
Finished Mar 28 02:29:21 PM PDT 24
Peak memory 433388 kb
Host smart-e57e769f-90cc-468a-819b-938c66cf7e38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3379430430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3379430430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.3763858668
Short name T208
Test name
Test status
Simulation time 468955478 ps
CPU time 5.15 seconds
Started Mar 28 02:00:08 PM PDT 24
Finished Mar 28 02:00:13 PM PDT 24
Peak memory 216116 kb
Host smart-06e541db-a5e7-4a02-ab5a-98954fd1c35d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763858668 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.3763858668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.2898552351
Short name T522
Test name
Test status
Simulation time 951506105 ps
CPU time 5.39 seconds
Started Mar 28 02:00:07 PM PDT 24
Finished Mar 28 02:00:13 PM PDT 24
Peak memory 216100 kb
Host smart-5b9ade5f-5257-41a6-bafb-a9e7fc1dac35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898552351 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.2898552351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.2698648973
Short name T187
Test name
Test status
Simulation time 98981732038 ps
CPU time 2028.08 seconds
Started Mar 28 02:00:06 PM PDT 24
Finished Mar 28 02:33:55 PM PDT 24
Peak memory 398664 kb
Host smart-1f8d35b6-a47f-4850-8283-31a217bd8912
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2698648973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.2698648973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.282779636
Short name T271
Test name
Test status
Simulation time 1512424901854 ps
CPU time 1861.11 seconds
Started Mar 28 02:00:06 PM PDT 24
Finished Mar 28 02:31:08 PM PDT 24
Peak memory 371484 kb
Host smart-57c31676-ee92-44cc-a376-b8ea6d436cce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=282779636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.282779636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.3147905963
Short name T378
Test name
Test status
Simulation time 27116143887 ps
CPU time 1163.23 seconds
Started Mar 28 02:00:08 PM PDT 24
Finished Mar 28 02:19:32 PM PDT 24
Peak memory 333912 kb
Host smart-282b5d5b-8ee2-4094-9f8d-c8dc317a2edf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3147905963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3147905963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.4133467460
Short name T1029
Test name
Test status
Simulation time 9897365620 ps
CPU time 845.92 seconds
Started Mar 28 02:00:08 PM PDT 24
Finished Mar 28 02:14:14 PM PDT 24
Peak memory 295360 kb
Host smart-0ae7c1f3-7bd3-4029-adb8-49c92d545e6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4133467460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.4133467460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.3418905878
Short name T777
Test name
Test status
Simulation time 201963040652 ps
CPU time 4104.93 seconds
Started Mar 28 02:00:09 PM PDT 24
Finished Mar 28 03:08:35 PM PDT 24
Peak memory 643220 kb
Host smart-32bf571b-ef78-4712-9ac8-f442591d6a1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3418905878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3418905878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.1781004853
Short name T870
Test name
Test status
Simulation time 173752990506 ps
CPU time 3622.3 seconds
Started Mar 28 02:00:05 PM PDT 24
Finished Mar 28 03:00:28 PM PDT 24
Peak memory 565736 kb
Host smart-c42a62da-6f65-41b5-8e36-c9389b509b5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1781004853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.1781004853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.1412615490
Short name T1045
Test name
Test status
Simulation time 49415343 ps
CPU time 0.84 seconds
Started Mar 28 02:01:05 PM PDT 24
Finished Mar 28 02:01:06 PM PDT 24
Peak memory 205524 kb
Host smart-4b612797-eb24-49d6-9746-64a1dc2e99e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412615490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.1412615490 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.153196949
Short name T977
Test name
Test status
Simulation time 2429641449 ps
CPU time 95.17 seconds
Started Mar 28 02:01:05 PM PDT 24
Finished Mar 28 02:02:40 PM PDT 24
Peak memory 229924 kb
Host smart-53621cd9-95a5-4d9e-a122-f8f7d72ed6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153196949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.153196949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.3858472309
Short name T600
Test name
Test status
Simulation time 144176612759 ps
CPU time 527.89 seconds
Started Mar 28 02:00:24 PM PDT 24
Finished Mar 28 02:09:12 PM PDT 24
Peak memory 230372 kb
Host smart-29d7e329-56ed-4a50-8b95-695763a9ecdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858472309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3858472309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.757132631
Short name T961
Test name
Test status
Simulation time 40656782079 ps
CPU time 276.08 seconds
Started Mar 28 02:01:03 PM PDT 24
Finished Mar 28 02:05:39 PM PDT 24
Peak memory 244880 kb
Host smart-63e9c4a6-93d0-45f1-bd24-7c420363441f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757132631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.757132631 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.4166132698
Short name T18
Test name
Test status
Simulation time 1359926065 ps
CPU time 102.31 seconds
Started Mar 28 02:01:04 PM PDT 24
Finished Mar 28 02:02:46 PM PDT 24
Peak memory 240684 kb
Host smart-2635f01e-576c-4688-84fd-f468c425b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166132698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.4166132698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.3693271802
Short name T527
Test name
Test status
Simulation time 460946828 ps
CPU time 2.76 seconds
Started Mar 28 02:01:06 PM PDT 24
Finished Mar 28 02:01:08 PM PDT 24
Peak memory 207200 kb
Host smart-5d03e1d4-d324-4da4-9347-7977dc532828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693271802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3693271802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.266457651
Short name T802
Test name
Test status
Simulation time 39331969 ps
CPU time 1.25 seconds
Started Mar 28 02:01:05 PM PDT 24
Finished Mar 28 02:01:07 PM PDT 24
Peak memory 217476 kb
Host smart-5e8cce91-86f8-4b87-84c5-9fb45757a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266457651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.266457651 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.327040127
Short name T1053
Test name
Test status
Simulation time 31209070989 ps
CPU time 694.77 seconds
Started Mar 28 02:00:21 PM PDT 24
Finished Mar 28 02:11:56 PM PDT 24
Peak memory 300860 kb
Host smart-aed9d998-61c0-41c8-8dfc-721928d85545
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327040127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_an
d_output.327040127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.2801203992
Short name T222
Test name
Test status
Simulation time 16565268089 ps
CPU time 87.8 seconds
Started Mar 28 02:00:25 PM PDT 24
Finished Mar 28 02:01:53 PM PDT 24
Peak memory 228592 kb
Host smart-129ccecb-bacd-4dae-ab7f-efccc7ce57d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801203992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2801203992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.2846352992
Short name T464
Test name
Test status
Simulation time 3923805828 ps
CPU time 51.98 seconds
Started Mar 28 02:00:23 PM PDT 24
Finished Mar 28 02:01:15 PM PDT 24
Peak memory 222148 kb
Host smart-48039e32-4bfb-470e-9ba6-babbd197511a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846352992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2846352992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.705925788
Short name T461
Test name
Test status
Simulation time 69189477567 ps
CPU time 1488.17 seconds
Started Mar 28 02:01:04 PM PDT 24
Finished Mar 28 02:25:52 PM PDT 24
Peak memory 392996 kb
Host smart-fce44195-fe63-4e09-b175-b65ce3277a16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=705925788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.705925788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.2677016152
Short name T517
Test name
Test status
Simulation time 64724238 ps
CPU time 3.94 seconds
Started Mar 28 02:00:40 PM PDT 24
Finished Mar 28 02:00:44 PM PDT 24
Peak memory 216148 kb
Host smart-544618be-c335-4fe9-9424-c570e4783e84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677016152 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.2677016152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.1321497730
Short name T555
Test name
Test status
Simulation time 62205184 ps
CPU time 3.83 seconds
Started Mar 28 02:00:39 PM PDT 24
Finished Mar 28 02:00:42 PM PDT 24
Peak memory 216160 kb
Host smart-cd4c3325-4f7c-45b3-b526-b1cd7d15a0f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321497730 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.1321497730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.2117679074
Short name T723
Test name
Test status
Simulation time 344887570677 ps
CPU time 1820.8 seconds
Started Mar 28 02:00:24 PM PDT 24
Finished Mar 28 02:30:45 PM PDT 24
Peak memory 378048 kb
Host smart-9c526608-20a5-4aad-a8a3-97d2418d2c58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2117679074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.2117679074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.1387966432
Short name T1025
Test name
Test status
Simulation time 63801472400 ps
CPU time 1781.58 seconds
Started Mar 28 02:00:41 PM PDT 24
Finished Mar 28 02:30:22 PM PDT 24
Peak memory 375800 kb
Host smart-b98500e6-8d3c-47f0-b6cf-8aae3090aa3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1387966432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.1387966432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.738320283
Short name T807
Test name
Test status
Simulation time 496230120476 ps
CPU time 1524.84 seconds
Started Mar 28 02:00:38 PM PDT 24
Finished Mar 28 02:26:03 PM PDT 24
Peak memory 332668 kb
Host smart-a59ecf1c-30ff-424c-b58c-ebac4fde311b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=738320283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.738320283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.2748787789
Short name T249
Test name
Test status
Simulation time 39993203401 ps
CPU time 819.33 seconds
Started Mar 28 02:00:39 PM PDT 24
Finished Mar 28 02:14:18 PM PDT 24
Peak memory 297300 kb
Host smart-76e408f5-f279-48e5-8b47-7fb978029a49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2748787789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2748787789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.1481209033
Short name T1020
Test name
Test status
Simulation time 153656083088 ps
CPU time 4165.45 seconds
Started Mar 28 02:00:39 PM PDT 24
Finished Mar 28 03:10:05 PM PDT 24
Peak memory 647400 kb
Host smart-6964a6cb-829d-42f7-8620-832aa05ece85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1481209033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.1481209033 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.1077826814
Short name T528
Test name
Test status
Simulation time 192438138314 ps
CPU time 4093.36 seconds
Started Mar 28 02:00:37 PM PDT 24
Finished Mar 28 03:08:51 PM PDT 24
Peak memory 562288 kb
Host smart-663bfbbf-83ee-4755-94b4-f21cabf4a0a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1077826814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.1077826814 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.77263949
Short name T680
Test name
Test status
Simulation time 22249939 ps
CPU time 0.78 seconds
Started Mar 28 02:01:56 PM PDT 24
Finished Mar 28 02:01:57 PM PDT 24
Peak memory 205592 kb
Host smart-72b8cbd7-7e77-4861-98bb-527d3225f9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77263949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.77263949 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.2784934338
Short name T430
Test name
Test status
Simulation time 44023583377 ps
CPU time 234.93 seconds
Started Mar 28 02:01:29 PM PDT 24
Finished Mar 28 02:05:24 PM PDT 24
Peak memory 239368 kb
Host smart-1e7da901-a3ff-431f-94a6-6ab8c0f3f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784934338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2784934338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3828113266
Short name T788
Test name
Test status
Simulation time 8395894713 ps
CPU time 685.71 seconds
Started Mar 28 02:01:29 PM PDT 24
Finished Mar 28 02:12:55 PM PDT 24
Peak memory 231916 kb
Host smart-f0965876-efa5-4f1b-a57f-4a3f4c56f8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828113266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3828113266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.3204069054
Short name T646
Test name
Test status
Simulation time 96924240459 ps
CPU time 241.27 seconds
Started Mar 28 02:01:28 PM PDT 24
Finished Mar 28 02:05:30 PM PDT 24
Peak memory 240176 kb
Host smart-ee19df70-cab4-4c30-a8f0-5ffb0adf77ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204069054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3204069054 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.3952725519
Short name T910
Test name
Test status
Simulation time 10338982758 ps
CPU time 175.24 seconds
Started Mar 28 02:01:31 PM PDT 24
Finished Mar 28 02:04:26 PM PDT 24
Peak memory 248912 kb
Host smart-ad0492fc-6206-471f-ad61-c3b1d8c937f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952725519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3952725519 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.2979101764
Short name T373
Test name
Test status
Simulation time 6326461755 ps
CPU time 5.99 seconds
Started Mar 28 02:01:56 PM PDT 24
Finished Mar 28 02:02:02 PM PDT 24
Peak memory 207708 kb
Host smart-4f6c948a-befa-477f-87d3-29b330b27ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979101764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2979101764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.3628608003
Short name T194
Test name
Test status
Simulation time 14623728555 ps
CPU time 820.33 seconds
Started Mar 28 02:01:29 PM PDT 24
Finished Mar 28 02:15:09 PM PDT 24
Peak memory 306108 kb
Host smart-eeeb4427-b901-4a33-8330-20e0d521f03f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628608003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.3628608003 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.2178388354
Short name T779
Test name
Test status
Simulation time 7930551735 ps
CPU time 140.18 seconds
Started Mar 28 02:01:28 PM PDT 24
Finished Mar 28 02:03:48 PM PDT 24
Peak memory 233152 kb
Host smart-be599190-258a-49c0-8800-e5724da9937e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178388354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2178388354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.3669450560
Short name T326
Test name
Test status
Simulation time 448321496 ps
CPU time 22.89 seconds
Started Mar 28 02:01:30 PM PDT 24
Finished Mar 28 02:01:53 PM PDT 24
Peak memory 216380 kb
Host smart-025f9560-9f7f-4082-a61b-b0bee3f24dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669450560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3669450560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.3969326450
Short name T77
Test name
Test status
Simulation time 191149415396 ps
CPU time 1466.83 seconds
Started Mar 28 02:01:55 PM PDT 24
Finished Mar 28 02:26:22 PM PDT 24
Peak memory 403200 kb
Host smart-60b6b2f7-b1fc-401a-a747-ee3122bf87c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3969326450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3969326450 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.1965261344
Short name T526
Test name
Test status
Simulation time 237952538 ps
CPU time 4.27 seconds
Started Mar 28 02:01:27 PM PDT 24
Finished Mar 28 02:01:32 PM PDT 24
Peak memory 216148 kb
Host smart-a44a920e-9b7f-4c97-9b3a-b766602df5e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965261344 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.1965261344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.1854232083
Short name T750
Test name
Test status
Simulation time 2147395095 ps
CPU time 4.85 seconds
Started Mar 28 02:01:31 PM PDT 24
Finished Mar 28 02:01:36 PM PDT 24
Peak memory 216108 kb
Host smart-47f7b7a1-a4bf-4a56-819a-06a845816656
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854232083 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.1854232083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.1258625287
Short name T871
Test name
Test status
Simulation time 84561513230 ps
CPU time 1881.98 seconds
Started Mar 28 02:01:31 PM PDT 24
Finished Mar 28 02:32:53 PM PDT 24
Peak memory 393508 kb
Host smart-d9ff7cae-4fb3-4c21-b997-076bdd3e29f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1258625287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.1258625287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.4171528949
Short name T332
Test name
Test status
Simulation time 60027823346 ps
CPU time 1689.51 seconds
Started Mar 28 02:01:30 PM PDT 24
Finished Mar 28 02:29:41 PM PDT 24
Peak memory 367644 kb
Host smart-e0b651d0-9cb1-4c3d-8bab-c1db1b1864e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4171528949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.4171528949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3195468490
Short name T662
Test name
Test status
Simulation time 55499427020 ps
CPU time 1202.5 seconds
Started Mar 28 02:01:29 PM PDT 24
Finished Mar 28 02:21:32 PM PDT 24
Peak memory 340456 kb
Host smart-2181181d-3932-4b74-9528-47142e4bf4a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3195468490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3195468490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.2146190285
Short name T878
Test name
Test status
Simulation time 235589399877 ps
CPU time 907.95 seconds
Started Mar 28 02:01:29 PM PDT 24
Finished Mar 28 02:16:37 PM PDT 24
Peak memory 297592 kb
Host smart-0d09d7f4-94b1-4c86-856b-b4f7a72de3ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2146190285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2146190285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.2026371602
Short name T469
Test name
Test status
Simulation time 262137528597 ps
CPU time 5156.57 seconds
Started Mar 28 02:01:31 PM PDT 24
Finished Mar 28 03:27:28 PM PDT 24
Peak memory 640488 kb
Host smart-c6dad974-c173-47b9-b7cf-f61373082cf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2026371602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.2026371602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.888957466
Short name T73
Test name
Test status
Simulation time 228411774069 ps
CPU time 4250.06 seconds
Started Mar 28 02:01:31 PM PDT 24
Finished Mar 28 03:12:22 PM PDT 24
Peak memory 571456 kb
Host smart-90c7d2ea-ff46-483c-ad65-e3856c9dee22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=888957466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.888957466 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.292229371
Short name T835
Test name
Test status
Simulation time 33208167 ps
CPU time 0.89 seconds
Started Mar 28 02:02:47 PM PDT 24
Finished Mar 28 02:02:47 PM PDT 24
Peak memory 205548 kb
Host smart-ef45eae9-ccce-41b0-81f6-20fc89664583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292229371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.292229371 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.3411050571
Short name T102
Test name
Test status
Simulation time 3801898226 ps
CPU time 226.03 seconds
Started Mar 28 02:02:17 PM PDT 24
Finished Mar 28 02:06:04 PM PDT 24
Peak memory 243924 kb
Host smart-c0c8db2d-0ef8-4021-afa6-8a8f6fb82716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411050571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3411050571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.1111144547
Short name T533
Test name
Test status
Simulation time 630268353 ps
CPU time 12.22 seconds
Started Mar 28 02:02:16 PM PDT 24
Finished Mar 28 02:02:29 PM PDT 24
Peak memory 224228 kb
Host smart-efac5835-dff1-43d6-a6fc-92a3991a1548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111144547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1111144547 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.3954685660
Short name T943
Test name
Test status
Simulation time 19421482423 ps
CPU time 137.61 seconds
Started Mar 28 02:02:46 PM PDT 24
Finished Mar 28 02:05:04 PM PDT 24
Peak memory 248868 kb
Host smart-516988a4-c130-4086-8e7f-0cbec1ab6674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954685660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3954685660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.2965231989
Short name T57
Test name
Test status
Simulation time 1678491765 ps
CPU time 3.14 seconds
Started Mar 28 02:02:46 PM PDT 24
Finished Mar 28 02:02:49 PM PDT 24
Peak memory 207656 kb
Host smart-68f464fa-3bba-4ecb-b872-0e028158ab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965231989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2965231989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.639135152
Short name T916
Test name
Test status
Simulation time 68980765711 ps
CPU time 2192.85 seconds
Started Mar 28 02:01:54 PM PDT 24
Finished Mar 28 02:38:27 PM PDT 24
Peak memory 411928 kb
Host smart-2799ebc7-4ce8-48fa-b72c-e4d4c617ecad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639135152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_an
d_output.639135152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.1708728490
Short name T272
Test name
Test status
Simulation time 4110124012 ps
CPU time 117.14 seconds
Started Mar 28 02:01:56 PM PDT 24
Finished Mar 28 02:03:53 PM PDT 24
Peak memory 229300 kb
Host smart-ac00cbb5-023b-48da-aea5-221d21859efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708728490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1708728490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.2321732469
Short name T1017
Test name
Test status
Simulation time 3596850138 ps
CPU time 58.38 seconds
Started Mar 28 02:01:55 PM PDT 24
Finished Mar 28 02:02:53 PM PDT 24
Peak memory 219800 kb
Host smart-7c2db243-76c8-44d6-8943-de0ab4d5c08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321732469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2321732469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.758700642
Short name T709
Test name
Test status
Simulation time 491980868832 ps
CPU time 1600.29 seconds
Started Mar 28 02:02:46 PM PDT 24
Finished Mar 28 02:29:26 PM PDT 24
Peak memory 420260 kb
Host smart-c785ffb1-0d59-4394-aee9-bdb2e3c6c82f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=758700642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.758700642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.1436797364
Short name T219
Test name
Test status
Simulation time 128064836 ps
CPU time 4.48 seconds
Started Mar 28 02:02:19 PM PDT 24
Finished Mar 28 02:02:24 PM PDT 24
Peak memory 209220 kb
Host smart-59fcf928-97dc-4d3a-bd2e-f89ab0cce080
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436797364 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.1436797364 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.574098600
Short name T829
Test name
Test status
Simulation time 264796694 ps
CPU time 4.16 seconds
Started Mar 28 02:02:18 PM PDT 24
Finished Mar 28 02:02:23 PM PDT 24
Peak memory 216140 kb
Host smart-a024769e-4eb8-4f72-af31-2ca331e94bbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574098600 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.kmac_test_vectors_kmac_xof.574098600 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.1827844888
Short name T743
Test name
Test status
Simulation time 19902533115 ps
CPU time 1657.48 seconds
Started Mar 28 02:02:17 PM PDT 24
Finished Mar 28 02:29:55 PM PDT 24
Peak memory 390132 kb
Host smart-04a1a071-33e7-4396-866f-9a69ffc78a40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1827844888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.1827844888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.2623487874
Short name T792
Test name
Test status
Simulation time 93860859642 ps
CPU time 2038.59 seconds
Started Mar 28 02:02:21 PM PDT 24
Finished Mar 28 02:36:20 PM PDT 24
Peak memory 373116 kb
Host smart-ba90db94-c1d6-4b1e-af56-1455b651e863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2623487874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.2623487874 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.486799848
Short name T1086
Test name
Test status
Simulation time 56433821239 ps
CPU time 1203.22 seconds
Started Mar 28 02:02:21 PM PDT 24
Finished Mar 28 02:22:25 PM PDT 24
Peak memory 333304 kb
Host smart-ba23c46e-452d-4a3b-b7c8-2769081c792d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=486799848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.486799848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.3766739701
Short name T285
Test name
Test status
Simulation time 45187283998 ps
CPU time 738.8 seconds
Started Mar 28 02:02:18 PM PDT 24
Finished Mar 28 02:14:38 PM PDT 24
Peak memory 294692 kb
Host smart-6f8d00ff-7ef4-4350-a953-e24672d37c07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3766739701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.3766739701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.1204721224
Short name T412
Test name
Test status
Simulation time 177687817747 ps
CPU time 4648.73 seconds
Started Mar 28 02:02:17 PM PDT 24
Finished Mar 28 03:19:47 PM PDT 24
Peak memory 652656 kb
Host smart-2d3703e0-59c9-4f34-a4a8-04c98fffe494
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1204721224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.1204721224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.598670590
Short name T1022
Test name
Test status
Simulation time 605933557215 ps
CPU time 4125.47 seconds
Started Mar 28 02:02:18 PM PDT 24
Finished Mar 28 03:11:04 PM PDT 24
Peak memory 561696 kb
Host smart-6210083c-506b-4a31-99e7-fedf38b99a00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=598670590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.598670590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.1904069288
Short name T573
Test name
Test status
Simulation time 92901367 ps
CPU time 0.79 seconds
Started Mar 28 02:03:51 PM PDT 24
Finished Mar 28 02:03:52 PM PDT 24
Peak memory 205520 kb
Host smart-7a66e6f3-eb95-4812-8524-568fbeb9f3c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904069288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1904069288 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.2629481506
Short name T810
Test name
Test status
Simulation time 2467876663 ps
CPU time 137.59 seconds
Started Mar 28 02:03:51 PM PDT 24
Finished Mar 28 02:06:09 PM PDT 24
Peak memory 235968 kb
Host smart-85cacef7-2a8b-481f-86fc-b55d7ec1e84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629481506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2629481506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.3834518670
Short name T1066
Test name
Test status
Simulation time 50022955260 ps
CPU time 717.63 seconds
Started Mar 28 02:03:22 PM PDT 24
Finished Mar 28 02:15:20 PM PDT 24
Peak memory 232200 kb
Host smart-17d73135-b252-4ef3-924a-6278c872d497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834518670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.3834518670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.3365174481
Short name T974
Test name
Test status
Simulation time 748483608 ps
CPU time 12.25 seconds
Started Mar 28 02:03:49 PM PDT 24
Finished Mar 28 02:04:02 PM PDT 24
Peak memory 217356 kb
Host smart-f4ff1607-8a2c-4a11-958c-75800d367fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365174481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3365174481 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.1235447010
Short name T763
Test name
Test status
Simulation time 16240516780 ps
CPU time 378.04 seconds
Started Mar 28 02:03:53 PM PDT 24
Finished Mar 28 02:10:11 PM PDT 24
Peak memory 257092 kb
Host smart-df4aacc9-e1e0-4043-b7e6-b832d0c77226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235447010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1235447010 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.2121393394
Short name T734
Test name
Test status
Simulation time 3806344503 ps
CPU time 5.55 seconds
Started Mar 28 02:03:50 PM PDT 24
Finished Mar 28 02:03:56 PM PDT 24
Peak memory 207876 kb
Host smart-6b635078-243e-4cf4-8f54-e73ade1c2d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121393394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2121393394 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.811206478
Short name T51
Test name
Test status
Simulation time 91337263 ps
CPU time 1.49 seconds
Started Mar 28 02:03:49 PM PDT 24
Finished Mar 28 02:03:51 PM PDT 24
Peak memory 216020 kb
Host smart-6c0a579b-40d2-4149-a96c-1747bf920736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811206478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.811206478 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.2613186077
Short name T252
Test name
Test status
Simulation time 103071759406 ps
CPU time 1682.2 seconds
Started Mar 28 02:03:21 PM PDT 24
Finished Mar 28 02:31:24 PM PDT 24
Peak memory 351924 kb
Host smart-3b8be4d9-394a-4ab7-9030-7e91e5a7d2e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613186077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.2613186077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.2523074921
Short name T741
Test name
Test status
Simulation time 47131976746 ps
CPU time 251.94 seconds
Started Mar 28 02:03:21 PM PDT 24
Finished Mar 28 02:07:33 PM PDT 24
Peak memory 236384 kb
Host smart-eafc9513-4e9b-460b-8bed-bc5a0d01ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523074921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.2523074921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.60396422
Short name T978
Test name
Test status
Simulation time 264612896 ps
CPU time 14.33 seconds
Started Mar 28 02:02:45 PM PDT 24
Finished Mar 28 02:03:00 PM PDT 24
Peak memory 219660 kb
Host smart-31cdefd3-a912-4994-9d24-72da14795774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60396422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.60396422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.2857130894
Short name T830
Test name
Test status
Simulation time 109209240387 ps
CPU time 1197.74 seconds
Started Mar 28 02:03:48 PM PDT 24
Finished Mar 28 02:23:46 PM PDT 24
Peak memory 354720 kb
Host smart-edea8aa6-e482-4f75-ba7a-57d384a4d253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2857130894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2857130894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.2924659663
Short name T869
Test name
Test status
Simulation time 174114971 ps
CPU time 5.13 seconds
Started Mar 28 02:03:25 PM PDT 24
Finished Mar 28 02:03:31 PM PDT 24
Peak memory 216128 kb
Host smart-4e3e5b95-2ce7-4cb0-a468-0d7a487780be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924659663 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.2924659663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2414935347
Short name T359
Test name
Test status
Simulation time 605403591 ps
CPU time 4.82 seconds
Started Mar 28 02:03:23 PM PDT 24
Finished Mar 28 02:03:28 PM PDT 24
Peak memory 216092 kb
Host smart-90e4eff8-c36e-4fd4-a672-7735d6dd50f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414935347 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2414935347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.779810431
Short name T697
Test name
Test status
Simulation time 192067470400 ps
CPU time 2101.77 seconds
Started Mar 28 02:03:22 PM PDT 24
Finished Mar 28 02:38:24 PM PDT 24
Peak memory 388296 kb
Host smart-23ec5cbd-9e45-4e0a-a4da-09f96bc3eed2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=779810431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.779810431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.3172378483
Short name T625
Test name
Test status
Simulation time 62666308531 ps
CPU time 1778.29 seconds
Started Mar 28 02:03:21 PM PDT 24
Finished Mar 28 02:33:00 PM PDT 24
Peak memory 369208 kb
Host smart-9e413ed3-b6ad-4806-a30c-7ecbeaadd4a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3172378483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.3172378483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.1360550174
Short name T922
Test name
Test status
Simulation time 47231670420 ps
CPU time 1347.96 seconds
Started Mar 28 02:03:24 PM PDT 24
Finished Mar 28 02:25:52 PM PDT 24
Peak memory 337480 kb
Host smart-5bba6cb6-7824-41fe-9f17-076dfb5c654e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1360550174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.1360550174 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.3237025787
Short name T513
Test name
Test status
Simulation time 48508099693 ps
CPU time 1049.83 seconds
Started Mar 28 02:03:22 PM PDT 24
Finished Mar 28 02:20:52 PM PDT 24
Peak memory 294100 kb
Host smart-d40ff886-74f0-4dfa-a929-15cdbc2683bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3237025787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.3237025787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.1665801986
Short name T367
Test name
Test status
Simulation time 50556123166 ps
CPU time 4107.18 seconds
Started Mar 28 02:03:24 PM PDT 24
Finished Mar 28 03:11:52 PM PDT 24
Peak memory 643768 kb
Host smart-ceefc379-8d01-4a08-ae14-eecbb079bda7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1665801986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.1665801986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.2392082161
Short name T145
Test name
Test status
Simulation time 602605234694 ps
CPU time 4093.16 seconds
Started Mar 28 02:03:21 PM PDT 24
Finished Mar 28 03:11:35 PM PDT 24
Peak memory 556888 kb
Host smart-a2530f5d-9a15-4d46-87c9-19a984ae6e1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2392082161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.2392082161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3033224947
Short name T868
Test name
Test status
Simulation time 48312206 ps
CPU time 0.8 seconds
Started Mar 28 02:05:00 PM PDT 24
Finished Mar 28 02:05:01 PM PDT 24
Peak memory 205516 kb
Host smart-d07eb361-7b70-458d-9e3f-3ac4d655538a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033224947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3033224947 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1715189229
Short name T1
Test name
Test status
Simulation time 13087366867 ps
CPU time 64.31 seconds
Started Mar 28 02:04:37 PM PDT 24
Finished Mar 28 02:05:41 PM PDT 24
Peak memory 224792 kb
Host smart-92b4e020-f8a9-48fb-9192-0e467f278dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715189229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1715189229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.656493349
Short name T765
Test name
Test status
Simulation time 18845643104 ps
CPU time 321.04 seconds
Started Mar 28 02:03:48 PM PDT 24
Finished Mar 28 02:09:10 PM PDT 24
Peak memory 227472 kb
Host smart-f1cd7af3-9842-4b59-8584-2c0b3cdb0e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656493349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.656493349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.1055301494
Short name T305
Test name
Test status
Simulation time 64992239594 ps
CPU time 233.24 seconds
Started Mar 28 02:04:38 PM PDT 24
Finished Mar 28 02:08:32 PM PDT 24
Peak memory 240540 kb
Host smart-341edb58-6512-4495-97e3-2c55605dcc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055301494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1055301494 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.3190944534
Short name T425
Test name
Test status
Simulation time 9708868497 ps
CPU time 195.34 seconds
Started Mar 28 02:04:37 PM PDT 24
Finished Mar 28 02:07:52 PM PDT 24
Peak memory 240660 kb
Host smart-c466756d-ba60-4e20-a754-b645a519aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190944534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3190944534 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.2959531317
Short name T925
Test name
Test status
Simulation time 140861811 ps
CPU time 1.32 seconds
Started Mar 28 02:04:40 PM PDT 24
Finished Mar 28 02:04:42 PM PDT 24
Peak memory 216040 kb
Host smart-d26945c1-ce08-410d-b19b-2a27d08e9499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959531317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2959531317 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.218735610
Short name T340
Test name
Test status
Simulation time 85222043261 ps
CPU time 1954.68 seconds
Started Mar 28 02:03:49 PM PDT 24
Finished Mar 28 02:36:25 PM PDT 24
Peak memory 391168 kb
Host smart-0a0b8285-0eca-48b6-9579-b7f77b64dc72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218735610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_an
d_output.218735610 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.2254267286
Short name T523
Test name
Test status
Simulation time 37484812817 ps
CPU time 401.53 seconds
Started Mar 28 02:03:48 PM PDT 24
Finished Mar 28 02:10:30 PM PDT 24
Peak memory 249584 kb
Host smart-1e35286e-309c-48dc-87b3-7b466d0220d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254267286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2254267286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.1118356549
Short name T233
Test name
Test status
Simulation time 2336243523 ps
CPU time 28.57 seconds
Started Mar 28 02:03:50 PM PDT 24
Finished Mar 28 02:04:19 PM PDT 24
Peak memory 216200 kb
Host smart-d500f889-a92b-47fa-8f3c-18feb5f340c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118356549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1118356549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.1586352617
Short name T631
Test name
Test status
Simulation time 36802538904 ps
CPU time 1042.49 seconds
Started Mar 28 02:04:58 PM PDT 24
Finished Mar 28 02:22:21 PM PDT 24
Peak memory 347256 kb
Host smart-21ab3187-c681-4e98-b42c-ddeb60aad2d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1586352617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1586352617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.951267172
Short name T786
Test name
Test status
Simulation time 693171404 ps
CPU time 4.46 seconds
Started Mar 28 02:04:05 PM PDT 24
Finished Mar 28 02:04:10 PM PDT 24
Peak memory 216108 kb
Host smart-b56ae61b-8a45-43b9-80ad-57a469c0c7da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951267172 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.kmac_test_vectors_kmac.951267172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.156201463
Short name T890
Test name
Test status
Simulation time 176878437 ps
CPU time 4.41 seconds
Started Mar 28 02:04:37 PM PDT 24
Finished Mar 28 02:04:41 PM PDT 24
Peak memory 216108 kb
Host smart-16e460b1-1403-4904-b4e4-aa796ce2f8c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156201463 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.kmac_test_vectors_kmac_xof.156201463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.981855975
Short name T747
Test name
Test status
Simulation time 495842345680 ps
CPU time 1990.34 seconds
Started Mar 28 02:03:52 PM PDT 24
Finished Mar 28 02:37:03 PM PDT 24
Peak memory 389340 kb
Host smart-87aa4a94-d595-42a1-b73a-09ae65124fca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=981855975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.981855975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.4038196092
Short name T241
Test name
Test status
Simulation time 45539585914 ps
CPU time 1485.97 seconds
Started Mar 28 02:04:05 PM PDT 24
Finished Mar 28 02:28:52 PM PDT 24
Peak memory 365292 kb
Host smart-93b5083d-2cb8-4466-99f0-dbcc7075d072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4038196092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.4038196092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.3887214504
Short name T548
Test name
Test status
Simulation time 56459719770 ps
CPU time 1115.04 seconds
Started Mar 28 02:04:10 PM PDT 24
Finished Mar 28 02:22:45 PM PDT 24
Peak memory 334128 kb
Host smart-2d5a0b92-e859-429a-a770-33f05c84b351
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3887214504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.3887214504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.514312762
Short name T192
Test name
Test status
Simulation time 20138415397 ps
CPU time 814.57 seconds
Started Mar 28 02:04:06 PM PDT 24
Finished Mar 28 02:17:41 PM PDT 24
Peak memory 294440 kb
Host smart-329505dd-593d-49a5-8097-31f986e97ec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=514312762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.514312762 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.1824149075
Short name T593
Test name
Test status
Simulation time 174614818177 ps
CPU time 4346.72 seconds
Started Mar 28 02:04:06 PM PDT 24
Finished Mar 28 03:16:33 PM PDT 24
Peak memory 635560 kb
Host smart-b5cf6383-9acc-435f-b6d1-c3068f153761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1824149075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.1824149075 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.2097694207
Short name T805
Test name
Test status
Simulation time 858681849406 ps
CPU time 4524.9 seconds
Started Mar 28 02:04:06 PM PDT 24
Finished Mar 28 03:19:31 PM PDT 24
Peak memory 565996 kb
Host smart-1eacf877-c4f0-40da-8e89-23d900cd32e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2097694207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.2097694207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.1872649230
Short name T524
Test name
Test status
Simulation time 56941402 ps
CPU time 0.83 seconds
Started Mar 28 02:05:45 PM PDT 24
Finished Mar 28 02:05:46 PM PDT 24
Peak memory 205524 kb
Host smart-17f40d81-abc5-4308-8804-915c9063250b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872649230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1872649230 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.4011181698
Short name T585
Test name
Test status
Simulation time 21386738063 ps
CPU time 132.68 seconds
Started Mar 28 02:05:19 PM PDT 24
Finished Mar 28 02:07:37 PM PDT 24
Peak memory 235864 kb
Host smart-ed926215-d437-4826-9af5-175b641b3de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011181698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.4011181698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.1587576269
Short name T396
Test name
Test status
Simulation time 3352465383 ps
CPU time 290.85 seconds
Started Mar 28 02:05:00 PM PDT 24
Finished Mar 28 02:09:51 PM PDT 24
Peak memory 227916 kb
Host smart-baaec131-1935-42a1-8fc9-b2260f3a8e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587576269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1587576269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.1886448425
Short name T494
Test name
Test status
Simulation time 153682682593 ps
CPU time 198.12 seconds
Started Mar 28 02:05:18 PM PDT 24
Finished Mar 28 02:08:39 PM PDT 24
Peak memory 233656 kb
Host smart-8435c756-5394-48e6-a595-1372cd69b81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886448425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1886448425 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.1015742828
Short name T889
Test name
Test status
Simulation time 8185771160 ps
CPU time 46.73 seconds
Started Mar 28 02:05:19 PM PDT 24
Finished Mar 28 02:06:07 PM PDT 24
Peak memory 238340 kb
Host smart-2f31f71c-753f-4a63-938a-07b3a859b4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015742828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1015742828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.2298891354
Short name T1064
Test name
Test status
Simulation time 192599388 ps
CPU time 1.6 seconds
Started Mar 28 02:05:19 PM PDT 24
Finished Mar 28 02:05:22 PM PDT 24
Peak memory 207360 kb
Host smart-4a8a0afc-8abc-4c9c-b606-e94e35c9b6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298891354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2298891354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1870180740
Short name T255
Test name
Test status
Simulation time 28654258 ps
CPU time 1.39 seconds
Started Mar 28 02:05:22 PM PDT 24
Finished Mar 28 02:05:26 PM PDT 24
Peak memory 218240 kb
Host smart-41415928-96a8-48ad-8052-e4fb18d30f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870180740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1870180740 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.3647432671
Short name T14
Test name
Test status
Simulation time 49049376592 ps
CPU time 1411.29 seconds
Started Mar 28 02:04:59 PM PDT 24
Finished Mar 28 02:28:30 PM PDT 24
Peak memory 354092 kb
Host smart-8a992f83-6706-41a0-a357-cc390619ea71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647432671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.3647432671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.3678740347
Short name T214
Test name
Test status
Simulation time 13515953611 ps
CPU time 96.28 seconds
Started Mar 28 02:04:59 PM PDT 24
Finished Mar 28 02:06:35 PM PDT 24
Peak memory 227944 kb
Host smart-ff2ab434-5bf0-4c9c-9e34-16f56c84ce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678740347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3678740347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.2622491130
Short name T337
Test name
Test status
Simulation time 395242565 ps
CPU time 22.47 seconds
Started Mar 28 02:04:59 PM PDT 24
Finished Mar 28 02:05:21 PM PDT 24
Peak memory 219332 kb
Host smart-7ebe7229-2ce8-4cae-bd01-8a994885c9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622491130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2622491130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.2228628044
Short name T774
Test name
Test status
Simulation time 8373609813 ps
CPU time 253.84 seconds
Started Mar 28 02:05:42 PM PDT 24
Finished Mar 28 02:09:56 PM PDT 24
Peak memory 234656 kb
Host smart-d304a290-9877-4b54-9ff1-ccfd7560b492
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2228628044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2228628044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.3048767486
Short name T1074
Test name
Test status
Simulation time 401721423 ps
CPU time 4.83 seconds
Started Mar 28 02:05:19 PM PDT 24
Finished Mar 28 02:05:25 PM PDT 24
Peak memory 216120 kb
Host smart-22e5892d-4698-4383-bac5-210e90175661
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048767486 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.3048767486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3428513207
Short name T377
Test name
Test status
Simulation time 63218179 ps
CPU time 4.38 seconds
Started Mar 28 02:05:19 PM PDT 24
Finished Mar 28 02:05:24 PM PDT 24
Peak memory 216148 kb
Host smart-a17e0c45-a0fe-48a4-a4b1-a8437fd6d9c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428513207 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3428513207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.1731114421
Short name T553
Test name
Test status
Simulation time 266211067561 ps
CPU time 1917.73 seconds
Started Mar 28 02:05:00 PM PDT 24
Finished Mar 28 02:36:58 PM PDT 24
Peak memory 402640 kb
Host smart-848c8c79-1efe-41d7-951b-b3f845376f3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1731114421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.1731114421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.2174157167
Short name T254
Test name
Test status
Simulation time 65275056700 ps
CPU time 1749.41 seconds
Started Mar 28 02:05:01 PM PDT 24
Finished Mar 28 02:34:11 PM PDT 24
Peak memory 389948 kb
Host smart-66e2bb0e-ad5d-412a-8116-2a0b3fdded24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2174157167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.2174157167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.3171813590
Short name T336
Test name
Test status
Simulation time 90426651153 ps
CPU time 1102.67 seconds
Started Mar 28 02:05:02 PM PDT 24
Finished Mar 28 02:23:25 PM PDT 24
Peak memory 333464 kb
Host smart-316169db-1e9a-41cf-a450-e8f685ee62c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3171813590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3171813590 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.768238648
Short name T1076
Test name
Test status
Simulation time 135158565775 ps
CPU time 908.58 seconds
Started Mar 28 02:05:02 PM PDT 24
Finished Mar 28 02:20:11 PM PDT 24
Peak memory 294508 kb
Host smart-8c34b63e-0e63-4ae1-8bf5-8b55ff1a73f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=768238648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.768238648 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.4194969017
Short name T185
Test name
Test status
Simulation time 228649769757 ps
CPU time 5078.04 seconds
Started Mar 28 02:04:59 PM PDT 24
Finished Mar 28 03:29:38 PM PDT 24
Peak memory 656300 kb
Host smart-b1de3c0a-5155-44d6-915d-f2c68664fe28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4194969017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.4194969017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.1471398872
Short name T306
Test name
Test status
Simulation time 44171315159 ps
CPU time 3542.61 seconds
Started Mar 28 02:05:23 PM PDT 24
Finished Mar 28 03:04:28 PM PDT 24
Peak memory 561680 kb
Host smart-b4b3dd01-323b-47cc-8def-9ed55d2978fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1471398872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1471398872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.4056068242
Short name T892
Test name
Test status
Simulation time 46935408 ps
CPU time 0.81 seconds
Started Mar 28 01:50:51 PM PDT 24
Finished Mar 28 01:50:52 PM PDT 24
Peak memory 205524 kb
Host smart-59d5bde2-0fd5-45e6-806b-898bb8fd87d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056068242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.4056068242 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.284710973
Short name T230
Test name
Test status
Simulation time 861605580 ps
CPU time 17.72 seconds
Started Mar 28 01:50:29 PM PDT 24
Finished Mar 28 01:50:48 PM PDT 24
Peak memory 224216 kb
Host smart-f003c5f4-2289-443f-99db-909288002bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284710973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.284710973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.1079642798
Short name T570
Test name
Test status
Simulation time 2503934879 ps
CPU time 73.81 seconds
Started Mar 28 01:50:23 PM PDT 24
Finished Mar 28 01:51:37 PM PDT 24
Peak memory 227604 kb
Host smart-504fef25-01d3-4847-90b1-7f809a335c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079642798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.1079642798 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.4284824587
Short name T898
Test name
Test status
Simulation time 24919414252 ps
CPU time 707.58 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 02:02:16 PM PDT 24
Peak memory 232756 kb
Host smart-e8bdad0b-bad3-4134-96b9-61d29fe369eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284824587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.4284824587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2089063900
Short name T505
Test name
Test status
Simulation time 7388878675 ps
CPU time 23.63 seconds
Started Mar 28 01:50:52 PM PDT 24
Finished Mar 28 01:51:16 PM PDT 24
Peak memory 219708 kb
Host smart-3d18d1be-83c0-4425-9cf8-156b42b147d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2089063900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2089063900 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.2154798422
Short name T549
Test name
Test status
Simulation time 1043746859 ps
CPU time 21.35 seconds
Started Mar 28 01:50:52 PM PDT 24
Finished Mar 28 01:51:14 PM PDT 24
Peak memory 224088 kb
Host smart-3b624ae7-3a81-41d3-9f6f-b2d87ac0e3fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2154798422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2154798422 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.157730316
Short name T737
Test name
Test status
Simulation time 4589443447 ps
CPU time 18.73 seconds
Started Mar 28 01:50:49 PM PDT 24
Finished Mar 28 01:51:09 PM PDT 24
Peak memory 217172 kb
Host smart-fdbd8e03-283f-40d9-b5de-1b77e9b1fbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157730316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.157730316 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.1748795599
Short name T101
Test name
Test status
Simulation time 30740748476 ps
CPU time 292.02 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 01:55:47 PM PDT 24
Peak memory 244652 kb
Host smart-9c4bf8d8-a74c-4a54-a2e6-075822748f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748795599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1748795599 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.127727525
Short name T411
Test name
Test status
Simulation time 24156360721 ps
CPU time 103.54 seconds
Started Mar 28 01:50:46 PM PDT 24
Finished Mar 28 01:52:30 PM PDT 24
Peak memory 240676 kb
Host smart-e25244a4-da40-4930-867c-cee9850b4f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127727525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.127727525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.991395833
Short name T510
Test name
Test status
Simulation time 914894866 ps
CPU time 4.91 seconds
Started Mar 28 01:50:47 PM PDT 24
Finished Mar 28 01:50:52 PM PDT 24
Peak memory 207604 kb
Host smart-2b3b8ade-f7e9-49ff-84ac-53905b836c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991395833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.991395833 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1840180767
Short name T53
Test name
Test status
Simulation time 153507114 ps
CPU time 1.22 seconds
Started Mar 28 01:50:53 PM PDT 24
Finished Mar 28 01:50:54 PM PDT 24
Peak memory 216008 kb
Host smart-c8b1b883-1168-4925-91b3-b3d5cb75b884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840180767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1840180767 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.2574798551
Short name T690
Test name
Test status
Simulation time 107675724133 ps
CPU time 1996.06 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 02:23:43 PM PDT 24
Peak memory 411196 kb
Host smart-3719f707-8f59-47e5-aa20-1c98f3be03fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574798551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.2574798551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.3879270917
Short name T1059
Test name
Test status
Simulation time 2368889781 ps
CPU time 144.04 seconds
Started Mar 28 01:50:46 PM PDT 24
Finished Mar 28 01:53:10 PM PDT 24
Peak memory 236160 kb
Host smart-1fdbd97c-ecf8-4eea-b376-da4c3b563c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879270917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3879270917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sideload.1338146225
Short name T791
Test name
Test status
Simulation time 2810234817 ps
CPU time 195.53 seconds
Started Mar 28 01:50:29 PM PDT 24
Finished Mar 28 01:53:45 PM PDT 24
Peak memory 239132 kb
Host smart-e3396607-0ae8-4ba2-b9a5-8701ac9788b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338146225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1338146225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.2224850568
Short name T816
Test name
Test status
Simulation time 236318017 ps
CPU time 11.58 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 01:50:40 PM PDT 24
Peak memory 224224 kb
Host smart-2a46953c-d360-4e6f-a21f-6b85127c2fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224850568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2224850568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1625179656
Short name T831
Test name
Test status
Simulation time 12034421985 ps
CPU time 900.25 seconds
Started Mar 28 01:50:48 PM PDT 24
Finished Mar 28 02:05:49 PM PDT 24
Peak memory 362312 kb
Host smart-e596182d-2334-48d7-bc0d-50610906e5f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1625179656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1625179656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.1420199927
Short name T495
Test name
Test status
Simulation time 179425100 ps
CPU time 4.47 seconds
Started Mar 28 01:50:26 PM PDT 24
Finished Mar 28 01:50:30 PM PDT 24
Peak memory 216112 kb
Host smart-a3d739a9-c704-41d9-b494-011d534fdce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420199927 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.1420199927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.776411950
Short name T236
Test name
Test status
Simulation time 739693142 ps
CPU time 4.86 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 01:50:32 PM PDT 24
Peak memory 216144 kb
Host smart-65879e54-dc3a-49f3-bc48-4d1f2336d15c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776411950 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.kmac_test_vectors_kmac_xof.776411950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.2155729403
Short name T905
Test name
Test status
Simulation time 67767299947 ps
CPU time 1829.85 seconds
Started Mar 28 01:50:24 PM PDT 24
Finished Mar 28 02:20:54 PM PDT 24
Peak memory 393348 kb
Host smart-4508e703-3782-4f2a-a5f3-0bcfdee93941
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2155729403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2155729403 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.1983368980
Short name T498
Test name
Test status
Simulation time 18151883347 ps
CPU time 1516.63 seconds
Started Mar 28 01:50:26 PM PDT 24
Finished Mar 28 02:15:43 PM PDT 24
Peak memory 375480 kb
Host smart-98100930-dc6d-479b-a6e5-a9318974a60f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1983368980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1983368980 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.4250384332
Short name T717
Test name
Test status
Simulation time 27041088243 ps
CPU time 1124.01 seconds
Started Mar 28 01:50:29 PM PDT 24
Finished Mar 28 02:09:14 PM PDT 24
Peak memory 327436 kb
Host smart-bd2e5262-7337-47cc-8f57-2e261b4a84df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4250384332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.4250384332 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.2621793150
Short name T226
Test name
Test status
Simulation time 495369761954 ps
CPU time 1054.66 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 02:08:02 PM PDT 24
Peak memory 298252 kb
Host smart-5ce98ad1-7a3d-4b1d-8a66-f46f53f56e0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2621793150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2621793150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.3932768850
Short name T315
Test name
Test status
Simulation time 720556782204 ps
CPU time 4392.17 seconds
Started Mar 28 01:50:27 PM PDT 24
Finished Mar 28 03:03:41 PM PDT 24
Peak memory 641460 kb
Host smart-1036b54a-5c9c-4e59-bcd8-48ddc0de4fc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3932768850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3932768850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.2728805497
Short name T672
Test name
Test status
Simulation time 90796584928 ps
CPU time 3910.49 seconds
Started Mar 28 01:50:26 PM PDT 24
Finished Mar 28 02:55:37 PM PDT 24
Peak memory 568172 kb
Host smart-d5bffa29-8903-41d3-b785-8d54601545ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2728805497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2728805497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.254248934
Short name T551
Test name
Test status
Simulation time 50405281 ps
CPU time 0.77 seconds
Started Mar 28 02:06:28 PM PDT 24
Finished Mar 28 02:06:29 PM PDT 24
Peak memory 205572 kb
Host smart-a66da1cf-d6b2-4acd-a6b4-ad0da525c722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254248934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.254248934 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_burst_write.2673564327
Short name T229
Test name
Test status
Simulation time 15527851191 ps
CPU time 523.58 seconds
Started Mar 28 02:05:43 PM PDT 24
Finished Mar 28 02:14:27 PM PDT 24
Peak memory 230252 kb
Host smart-d56091dc-28dd-48e6-9d7f-6b46163ccb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673564327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2673564327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.2022054678
Short name T1035
Test name
Test status
Simulation time 17043844502 ps
CPU time 111.63 seconds
Started Mar 28 02:06:29 PM PDT 24
Finished Mar 28 02:08:21 PM PDT 24
Peak memory 233252 kb
Host smart-06f80421-7989-4ae5-8b17-ab1879e0e4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022054678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2022054678 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.3284650554
Short name T516
Test name
Test status
Simulation time 15368599166 ps
CPU time 174.09 seconds
Started Mar 28 02:06:29 PM PDT 24
Finished Mar 28 02:09:23 PM PDT 24
Peak memory 248852 kb
Host smart-0380fd9d-8419-4919-a22f-7cd3d93a397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284650554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3284650554 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.1533034833
Short name T56
Test name
Test status
Simulation time 908565820 ps
CPU time 1.73 seconds
Started Mar 28 02:06:30 PM PDT 24
Finished Mar 28 02:06:32 PM PDT 24
Peak memory 207136 kb
Host smart-dd153dcc-d9c9-4102-ba03-457d5c7e7d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533034833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1533034833 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.395639864
Short name T1036
Test name
Test status
Simulation time 41283411 ps
CPU time 1.39 seconds
Started Mar 28 02:06:28 PM PDT 24
Finished Mar 28 02:06:30 PM PDT 24
Peak memory 215984 kb
Host smart-32ec5a3c-9d67-46f3-96b1-2351198e98eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395639864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.395639864 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.2996347493
Short name T184
Test name
Test status
Simulation time 12313848940 ps
CPU time 384.61 seconds
Started Mar 28 02:05:44 PM PDT 24
Finished Mar 28 02:12:09 PM PDT 24
Peak memory 254396 kb
Host smart-dd90d9ea-d991-4ea6-a144-a0a41850acf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996347493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.2996347493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.2105526840
Short name T1012
Test name
Test status
Simulation time 8105953325 ps
CPU time 168.31 seconds
Started Mar 28 02:05:42 PM PDT 24
Finished Mar 28 02:08:31 PM PDT 24
Peak memory 233876 kb
Host smart-f8fecec7-9fc0-43b5-9826-28d8ac539ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105526840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2105526840 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.790996285
Short name T874
Test name
Test status
Simulation time 3669967016 ps
CPU time 40.76 seconds
Started Mar 28 02:05:44 PM PDT 24
Finished Mar 28 02:06:25 PM PDT 24
Peak memory 222232 kb
Host smart-ed6ea212-c870-46b2-8d06-bc996567c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790996285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.790996285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.3639498242
Short name T822
Test name
Test status
Simulation time 25920235769 ps
CPU time 431.45 seconds
Started Mar 28 02:06:28 PM PDT 24
Finished Mar 28 02:13:39 PM PDT 24
Peak memory 271224 kb
Host smart-48e7272e-672e-4cf5-a357-2b063475c559
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3639498242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3639498242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.2099155003
Short name T619
Test name
Test status
Simulation time 633092236 ps
CPU time 4.51 seconds
Started Mar 28 02:06:07 PM PDT 24
Finished Mar 28 02:06:12 PM PDT 24
Peak memory 216124 kb
Host smart-2a625069-226b-4c81-9e0a-4bb18acf3e63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099155003 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.2099155003 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1403198493
Short name T466
Test name
Test status
Simulation time 173280831 ps
CPU time 4.56 seconds
Started Mar 28 02:06:07 PM PDT 24
Finished Mar 28 02:06:12 PM PDT 24
Peak memory 216152 kb
Host smart-06abbc0d-6a08-4d33-af3f-ef811077b058
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403198493 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1403198493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.2035738887
Short name T962
Test name
Test status
Simulation time 102930705074 ps
CPU time 2126.42 seconds
Started Mar 28 02:05:43 PM PDT 24
Finished Mar 28 02:41:09 PM PDT 24
Peak memory 398556 kb
Host smart-db4e1122-7015-45ed-8ab2-76c281e1fdee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2035738887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.2035738887 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.485352925
Short name T860
Test name
Test status
Simulation time 93384606453 ps
CPU time 1480.65 seconds
Started Mar 28 02:05:41 PM PDT 24
Finished Mar 28 02:30:22 PM PDT 24
Peak memory 374424 kb
Host smart-44ac43f3-dec9-49cd-a43c-cc6278179a64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=485352925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.485352925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.2846690545
Short name T541
Test name
Test status
Simulation time 75073766321 ps
CPU time 1451.18 seconds
Started Mar 28 02:05:44 PM PDT 24
Finished Mar 28 02:29:56 PM PDT 24
Peak memory 339628 kb
Host smart-6972ab18-024e-45a0-88e8-65cab788b04c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2846690545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.2846690545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.2308925869
Short name T785
Test name
Test status
Simulation time 19826069804 ps
CPU time 839.83 seconds
Started Mar 28 02:06:07 PM PDT 24
Finished Mar 28 02:20:07 PM PDT 24
Peak memory 295848 kb
Host smart-3efd047d-63b2-4d5f-92bd-e5b25abeba8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2308925869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.2308925869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.2942769901
Short name T556
Test name
Test status
Simulation time 52084176698 ps
CPU time 4031.98 seconds
Started Mar 28 02:06:07 PM PDT 24
Finished Mar 28 03:13:20 PM PDT 24
Peak memory 635928 kb
Host smart-e8ea33b6-f8ad-41ac-877e-1541fa2bdd51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2942769901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.2942769901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.2779519582
Short name T966
Test name
Test status
Simulation time 45000444626 ps
CPU time 3482.1 seconds
Started Mar 28 02:06:09 PM PDT 24
Finished Mar 28 03:04:11 PM PDT 24
Peak memory 569720 kb
Host smart-82cd915d-c57e-45bd-a77f-97234b5cefc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2779519582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.2779519582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.2352450279
Short name T296
Test name
Test status
Simulation time 15153770 ps
CPU time 0.78 seconds
Started Mar 28 02:07:35 PM PDT 24
Finished Mar 28 02:07:36 PM PDT 24
Peak memory 205400 kb
Host smart-540566d9-e023-4f3b-8599-9c4b84b87bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352450279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2352450279 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.4107000440
Short name T812
Test name
Test status
Simulation time 44716544786 ps
CPU time 297.09 seconds
Started Mar 28 02:07:07 PM PDT 24
Finished Mar 28 02:12:05 PM PDT 24
Peak memory 244856 kb
Host smart-bb0e8b9b-0f0d-443e-9825-3bfe87c4dea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107000440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.4107000440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.4089204300
Short name T546
Test name
Test status
Simulation time 33598757326 ps
CPU time 184.51 seconds
Started Mar 28 02:06:30 PM PDT 24
Finished Mar 28 02:09:35 PM PDT 24
Peak memory 224276 kb
Host smart-b733f305-4fd7-4dc2-a43d-92f2f9ecd9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089204300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.4089204300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.1539447165
Short name T989
Test name
Test status
Simulation time 14209273751 ps
CPU time 317.75 seconds
Started Mar 28 02:07:33 PM PDT 24
Finished Mar 28 02:12:51 PM PDT 24
Peak memory 245868 kb
Host smart-50e84b8f-75b8-446f-8a16-6e6355deb9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539447165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1539447165 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.2816998457
Short name T960
Test name
Test status
Simulation time 16815137996 ps
CPU time 122.45 seconds
Started Mar 28 02:07:34 PM PDT 24
Finished Mar 28 02:09:36 PM PDT 24
Peak memory 250940 kb
Host smart-f53ef6ff-93ca-44a6-836c-62c8ed9b3013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816998457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2816998457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.1469059183
Short name T19
Test name
Test status
Simulation time 1060122105 ps
CPU time 5.46 seconds
Started Mar 28 02:07:37 PM PDT 24
Finished Mar 28 02:07:45 PM PDT 24
Peak memory 207716 kb
Host smart-57ee289e-51bf-4150-ac7b-7b7a4f1c8301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469059183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1469059183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.1951640786
Short name T766
Test name
Test status
Simulation time 325209122 ps
CPU time 1.25 seconds
Started Mar 28 02:07:33 PM PDT 24
Finished Mar 28 02:07:35 PM PDT 24
Peak memory 215984 kb
Host smart-5b6a345c-83d3-4e30-b66f-1f8a76268e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951640786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1951640786 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.524692579
Short name T1000
Test name
Test status
Simulation time 76293389910 ps
CPU time 1018.05 seconds
Started Mar 28 02:06:29 PM PDT 24
Finished Mar 28 02:23:27 PM PDT 24
Peak memory 321196 kb
Host smart-c38e6da4-e522-4382-a042-6906fccfe9ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524692579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_an
d_output.524692579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.813518790
Short name T314
Test name
Test status
Simulation time 1286921260 ps
CPU time 103.12 seconds
Started Mar 28 02:06:31 PM PDT 24
Finished Mar 28 02:08:14 PM PDT 24
Peak memory 227228 kb
Host smart-f0799600-3a74-4cb4-8c65-4a4d80028033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813518790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.813518790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.2262289403
Short name T512
Test name
Test status
Simulation time 7166744558 ps
CPU time 41.02 seconds
Started Mar 28 02:06:29 PM PDT 24
Finished Mar 28 02:07:10 PM PDT 24
Peak memory 222428 kb
Host smart-fe68979b-282a-4637-9246-06f0b21b0dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262289403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2262289403 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.1227901249
Short name T1069
Test name
Test status
Simulation time 5080230048 ps
CPU time 69.67 seconds
Started Mar 28 02:07:31 PM PDT 24
Finished Mar 28 02:08:41 PM PDT 24
Peak memory 226300 kb
Host smart-74de67fa-de15-4b12-ba0c-ecec80c0f850
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1227901249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1227901249 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.2718785384
Short name T663
Test name
Test status
Simulation time 267724569 ps
CPU time 4.25 seconds
Started Mar 28 02:07:07 PM PDT 24
Finished Mar 28 02:07:12 PM PDT 24
Peak memory 216128 kb
Host smart-9c242e71-bdd3-4583-9679-a87b9163e1ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718785384 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.2718785384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.3596644533
Short name T875
Test name
Test status
Simulation time 169935179 ps
CPU time 4.39 seconds
Started Mar 28 02:07:06 PM PDT 24
Finished Mar 28 02:07:11 PM PDT 24
Peak memory 216184 kb
Host smart-7536d7f8-3451-45c3-b00b-9318ebaa7e19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596644533 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.3596644533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.3808136041
Short name T891
Test name
Test status
Simulation time 88162146356 ps
CPU time 1958.21 seconds
Started Mar 28 02:07:08 PM PDT 24
Finished Mar 28 02:39:46 PM PDT 24
Peak memory 394552 kb
Host smart-27a781d3-3508-4106-bcdc-343a9121854a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3808136041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.3808136041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.3673473599
Short name T218
Test name
Test status
Simulation time 83881182007 ps
CPU time 1811.98 seconds
Started Mar 28 02:07:07 PM PDT 24
Finished Mar 28 02:37:20 PM PDT 24
Peak memory 387600 kb
Host smart-4589c533-f234-49c7-943b-86c69b3a4d7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3673473599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.3673473599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.3607282357
Short name T650
Test name
Test status
Simulation time 13851903234 ps
CPU time 1198.32 seconds
Started Mar 28 02:07:07 PM PDT 24
Finished Mar 28 02:27:06 PM PDT 24
Peak memory 340160 kb
Host smart-c4faa768-a1e9-48fd-a189-f15535ff5495
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3607282357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.3607282357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.3010982474
Short name T847
Test name
Test status
Simulation time 42622284918 ps
CPU time 916.35 seconds
Started Mar 28 02:07:08 PM PDT 24
Finished Mar 28 02:22:24 PM PDT 24
Peak memory 296524 kb
Host smart-a9222434-e95e-4fe1-81ea-053f89e56f57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3010982474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3010982474 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.901403567
Short name T880
Test name
Test status
Simulation time 256470260363 ps
CPU time 5022.42 seconds
Started Mar 28 02:07:07 PM PDT 24
Finished Mar 28 03:30:50 PM PDT 24
Peak memory 649268 kb
Host smart-90a9aa25-d296-4828-9bdd-8a9f10678f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=901403567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.901403567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.114875452
Short name T368
Test name
Test status
Simulation time 308626806919 ps
CPU time 4037.77 seconds
Started Mar 28 02:07:07 PM PDT 24
Finished Mar 28 03:14:25 PM PDT 24
Peak memory 542128 kb
Host smart-aa91f3b1-d990-4228-8632-7db1f2013345
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=114875452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.114875452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.874641631
Short name T687
Test name
Test status
Simulation time 94298877 ps
CPU time 0.74 seconds
Started Mar 28 02:08:21 PM PDT 24
Finished Mar 28 02:08:22 PM PDT 24
Peak memory 205564 kb
Host smart-8675a8fa-7f56-44b0-9296-25c4b37a96dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874641631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.874641631 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.1526707219
Short name T148
Test name
Test status
Simulation time 4122166674 ps
CPU time 175.18 seconds
Started Mar 28 02:08:00 PM PDT 24
Finished Mar 28 02:10:55 PM PDT 24
Peak memory 238656 kb
Host smart-e4779cd8-dd82-4e23-b2bf-532c34496097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526707219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1526707219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.3942679442
Short name T117
Test name
Test status
Simulation time 6974662300 ps
CPU time 628.39 seconds
Started Mar 28 02:07:34 PM PDT 24
Finished Mar 28 02:18:02 PM PDT 24
Peak memory 231424 kb
Host smart-8a0c5221-4552-4864-b21b-b13407e3ebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942679442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.3942679442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.1630642532
Short name T808
Test name
Test status
Simulation time 20272143133 ps
CPU time 172.31 seconds
Started Mar 28 02:07:57 PM PDT 24
Finished Mar 28 02:10:49 PM PDT 24
Peak memory 232740 kb
Host smart-5e53aebe-7850-429f-b130-9bd5fd07968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630642532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1630642532 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.794647281
Short name T639
Test name
Test status
Simulation time 4449403767 ps
CPU time 95.43 seconds
Started Mar 28 02:08:19 PM PDT 24
Finished Mar 28 02:09:54 PM PDT 24
Peak memory 240760 kb
Host smart-a8e45139-33a7-4fc5-9f2f-2abea2c91f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794647281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.794647281 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.4195342126
Short name T60
Test name
Test status
Simulation time 350700140 ps
CPU time 1.76 seconds
Started Mar 28 02:08:18 PM PDT 24
Finished Mar 28 02:08:20 PM PDT 24
Peak memory 207452 kb
Host smart-38c3888a-153f-44bf-a10a-22b9e4bf6189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195342126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.4195342126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.3592029847
Short name T1034
Test name
Test status
Simulation time 38334826 ps
CPU time 1.3 seconds
Started Mar 28 02:08:18 PM PDT 24
Finished Mar 28 02:08:20 PM PDT 24
Peak memory 215976 kb
Host smart-06a14ec6-73b4-4110-b7f1-07caa75a5258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592029847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3592029847 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.1190856133
Short name T839
Test name
Test status
Simulation time 40265228935 ps
CPU time 832.1 seconds
Started Mar 28 02:07:32 PM PDT 24
Finished Mar 28 02:21:25 PM PDT 24
Peak memory 293656 kb
Host smart-69df084c-b151-451e-80e5-d461c00dfc85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190856133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.1190856133 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.1560635708
Short name T927
Test name
Test status
Simulation time 1936296702 ps
CPU time 34.9 seconds
Started Mar 28 02:07:33 PM PDT 24
Finished Mar 28 02:08:08 PM PDT 24
Peak memory 223424 kb
Host smart-c015066e-61a9-437c-b845-05be916a7e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560635708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1560635708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.118412077
Short name T904
Test name
Test status
Simulation time 3477952822 ps
CPU time 49.89 seconds
Started Mar 28 02:07:33 PM PDT 24
Finished Mar 28 02:08:23 PM PDT 24
Peak memory 220028 kb
Host smart-93d2a65e-3edb-4084-a65a-aa887333cf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118412077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.118412077 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.1309241866
Short name T347
Test name
Test status
Simulation time 20442525344 ps
CPU time 428.53 seconds
Started Mar 28 02:08:18 PM PDT 24
Finished Mar 28 02:15:27 PM PDT 24
Peak memory 271840 kb
Host smart-ec85230b-e116-4240-afa7-aea3fd2d7fe9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1309241866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1309241866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.1855551272
Short name T575
Test name
Test status
Simulation time 1556933666 ps
CPU time 5.21 seconds
Started Mar 28 02:07:58 PM PDT 24
Finished Mar 28 02:08:03 PM PDT 24
Peak memory 216132 kb
Host smart-862c67c4-2300-4819-9094-25a15ac728b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855551272 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.1855551272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2025833114
Short name T61
Test name
Test status
Simulation time 440843239 ps
CPU time 5.35 seconds
Started Mar 28 02:07:56 PM PDT 24
Finished Mar 28 02:08:02 PM PDT 24
Peak memory 216140 kb
Host smart-cc81452c-9a0e-4c1c-b70d-065637fd1e50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025833114 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2025833114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.1821540855
Short name T395
Test name
Test status
Simulation time 76310895490 ps
CPU time 1800.55 seconds
Started Mar 28 02:07:35 PM PDT 24
Finished Mar 28 02:37:36 PM PDT 24
Peak memory 397208 kb
Host smart-d4beb368-1dfa-4272-9e62-ecdc999c096e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1821540855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.1821540855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.358256027
Short name T292
Test name
Test status
Simulation time 61434526045 ps
CPU time 1836.41 seconds
Started Mar 28 02:07:34 PM PDT 24
Finished Mar 28 02:38:12 PM PDT 24
Peak memory 375896 kb
Host smart-86747cd4-7091-4ccd-854a-ec84d82636a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=358256027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.358256027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.1282571675
Short name T401
Test name
Test status
Simulation time 288366660538 ps
CPU time 1462.48 seconds
Started Mar 28 02:07:33 PM PDT 24
Finished Mar 28 02:31:56 PM PDT 24
Peak memory 331752 kb
Host smart-a319d6e3-0440-47ce-8225-14339d5f804e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1282571675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.1282571675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.114132484
Short name T1062
Test name
Test status
Simulation time 36224207370 ps
CPU time 1046.44 seconds
Started Mar 28 02:07:32 PM PDT 24
Finished Mar 28 02:24:59 PM PDT 24
Peak memory 302804 kb
Host smart-833f79ca-1f4f-4fcc-b55c-8c534af8e63b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=114132484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.114132484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.1030306391
Short name T888
Test name
Test status
Simulation time 452325310850 ps
CPU time 5444.06 seconds
Started Mar 28 02:07:36 PM PDT 24
Finished Mar 28 03:38:25 PM PDT 24
Peak memory 654808 kb
Host smart-70db8a52-8482-460d-abf0-46307834d592
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1030306391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.1030306391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.834010347
Short name T251
Test name
Test status
Simulation time 89022107052 ps
CPU time 3194 seconds
Started Mar 28 02:07:58 PM PDT 24
Finished Mar 28 03:01:12 PM PDT 24
Peak memory 568548 kb
Host smart-c65be67f-2b10-4376-bea6-1211613f5266
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=834010347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.834010347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.2049843208
Short name T455
Test name
Test status
Simulation time 45047282 ps
CPU time 0.82 seconds
Started Mar 28 02:09:35 PM PDT 24
Finished Mar 28 02:09:35 PM PDT 24
Peak memory 205544 kb
Host smart-5232880d-96bd-4158-937c-86f3bc31d2ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049843208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2049843208 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.749272893
Short name T605
Test name
Test status
Simulation time 11425056867 ps
CPU time 246.07 seconds
Started Mar 28 02:09:02 PM PDT 24
Finished Mar 28 02:13:08 PM PDT 24
Peak memory 243656 kb
Host smart-e480d3da-ae62-4d6e-b7b4-1dd8f79b08e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749272893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.749272893 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.3892517968
Short name T971
Test name
Test status
Simulation time 62911480338 ps
CPU time 658.39 seconds
Started Mar 28 02:08:22 PM PDT 24
Finished Mar 28 02:19:21 PM PDT 24
Peak memory 231912 kb
Host smart-7b36a30a-31bc-40dd-95a8-231bb748c7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892517968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3892517968 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.879282471
Short name T572
Test name
Test status
Simulation time 9609254666 ps
CPU time 245.53 seconds
Started Mar 28 02:09:00 PM PDT 24
Finished Mar 28 02:13:06 PM PDT 24
Peak memory 244444 kb
Host smart-2a7a0144-4a12-46fb-8bc9-205c273ab3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879282471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.879282471 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.2216843398
Short name T691
Test name
Test status
Simulation time 2091951903 ps
CPU time 111.12 seconds
Started Mar 28 02:09:00 PM PDT 24
Finished Mar 28 02:10:51 PM PDT 24
Peak memory 238628 kb
Host smart-d6f7f733-d4d5-4673-8586-c0b87e4148eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216843398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2216843398 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.2319387748
Short name T414
Test name
Test status
Simulation time 3383731133 ps
CPU time 4.4 seconds
Started Mar 28 02:08:59 PM PDT 24
Finished Mar 28 02:09:03 PM PDT 24
Peak memory 207712 kb
Host smart-1c3ac0ad-fae1-4aed-9203-ad28cf373f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319387748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2319387748 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.1228179211
Short name T448
Test name
Test status
Simulation time 55413718 ps
CPU time 1.12 seconds
Started Mar 28 02:09:34 PM PDT 24
Finished Mar 28 02:09:35 PM PDT 24
Peak memory 216000 kb
Host smart-1485b0b6-1002-4b55-86eb-1853c6eeaa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228179211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1228179211 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.4120324511
Short name T1033
Test name
Test status
Simulation time 72678491345 ps
CPU time 1637.53 seconds
Started Mar 28 02:08:18 PM PDT 24
Finished Mar 28 02:35:36 PM PDT 24
Peak memory 375832 kb
Host smart-6930d9c8-5c26-46e1-afc7-82ec755c7cf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120324511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.4120324511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_smoke.3257503237
Short name T852
Test name
Test status
Simulation time 705468665 ps
CPU time 19.54 seconds
Started Mar 28 02:08:24 PM PDT 24
Finished Mar 28 02:08:44 PM PDT 24
Peak memory 219560 kb
Host smart-438f47d9-d06d-4932-a6e9-ddfaf27a5e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257503237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3257503237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.3169021750
Short name T276
Test name
Test status
Simulation time 31816108488 ps
CPU time 1361.57 seconds
Started Mar 28 02:09:34 PM PDT 24
Finished Mar 28 02:32:16 PM PDT 24
Peak memory 368624 kb
Host smart-a830c2ca-a6de-4b61-8035-8a808cbdb1d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3169021750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3169021750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.352926296
Short name T970
Test name
Test status
Simulation time 126872612 ps
CPU time 4.3 seconds
Started Mar 28 02:08:59 PM PDT 24
Finished Mar 28 02:09:04 PM PDT 24
Peak memory 216128 kb
Host smart-2a5f1348-1603-43ce-b624-6299afb4413c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352926296 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.kmac_test_vectors_kmac.352926296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1539067391
Short name T297
Test name
Test status
Simulation time 226183715 ps
CPU time 4.43 seconds
Started Mar 28 02:09:00 PM PDT 24
Finished Mar 28 02:09:05 PM PDT 24
Peak memory 216016 kb
Host smart-10629048-5087-4a83-9031-60cf4b88cb61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539067391 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1539067391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.1525014400
Short name T616
Test name
Test status
Simulation time 810044908626 ps
CPU time 1870.79 seconds
Started Mar 28 02:08:40 PM PDT 24
Finished Mar 28 02:39:51 PM PDT 24
Peak memory 392152 kb
Host smart-1e431926-b2b4-448e-9c57-054467bda115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1525014400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.1525014400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.1053861668
Short name T288
Test name
Test status
Simulation time 18306481319 ps
CPU time 1587.64 seconds
Started Mar 28 02:08:38 PM PDT 24
Finished Mar 28 02:35:06 PM PDT 24
Peak memory 370460 kb
Host smart-fa0d3fc8-776e-4e88-bee7-6d3bf3d57b01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1053861668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.1053861668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.3146692110
Short name T638
Test name
Test status
Simulation time 64014637872 ps
CPU time 1252.51 seconds
Started Mar 28 02:08:39 PM PDT 24
Finished Mar 28 02:29:32 PM PDT 24
Peak memory 337504 kb
Host smart-7f331a47-bf7f-4d40-901a-bda6bebfc9d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3146692110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.3146692110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.3139682245
Short name T564
Test name
Test status
Simulation time 9526998608 ps
CPU time 787.66 seconds
Started Mar 28 02:08:39 PM PDT 24
Finished Mar 28 02:21:47 PM PDT 24
Peak memory 292116 kb
Host smart-22549a68-2d9e-4ec6-9098-fc4450330a56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3139682245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.3139682245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.529171695
Short name T861
Test name
Test status
Simulation time 1064800237549 ps
CPU time 5086.21 seconds
Started Mar 28 02:08:39 PM PDT 24
Finished Mar 28 03:33:25 PM PDT 24
Peak memory 645556 kb
Host smart-ea3d9f9d-02ff-458b-ab1a-e6500376d890
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=529171695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.529171695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.3116323074
Short name T212
Test name
Test status
Simulation time 863179404308 ps
CPU time 4490.11 seconds
Started Mar 28 02:08:59 PM PDT 24
Finished Mar 28 03:23:50 PM PDT 24
Peak memory 558332 kb
Host smart-fa969b24-4635-4d26-8354-102c6a606e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3116323074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3116323074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.660247865
Short name T559
Test name
Test status
Simulation time 43941433 ps
CPU time 0.75 seconds
Started Mar 28 02:10:22 PM PDT 24
Finished Mar 28 02:10:22 PM PDT 24
Peak memory 205576 kb
Host smart-ffa4cf95-ee19-4c9c-bd8d-cc98dc12f6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660247865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.660247865 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.1102854731
Short name T416
Test name
Test status
Simulation time 2173465233 ps
CPU time 129.82 seconds
Started Mar 28 02:10:03 PM PDT 24
Finished Mar 28 02:12:13 PM PDT 24
Peak memory 233364 kb
Host smart-cc6b342c-d057-41ae-93bf-3c12b006ca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102854731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1102854731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.319557633
Short name T589
Test name
Test status
Simulation time 11146488257 ps
CPU time 138.73 seconds
Started Mar 28 02:10:01 PM PDT 24
Finished Mar 28 02:12:20 PM PDT 24
Peak memory 232312 kb
Host smart-a75a7ba5-f7dc-4fd5-95d7-68c96ae9a136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319557633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.319557633 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.1790234147
Short name T404
Test name
Test status
Simulation time 12542577512 ps
CPU time 179.02 seconds
Started Mar 28 02:10:02 PM PDT 24
Finished Mar 28 02:13:01 PM PDT 24
Peak memory 248956 kb
Host smart-9249ead2-ab48-4796-8c68-708f3c38414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790234147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1790234147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.3923086323
Short name T330
Test name
Test status
Simulation time 678307686 ps
CPU time 3.83 seconds
Started Mar 28 02:10:02 PM PDT 24
Finished Mar 28 02:10:06 PM PDT 24
Peak memory 207732 kb
Host smart-a3afe5bd-1e81-4d06-a5da-95759d8e7d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923086323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3923086323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.1511087797
Short name T1016
Test name
Test status
Simulation time 38952660 ps
CPU time 1.44 seconds
Started Mar 28 02:10:01 PM PDT 24
Finished Mar 28 02:10:03 PM PDT 24
Peak memory 218224 kb
Host smart-425cf5ab-f6d7-4598-b627-b3501158da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511087797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1511087797 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.396601027
Short name T1058
Test name
Test status
Simulation time 45877228695 ps
CPU time 2026.12 seconds
Started Mar 28 02:09:33 PM PDT 24
Finished Mar 28 02:43:19 PM PDT 24
Peak memory 443868 kb
Host smart-708bb5ea-87c5-4046-978f-8ea07f2ea326
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396601027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_an
d_output.396601027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.3011569889
Short name T386
Test name
Test status
Simulation time 18842172246 ps
CPU time 383.27 seconds
Started Mar 28 02:09:34 PM PDT 24
Finished Mar 28 02:15:58 PM PDT 24
Peak memory 246108 kb
Host smart-5dd3cda7-b54e-4ccc-a726-92875e0a913e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011569889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3011569889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.1127648148
Short name T346
Test name
Test status
Simulation time 3289907066 ps
CPU time 46.92 seconds
Started Mar 28 02:09:35 PM PDT 24
Finished Mar 28 02:10:22 PM PDT 24
Peak memory 219924 kb
Host smart-d713bcbe-3e93-49ec-a61f-5a0c98b81889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127648148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1127648148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.844363957
Short name T1075
Test name
Test status
Simulation time 2754064826 ps
CPU time 59.57 seconds
Started Mar 28 02:10:01 PM PDT 24
Finished Mar 28 02:11:01 PM PDT 24
Peak memory 248916 kb
Host smart-3b51e32c-36a4-470f-b607-c954c4f40e7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=844363957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.844363957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_stress_all_with_rand_reset.4294074512
Short name T1044
Test name
Test status
Simulation time 119573007622 ps
CPU time 1296.65 seconds
Started Mar 28 02:10:21 PM PDT 24
Finished Mar 28 02:31:58 PM PDT 24
Peak memory 355804 kb
Host smart-d1fb40c0-c0e6-4fb0-b84b-d6cc21111611
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294074512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all_with_rand_reset.4294074512 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.2663398515
Short name T739
Test name
Test status
Simulation time 65175273 ps
CPU time 3.92 seconds
Started Mar 28 02:10:03 PM PDT 24
Finished Mar 28 02:10:07 PM PDT 24
Peak memory 216112 kb
Host smart-8a06d8e6-85b1-4e79-b69f-b5667326ff63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663398515 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.2663398515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.3873937906
Short name T641
Test name
Test status
Simulation time 2766032077 ps
CPU time 5.12 seconds
Started Mar 28 02:10:02 PM PDT 24
Finished Mar 28 02:10:07 PM PDT 24
Peak memory 216164 kb
Host smart-557d3cc8-bbeb-49b8-96df-0e01392bad2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873937906 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.3873937906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.3775514354
Short name T331
Test name
Test status
Simulation time 18845706741 ps
CPU time 1482.11 seconds
Started Mar 28 02:10:01 PM PDT 24
Finished Mar 28 02:34:44 PM PDT 24
Peak memory 392664 kb
Host smart-54d59dec-632b-4a2a-9647-c4da274ddc3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3775514354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.3775514354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.2091540912
Short name T1024
Test name
Test status
Simulation time 60321953644 ps
CPU time 1606.66 seconds
Started Mar 28 02:10:04 PM PDT 24
Finished Mar 28 02:36:51 PM PDT 24
Peak memory 369288 kb
Host smart-9e985673-c21a-4cdf-bbb5-9b61183e16ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2091540912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.2091540912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.2681478159
Short name T601
Test name
Test status
Simulation time 74126902413 ps
CPU time 1306.82 seconds
Started Mar 28 02:10:02 PM PDT 24
Finished Mar 28 02:31:50 PM PDT 24
Peak memory 329940 kb
Host smart-7fb684e9-123a-4767-a344-9ad5306bb7a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2681478159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.2681478159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.1311662406
Short name T427
Test name
Test status
Simulation time 19252045934 ps
CPU time 826.76 seconds
Started Mar 28 02:10:01 PM PDT 24
Finished Mar 28 02:23:48 PM PDT 24
Peak memory 294300 kb
Host smart-38571e7d-6361-4cc3-889f-bee4186f4734
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1311662406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1311662406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.875562824
Short name T627
Test name
Test status
Simulation time 265418566798 ps
CPU time 5160.91 seconds
Started Mar 28 02:10:00 PM PDT 24
Finished Mar 28 03:36:02 PM PDT 24
Peak memory 643112 kb
Host smart-d77485ab-556b-4393-b03a-3587f64ccf01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=875562824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.875562824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.1564249002
Short name T1008
Test name
Test status
Simulation time 90831016177 ps
CPU time 3286.91 seconds
Started Mar 28 02:10:01 PM PDT 24
Finished Mar 28 03:04:48 PM PDT 24
Peak memory 567332 kb
Host smart-7defe067-15bb-490e-9877-9cfd6db95373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1564249002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.1564249002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.3105789417
Short name T366
Test name
Test status
Simulation time 17624815 ps
CPU time 0.79 seconds
Started Mar 28 02:11:13 PM PDT 24
Finished Mar 28 02:11:13 PM PDT 24
Peak memory 205592 kb
Host smart-94b099f8-c64c-4a8c-ad37-fa4fde018cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105789417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3105789417 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.3543656178
Short name T123
Test name
Test status
Simulation time 16632525155 ps
CPU time 251.27 seconds
Started Mar 28 02:10:45 PM PDT 24
Finished Mar 28 02:14:56 PM PDT 24
Peak memory 243820 kb
Host smart-337278d5-abf1-4724-ba8e-b61d656a9d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543656178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3543656178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.332664713
Short name T914
Test name
Test status
Simulation time 13065338069 ps
CPU time 94.86 seconds
Started Mar 28 02:10:22 PM PDT 24
Finished Mar 28 02:11:57 PM PDT 24
Peak memory 231200 kb
Host smart-049c94a8-1892-4d7f-a2e0-b990cec42691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332664713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.332664713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.3729227031
Short name T1005
Test name
Test status
Simulation time 20332725850 ps
CPU time 220.36 seconds
Started Mar 28 02:11:11 PM PDT 24
Finished Mar 28 02:14:52 PM PDT 24
Peak memory 238436 kb
Host smart-b0bafa33-23b0-4077-96a5-3e75c98a17f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729227031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3729227031 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.3669301616
Short name T571
Test name
Test status
Simulation time 26989320130 ps
CPU time 212.49 seconds
Started Mar 28 02:11:12 PM PDT 24
Finished Mar 28 02:14:45 PM PDT 24
Peak memory 248808 kb
Host smart-05fd4916-4359-4326-9965-3672355836af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669301616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3669301616 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.977961351
Short name T428
Test name
Test status
Simulation time 35175930 ps
CPU time 0.88 seconds
Started Mar 28 02:11:11 PM PDT 24
Finished Mar 28 02:11:12 PM PDT 24
Peak memory 205756 kb
Host smart-200bd473-a071-4543-bf7d-bf0deb74b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977961351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.977961351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.797847997
Short name T384
Test name
Test status
Simulation time 175888977776 ps
CPU time 1408.18 seconds
Started Mar 28 02:10:19 PM PDT 24
Finished Mar 28 02:33:49 PM PDT 24
Peak memory 345812 kb
Host smart-a254b7e4-8d3b-48ae-b638-cd0333c12a5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797847997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_an
d_output.797847997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.1587754505
Short name T545
Test name
Test status
Simulation time 3153986018 ps
CPU time 239.77 seconds
Started Mar 28 02:10:22 PM PDT 24
Finished Mar 28 02:14:22 PM PDT 24
Peak memory 240740 kb
Host smart-88143d43-2541-4320-abbc-91a91edcbf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587754505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1587754505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.2328033696
Short name T854
Test name
Test status
Simulation time 2589435737 ps
CPU time 53.85 seconds
Started Mar 28 02:10:23 PM PDT 24
Finished Mar 28 02:11:17 PM PDT 24
Peak memory 217532 kb
Host smart-a194a772-17d5-474c-9e60-07ddd9953010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328033696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2328033696 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.520633695
Short name T930
Test name
Test status
Simulation time 2934136897 ps
CPU time 79.78 seconds
Started Mar 28 02:11:10 PM PDT 24
Finished Mar 28 02:12:30 PM PDT 24
Peak memory 235128 kb
Host smart-76838832-b78c-46c6-8a07-c940d5f468cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=520633695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.520633695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.866435614
Short name T674
Test name
Test status
Simulation time 225233668 ps
CPU time 5.17 seconds
Started Mar 28 02:10:42 PM PDT 24
Finished Mar 28 02:10:48 PM PDT 24
Peak memory 216112 kb
Host smart-d9776eca-c50d-440d-b906-7bcb9b95c4b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866435614 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.kmac_test_vectors_kmac.866435614 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3371398378
Short name T467
Test name
Test status
Simulation time 1485024932 ps
CPU time 5.05 seconds
Started Mar 28 02:10:43 PM PDT 24
Finished Mar 28 02:10:48 PM PDT 24
Peak memory 216116 kb
Host smart-ce8e9d5d-079d-43af-8153-9d520dc403fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371398378 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3371398378 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.3690166264
Short name T948
Test name
Test status
Simulation time 25318793023 ps
CPU time 1574.94 seconds
Started Mar 28 02:10:22 PM PDT 24
Finished Mar 28 02:36:38 PM PDT 24
Peak memory 394476 kb
Host smart-af6452ed-71c4-4592-93f2-84568357fa22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3690166264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.3690166264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.932335479
Short name T629
Test name
Test status
Simulation time 239353011268 ps
CPU time 1891.71 seconds
Started Mar 28 02:10:25 PM PDT 24
Finished Mar 28 02:41:57 PM PDT 24
Peak memory 388252 kb
Host smart-95eada11-61d7-4fee-9e69-1d6020f56af1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=932335479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.932335479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.3680845242
Short name T628
Test name
Test status
Simulation time 140944701873 ps
CPU time 1357.34 seconds
Started Mar 28 02:10:22 PM PDT 24
Finished Mar 28 02:32:59 PM PDT 24
Peak memory 331044 kb
Host smart-e47aa73c-ce9b-462b-bb02-e8b5fcf5deed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3680845242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.3680845242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.699513759
Short name T521
Test name
Test status
Simulation time 41789386509 ps
CPU time 872.71 seconds
Started Mar 28 02:10:23 PM PDT 24
Finished Mar 28 02:24:56 PM PDT 24
Peak memory 292572 kb
Host smart-d5a81d6c-c600-4516-9c01-cfb99889e31b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=699513759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.699513759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.889223013
Short name T307
Test name
Test status
Simulation time 218889864078 ps
CPU time 4597.75 seconds
Started Mar 28 02:10:44 PM PDT 24
Finished Mar 28 03:27:23 PM PDT 24
Peak memory 633176 kb
Host smart-004ddba6-2aff-4fd5-8461-9dc5485f7775
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=889223013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.889223013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.2558447265
Short name T280
Test name
Test status
Simulation time 675186952031 ps
CPU time 4248.65 seconds
Started Mar 28 02:10:44 PM PDT 24
Finished Mar 28 03:21:33 PM PDT 24
Peak memory 565632 kb
Host smart-bd70a2a2-5e77-4c5c-9017-65c59d76e8c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2558447265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.2558447265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.1139374453
Short name T240
Test name
Test status
Simulation time 15725828 ps
CPU time 0.77 seconds
Started Mar 28 02:12:34 PM PDT 24
Finished Mar 28 02:12:35 PM PDT 24
Peak memory 205592 kb
Host smart-0ea92359-90b4-48c2-a15b-5e81f60092b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139374453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1139374453 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.3372425585
Short name T1057
Test name
Test status
Simulation time 10207797365 ps
CPU time 183.15 seconds
Started Mar 28 02:12:32 PM PDT 24
Finished Mar 28 02:15:35 PM PDT 24
Peak memory 236148 kb
Host smart-f112a03d-f524-4b38-9caf-3afcaa8a340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372425585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3372425585 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.3763038583
Short name T1019
Test name
Test status
Simulation time 34302205795 ps
CPU time 189.62 seconds
Started Mar 28 02:11:11 PM PDT 24
Finished Mar 28 02:14:21 PM PDT 24
Peak memory 224016 kb
Host smart-b3c6bdc2-438d-4ed0-954c-dfa8a3614cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763038583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.3763038583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.1883824072
Short name T584
Test name
Test status
Simulation time 154186076393 ps
CPU time 303.41 seconds
Started Mar 28 02:12:35 PM PDT 24
Finished Mar 28 02:17:38 PM PDT 24
Peak memory 240428 kb
Host smart-f4bf68ee-920e-4e98-9b39-34ae2aa5da8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883824072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1883824072 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.1687010541
Short name T682
Test name
Test status
Simulation time 8706555400 ps
CPU time 235.58 seconds
Started Mar 28 02:12:34 PM PDT 24
Finished Mar 28 02:16:30 PM PDT 24
Peak memory 248932 kb
Host smart-e573b6d8-2eeb-4e3f-a2f1-a5cc16e8d7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687010541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1687010541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.271741418
Short name T507
Test name
Test status
Simulation time 273421343 ps
CPU time 1.24 seconds
Started Mar 28 02:12:34 PM PDT 24
Finished Mar 28 02:12:35 PM PDT 24
Peak memory 215992 kb
Host smart-0a565432-96b8-4cc9-ac1c-9281540a2fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271741418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.271741418 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.4228613987
Short name T413
Test name
Test status
Simulation time 67429344723 ps
CPU time 2054.18 seconds
Started Mar 28 02:11:13 PM PDT 24
Finished Mar 28 02:45:27 PM PDT 24
Peak memory 412572 kb
Host smart-61f82585-8465-4c27-9862-d8f7ea359f91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228613987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.4228613987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.2439816800
Short name T599
Test name
Test status
Simulation time 14111656489 ps
CPU time 276.36 seconds
Started Mar 28 02:11:11 PM PDT 24
Finished Mar 28 02:15:48 PM PDT 24
Peak memory 243584 kb
Host smart-55165193-3086-4476-8745-b2d3e7dbc236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439816800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2439816800 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.313617673
Short name T975
Test name
Test status
Simulation time 4372523880 ps
CPU time 21.81 seconds
Started Mar 28 02:11:13 PM PDT 24
Finished Mar 28 02:11:35 PM PDT 24
Peak memory 217496 kb
Host smart-ab10ebb4-99cc-4b69-9d28-3afe8db526aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313617673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.313617673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.1978745182
Short name T319
Test name
Test status
Simulation time 59983370691 ps
CPU time 1649.6 seconds
Started Mar 28 02:12:33 PM PDT 24
Finished Mar 28 02:40:02 PM PDT 24
Peak memory 434068 kb
Host smart-7e089df8-b3f5-49a9-a981-6120ff19eb52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1978745182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1978745182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.3548827374
Short name T1041
Test name
Test status
Simulation time 250426439 ps
CPU time 3.78 seconds
Started Mar 28 02:11:57 PM PDT 24
Finished Mar 28 02:12:01 PM PDT 24
Peak memory 216060 kb
Host smart-26fcd132-abb1-4aab-8c9e-548121e7003f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548827374 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.3548827374 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2023189242
Short name T826
Test name
Test status
Simulation time 1054963793 ps
CPU time 5.41 seconds
Started Mar 28 02:11:56 PM PDT 24
Finished Mar 28 02:12:01 PM PDT 24
Peak memory 216120 kb
Host smart-ed86a373-85e5-4304-b392-4ebad628859d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023189242 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2023189242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.1103503426
Short name T385
Test name
Test status
Simulation time 36626153424 ps
CPU time 1632.79 seconds
Started Mar 28 02:11:56 PM PDT 24
Finished Mar 28 02:39:09 PM PDT 24
Peak memory 375068 kb
Host smart-8729fd6d-75d0-48e9-89d4-c71ae65b8164
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1103503426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.1103503426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.3438498854
Short name T506
Test name
Test status
Simulation time 159800951688 ps
CPU time 1455.04 seconds
Started Mar 28 02:11:56 PM PDT 24
Finished Mar 28 02:36:11 PM PDT 24
Peak memory 371528 kb
Host smart-0284842f-b332-4b2c-9b18-806bdd1ccf96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3438498854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.3438498854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.2434547257
Short name T692
Test name
Test status
Simulation time 13907229289 ps
CPU time 1086.74 seconds
Started Mar 28 02:11:55 PM PDT 24
Finished Mar 28 02:30:02 PM PDT 24
Peak memory 329004 kb
Host smart-85ef50f0-2f3f-49db-b852-fdff1ba7203f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2434547257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2434547257 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.1797820358
Short name T424
Test name
Test status
Simulation time 66852299489 ps
CPU time 947.94 seconds
Started Mar 28 02:11:57 PM PDT 24
Finished Mar 28 02:27:46 PM PDT 24
Peak memory 291912 kb
Host smart-98c73b8e-088f-43ae-ae6c-1d5fd0fd1684
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1797820358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.1797820358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.935587415
Short name T536
Test name
Test status
Simulation time 958497007869 ps
CPU time 5070.91 seconds
Started Mar 28 02:11:56 PM PDT 24
Finished Mar 28 03:36:28 PM PDT 24
Peak memory 654708 kb
Host smart-5d19fec3-ecbf-4320-be06-762455a39bd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=935587415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.935587415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2126334522
Short name T780
Test name
Test status
Simulation time 224556751982 ps
CPU time 3508.09 seconds
Started Mar 28 02:11:59 PM PDT 24
Finished Mar 28 03:10:30 PM PDT 24
Peak memory 548504 kb
Host smart-9d08d375-ebb6-4043-9af4-4b5485442635
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2126334522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2126334522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.1810045728
Short name T435
Test name
Test status
Simulation time 71614899 ps
CPU time 0.84 seconds
Started Mar 28 02:13:31 PM PDT 24
Finished Mar 28 02:13:33 PM PDT 24
Peak memory 205444 kb
Host smart-8c732e1b-7b1d-4d12-889f-dd7e891746d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810045728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1810045728 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.4232259572
Short name T488
Test name
Test status
Simulation time 47353100454 ps
CPU time 331.95 seconds
Started Mar 28 02:13:09 PM PDT 24
Finished Mar 28 02:18:41 PM PDT 24
Peak memory 247020 kb
Host smart-2aed175a-199a-4cb8-83a9-d441f87c87d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232259572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.4232259572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.654059803
Short name T128
Test name
Test status
Simulation time 17195415179 ps
CPU time 462.65 seconds
Started Mar 28 02:13:05 PM PDT 24
Finished Mar 28 02:20:48 PM PDT 24
Peak memory 238384 kb
Host smart-62ace393-1d98-4168-9ade-0ae0583062d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654059803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.654059803 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.4102981255
Short name T1026
Test name
Test status
Simulation time 61018526994 ps
CPU time 296.73 seconds
Started Mar 28 02:13:08 PM PDT 24
Finished Mar 28 02:18:05 PM PDT 24
Peak memory 242968 kb
Host smart-bda3bad0-b856-476f-81c4-12bbcbb680d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102981255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.4102981255 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.2222781402
Short name T152
Test name
Test status
Simulation time 6701757890 ps
CPU time 258.44 seconds
Started Mar 28 02:13:31 PM PDT 24
Finished Mar 28 02:17:50 PM PDT 24
Peak memory 253568 kb
Host smart-366b2c5e-1010-458b-be6b-4987614ac476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222781402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2222781402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.280123271
Short name T294
Test name
Test status
Simulation time 604744634 ps
CPU time 2.08 seconds
Started Mar 28 02:13:32 PM PDT 24
Finished Mar 28 02:13:35 PM PDT 24
Peak memory 207640 kb
Host smart-ea9eb04f-907b-4ca1-8d01-afd746c25573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280123271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.280123271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.551409371
Short name T317
Test name
Test status
Simulation time 41527248 ps
CPU time 1.33 seconds
Started Mar 28 02:13:32 PM PDT 24
Finished Mar 28 02:13:34 PM PDT 24
Peak memory 215988 kb
Host smart-2aa0b20a-2be9-4645-b89e-5579f1df4856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551409371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.551409371 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.3235152411
Short name T538
Test name
Test status
Simulation time 44480239669 ps
CPU time 620.55 seconds
Started Mar 28 02:12:31 PM PDT 24
Finished Mar 28 02:22:52 PM PDT 24
Peak memory 282512 kb
Host smart-ff5a39e7-841b-4288-80bf-7efe5a3c4a58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235152411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.3235152411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.772411727
Short name T756
Test name
Test status
Simulation time 10366444055 ps
CPU time 161 seconds
Started Mar 28 02:12:36 PM PDT 24
Finished Mar 28 02:15:17 PM PDT 24
Peak memory 237624 kb
Host smart-d949fa70-d5ba-47e8-b052-91162a3bfc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772411727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.772411727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.1849655430
Short name T452
Test name
Test status
Simulation time 738731271 ps
CPU time 37.15 seconds
Started Mar 28 02:12:33 PM PDT 24
Finished Mar 28 02:13:10 PM PDT 24
Peak memory 220320 kb
Host smart-33593023-1eb6-4e93-a3eb-cf29fcd220ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849655430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1849655430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.3856570458
Short name T844
Test name
Test status
Simulation time 13062571123 ps
CPU time 767.63 seconds
Started Mar 28 02:13:32 PM PDT 24
Finished Mar 28 02:26:20 PM PDT 24
Peak memory 337752 kb
Host smart-9156b6da-6487-44d4-907c-6e69ccba3b62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3856570458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3856570458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_stress_all_with_rand_reset.3015371179
Short name T45
Test name
Test status
Simulation time 971108513810 ps
CPU time 1645.25 seconds
Started Mar 28 02:13:40 PM PDT 24
Finished Mar 28 02:41:06 PM PDT 24
Peak memory 322200 kb
Host smart-53c27e9e-bd0b-4e06-9665-5b185f98aafe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015371179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all_with_rand_reset.3015371179 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.4053289002
Short name T825
Test name
Test status
Simulation time 170413949 ps
CPU time 4.86 seconds
Started Mar 28 02:13:07 PM PDT 24
Finished Mar 28 02:13:12 PM PDT 24
Peak memory 216208 kb
Host smart-cfecaf30-74d8-4f3f-985f-f0c58fba2d79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053289002 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.4053289002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.477394917
Short name T320
Test name
Test status
Simulation time 79747073 ps
CPU time 4.12 seconds
Started Mar 28 02:13:05 PM PDT 24
Finished Mar 28 02:13:09 PM PDT 24
Peak memory 216116 kb
Host smart-9198b459-6a84-4136-8fbd-07302959785b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477394917 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.kmac_test_vectors_kmac_xof.477394917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.4217235720
Short name T514
Test name
Test status
Simulation time 22958438729 ps
CPU time 1646.19 seconds
Started Mar 28 02:13:08 PM PDT 24
Finished Mar 28 02:40:34 PM PDT 24
Peak memory 387620 kb
Host smart-6cab9aa1-b290-4430-bfa9-4bc6f244ab7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4217235720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.4217235720 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.1349533920
Short name T999
Test name
Test status
Simulation time 93338803621 ps
CPU time 1603.23 seconds
Started Mar 28 02:13:05 PM PDT 24
Finished Mar 28 02:39:48 PM PDT 24
Peak memory 366412 kb
Host smart-919e63a0-2a95-4d6f-826d-1495b02e739d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1349533920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.1349533920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.782309897
Short name T1087
Test name
Test status
Simulation time 28155345287 ps
CPU time 1168.31 seconds
Started Mar 28 02:13:05 PM PDT 24
Finished Mar 28 02:32:33 PM PDT 24
Peak memory 332636 kb
Host smart-c2d9a5b9-13de-45dc-a207-dd8ff29f9168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=782309897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.782309897 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.176010736
Short name T726
Test name
Test status
Simulation time 39971826506 ps
CPU time 835.75 seconds
Started Mar 28 02:13:06 PM PDT 24
Finished Mar 28 02:27:02 PM PDT 24
Peak memory 296820 kb
Host smart-a559904e-f00d-4fbf-a512-d308455d7127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=176010736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.176010736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.3887663288
Short name T849
Test name
Test status
Simulation time 850673933866 ps
CPU time 4802.99 seconds
Started Mar 28 02:13:05 PM PDT 24
Finished Mar 28 03:33:09 PM PDT 24
Peak memory 640492 kb
Host smart-5262ee95-f080-42de-a501-8ac156b74c18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3887663288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3887663288 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.1671476473
Short name T446
Test name
Test status
Simulation time 198956175063 ps
CPU time 4094.07 seconds
Started Mar 28 02:13:05 PM PDT 24
Finished Mar 28 03:21:20 PM PDT 24
Peak memory 561456 kb
Host smart-6babe866-b03c-4c41-a9cf-399c8c4b38fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1671476473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.1671476473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.1428977369
Short name T653
Test name
Test status
Simulation time 17560201 ps
CPU time 0.81 seconds
Started Mar 28 02:15:24 PM PDT 24
Finished Mar 28 02:15:25 PM PDT 24
Peak memory 205572 kb
Host smart-2202ff01-020a-4efa-ab7c-9f353060d462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428977369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1428977369 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.4227523421
Short name T590
Test name
Test status
Simulation time 9800340102 ps
CPU time 257.44 seconds
Started Mar 28 02:14:55 PM PDT 24
Finished Mar 28 02:19:12 PM PDT 24
Peak memory 240660 kb
Host smart-dcfbb3c2-acf4-4f9a-85ca-961e7c99f0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227523421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.4227523421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.79126411
Short name T357
Test name
Test status
Simulation time 24492170412 ps
CPU time 633.51 seconds
Started Mar 28 02:13:58 PM PDT 24
Finished Mar 28 02:24:31 PM PDT 24
Peak memory 231480 kb
Host smart-a8d8723c-12ac-4b05-b31c-62530397b2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79126411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.79126411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1696313650
Short name T458
Test name
Test status
Simulation time 37704720252 ps
CPU time 270.96 seconds
Started Mar 28 02:15:02 PM PDT 24
Finished Mar 28 02:19:33 PM PDT 24
Peak memory 244684 kb
Host smart-52682316-2e0d-4c73-9e71-fce40eade8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696313650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1696313650 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.473559242
Short name T530
Test name
Test status
Simulation time 93023182 ps
CPU time 3.62 seconds
Started Mar 28 02:14:54 PM PDT 24
Finished Mar 28 02:14:58 PM PDT 24
Peak memory 221552 kb
Host smart-4a6431b9-8189-476c-b194-37ace5c8d2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473559242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.473559242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.1559073188
Short name T58
Test name
Test status
Simulation time 10045240218 ps
CPU time 8.06 seconds
Started Mar 28 02:14:54 PM PDT 24
Finished Mar 28 02:15:03 PM PDT 24
Peak memory 207720 kb
Host smart-d9865907-3470-46ea-a236-975255f87ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559073188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1559073188 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.1375881935
Short name T760
Test name
Test status
Simulation time 34327527 ps
CPU time 1.3 seconds
Started Mar 28 02:14:54 PM PDT 24
Finished Mar 28 02:14:55 PM PDT 24
Peak memory 216088 kb
Host smart-3df07647-07d1-4664-835a-bff48bad1601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375881935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1375881935 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.1733854372
Short name T602
Test name
Test status
Simulation time 27973279866 ps
CPU time 1500.16 seconds
Started Mar 28 02:13:59 PM PDT 24
Finished Mar 28 02:38:59 PM PDT 24
Peak memory 397132 kb
Host smart-1499b9c5-1511-4853-8cc8-a4f85c44ba4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733854372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.1733854372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.659812743
Short name T848
Test name
Test status
Simulation time 72352048235 ps
CPU time 418.21 seconds
Started Mar 28 02:13:58 PM PDT 24
Finished Mar 28 02:20:56 PM PDT 24
Peak memory 248148 kb
Host smart-06944bbe-54fc-474c-89ed-ca845bfcfc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659812743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.659812743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.1951136201
Short name T985
Test name
Test status
Simulation time 11689939876 ps
CPU time 43.9 seconds
Started Mar 28 02:13:46 PM PDT 24
Finished Mar 28 02:14:32 PM PDT 24
Peak memory 224320 kb
Host smart-4860bea4-ba2c-4e1e-b0a5-a206edbc9647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951136201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1951136201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.445487619
Short name T496
Test name
Test status
Simulation time 121914034030 ps
CPU time 511.44 seconds
Started Mar 28 02:15:21 PM PDT 24
Finished Mar 28 02:23:53 PM PDT 24
Peak memory 286768 kb
Host smart-7b9f61f7-b9bf-4004-b7db-b9783555b4f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=445487619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.445487619 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.2565101904
Short name T535
Test name
Test status
Simulation time 229750560 ps
CPU time 4.77 seconds
Started Mar 28 02:15:00 PM PDT 24
Finished Mar 28 02:15:05 PM PDT 24
Peak memory 216088 kb
Host smart-e63253c0-01bf-4996-ae1f-8ea7ab54209d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565101904 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.2565101904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.1700675872
Short name T865
Test name
Test status
Simulation time 919890416 ps
CPU time 4.96 seconds
Started Mar 28 02:14:53 PM PDT 24
Finished Mar 28 02:14:58 PM PDT 24
Peak memory 216064 kb
Host smart-a2a849f9-e4e2-4794-bff6-4edc9fb3e491
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700675872 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.1700675872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.3538245228
Short name T238
Test name
Test status
Simulation time 39315399301 ps
CPU time 1731.09 seconds
Started Mar 28 02:14:00 PM PDT 24
Finished Mar 28 02:42:51 PM PDT 24
Peak memory 401292 kb
Host smart-b6b9adb3-1d36-41e3-9e14-c616c18512f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3538245228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3538245228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.1661177866
Short name T308
Test name
Test status
Simulation time 94038659216 ps
CPU time 1457.57 seconds
Started Mar 28 02:14:01 PM PDT 24
Finished Mar 28 02:38:19 PM PDT 24
Peak memory 377128 kb
Host smart-8ab3297c-1b4a-4f93-ab1f-44b6b7002917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1661177866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.1661177866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.3841437040
Short name T578
Test name
Test status
Simulation time 93263901858 ps
CPU time 1269.2 seconds
Started Mar 28 02:14:06 PM PDT 24
Finished Mar 28 02:35:16 PM PDT 24
Peak memory 328444 kb
Host smart-4f0ad1eb-1eaf-458e-bc1b-13350affae86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3841437040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3841437040 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.3337482855
Short name T290
Test name
Test status
Simulation time 50063972000 ps
CPU time 1046.3 seconds
Started Mar 28 02:14:24 PM PDT 24
Finished Mar 28 02:31:50 PM PDT 24
Peak memory 300016 kb
Host smart-1f2a6b94-0e17-4031-aa9a-a5069ed87281
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3337482855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3337482855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.1359515378
Short name T69
Test name
Test status
Simulation time 352541884775 ps
CPU time 4960.38 seconds
Started Mar 28 02:15:00 PM PDT 24
Finished Mar 28 03:37:41 PM PDT 24
Peak memory 654788 kb
Host smart-c69a3b9e-3d18-4af3-bedf-e63be047bc63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1359515378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.1359515378 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.3325310163
Short name T778
Test name
Test status
Simulation time 45034387631 ps
CPU time 3600.6 seconds
Started Mar 28 02:14:56 PM PDT 24
Finished Mar 28 03:14:57 PM PDT 24
Peak memory 560716 kb
Host smart-7c42eb51-6aee-4ac0-a465-e3e7c0ca531b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3325310163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3325310163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.3381996287
Short name T39
Test name
Test status
Simulation time 40468560 ps
CPU time 0.8 seconds
Started Mar 28 02:16:35 PM PDT 24
Finished Mar 28 02:16:35 PM PDT 24
Peak memory 205540 kb
Host smart-f8b34997-f741-41e0-9946-ee311bc0b70c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381996287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3381996287 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.4006733456
Short name T281
Test name
Test status
Simulation time 44717709499 ps
CPU time 237.18 seconds
Started Mar 28 02:15:50 PM PDT 24
Finished Mar 28 02:19:48 PM PDT 24
Peak memory 241664 kb
Host smart-ead33f11-6d64-43a5-a2bd-fb1e3ddc0198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006733456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.4006733456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.209192622
Short name T338
Test name
Test status
Simulation time 6929708432 ps
CPU time 109.55 seconds
Started Mar 28 02:15:24 PM PDT 24
Finished Mar 28 02:17:14 PM PDT 24
Peak memory 224720 kb
Host smart-3bb46ed5-97a2-4c21-92ac-8cdde3de84f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209192622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.209192622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.4148588766
Short name T13
Test name
Test status
Simulation time 2553853702 ps
CPU time 35.42 seconds
Started Mar 28 02:15:53 PM PDT 24
Finished Mar 28 02:16:29 PM PDT 24
Peak memory 224268 kb
Host smart-f90bf5e0-173b-4280-9484-9533ac433276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148588766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.4148588766 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.583369371
Short name T1038
Test name
Test status
Simulation time 50281873730 ps
CPU time 236.9 seconds
Started Mar 28 02:15:52 PM PDT 24
Finished Mar 28 02:19:49 PM PDT 24
Peak memory 240804 kb
Host smart-f4e47c46-0415-420c-ac31-81bb07facdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583369371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.583369371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.779693699
Short name T23
Test name
Test status
Simulation time 4035358565 ps
CPU time 3.58 seconds
Started Mar 28 02:15:54 PM PDT 24
Finished Mar 28 02:15:58 PM PDT 24
Peak memory 207644 kb
Host smart-566e4cfa-7afc-4cc2-b1ff-9816ead529e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779693699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.779693699 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.2449030684
Short name T83
Test name
Test status
Simulation time 41592475 ps
CPU time 1.18 seconds
Started Mar 28 02:15:51 PM PDT 24
Finished Mar 28 02:15:52 PM PDT 24
Peak memory 217028 kb
Host smart-9b5d08cd-8c67-470e-8380-83c665e5656c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449030684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2449030684 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.252353659
Short name T1083
Test name
Test status
Simulation time 26495394415 ps
CPU time 2254.26 seconds
Started Mar 28 02:15:23 PM PDT 24
Finished Mar 28 02:52:58 PM PDT 24
Peak memory 471272 kb
Host smart-d555325b-ae52-473d-a103-a24ec565f414
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252353659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_an
d_output.252353659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.2761754903
Short name T273
Test name
Test status
Simulation time 49752869142 ps
CPU time 209.44 seconds
Started Mar 28 02:15:24 PM PDT 24
Finished Mar 28 02:18:54 PM PDT 24
Peak memory 237700 kb
Host smart-5f9cca85-7722-4883-9e1f-c700adc03afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761754903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2761754903 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.1250140109
Short name T394
Test name
Test status
Simulation time 15306855166 ps
CPU time 65.1 seconds
Started Mar 28 02:15:24 PM PDT 24
Finished Mar 28 02:16:30 PM PDT 24
Peak memory 222784 kb
Host smart-39cb0ae7-cd23-4993-b367-affd15c1aa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250140109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1250140109 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.3622047277
Short name T736
Test name
Test status
Simulation time 17310011308 ps
CPU time 1369.77 seconds
Started Mar 28 02:15:52 PM PDT 24
Finished Mar 28 02:38:42 PM PDT 24
Peak memory 402744 kb
Host smart-63e2fdd1-92d0-4ac7-9fff-606560f12766
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3622047277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3622047277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_stress_all_with_rand_reset.3677221268
Short name T116
Test name
Test status
Simulation time 25757639055 ps
CPU time 283.95 seconds
Started Mar 28 02:16:36 PM PDT 24
Finished Mar 28 02:21:20 PM PDT 24
Peak memory 252552 kb
Host smart-48a3fd0f-286e-4f57-947a-49f30a84cdf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677221268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.3677221268 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.1637975816
Short name T940
Test name
Test status
Simulation time 1012873603 ps
CPU time 5.27 seconds
Started Mar 28 02:15:53 PM PDT 24
Finished Mar 28 02:15:59 PM PDT 24
Peak memory 216060 kb
Host smart-62c91729-0de2-45b1-a610-6793ba254deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637975816 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.1637975816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.3733240343
Short name T17
Test name
Test status
Simulation time 344520529 ps
CPU time 4.55 seconds
Started Mar 28 02:15:52 PM PDT 24
Finished Mar 28 02:15:57 PM PDT 24
Peak memory 216132 kb
Host smart-46b92321-7555-42ee-b0ae-1e02006c0081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733240343 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.3733240343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.358103621
Short name T952
Test name
Test status
Simulation time 195849954552 ps
CPU time 2024.68 seconds
Started Mar 28 02:15:45 PM PDT 24
Finished Mar 28 02:49:30 PM PDT 24
Peak memory 388120 kb
Host smart-c2f253e6-ce6b-43a1-b1bb-6c3702b63086
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=358103621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.358103621 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.1201977298
Short name T207
Test name
Test status
Simulation time 91760735739 ps
CPU time 2011.23 seconds
Started Mar 28 02:15:26 PM PDT 24
Finished Mar 28 02:48:57 PM PDT 24
Peak memory 375664 kb
Host smart-e2691dd7-7e63-4772-83ec-e9d64600df55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1201977298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.1201977298 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.329354674
Short name T895
Test name
Test status
Simulation time 13771836042 ps
CPU time 1180.53 seconds
Started Mar 28 02:15:22 PM PDT 24
Finished Mar 28 02:35:03 PM PDT 24
Peak memory 334752 kb
Host smart-d494f858-29e9-4bf9-9312-decd5226af86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=329354674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.329354674 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.3935999965
Short name T634
Test name
Test status
Simulation time 66081653457 ps
CPU time 770.95 seconds
Started Mar 28 02:15:23 PM PDT 24
Finished Mar 28 02:28:14 PM PDT 24
Peak memory 290780 kb
Host smart-16ddd617-af05-43b3-98e2-43cd7d2c24fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3935999965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.3935999965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.710249085
Short name T762
Test name
Test status
Simulation time 280642624233 ps
CPU time 4182.15 seconds
Started Mar 28 02:15:27 PM PDT 24
Finished Mar 28 03:25:11 PM PDT 24
Peak memory 643852 kb
Host smart-e6c2ed3c-f217-4cc9-9158-7c32b13f5df4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=710249085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.710249085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3980497927
Short name T70
Test name
Test status
Simulation time 314296322468 ps
CPU time 4168.48 seconds
Started Mar 28 02:15:23 PM PDT 24
Finished Mar 28 03:24:52 PM PDT 24
Peak memory 558668 kb
Host smart-19e588a8-aaa8-4f6d-983d-d211af1363aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3980497927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3980497927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.185945944
Short name T383
Test name
Test status
Simulation time 54466817 ps
CPU time 0.73 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 01:50:56 PM PDT 24
Peak memory 205592 kb
Host smart-80fdb727-59be-409a-899f-d03902b91ac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185945944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.185945944 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.2874109394
Short name T603
Test name
Test status
Simulation time 6345630428 ps
CPU time 44.68 seconds
Started Mar 28 01:50:53 PM PDT 24
Finished Mar 28 01:51:38 PM PDT 24
Peak memory 223244 kb
Host smart-061a5631-e705-443b-9079-00e510d882c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874109394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2874109394 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.2871064873
Short name T801
Test name
Test status
Simulation time 18051876349 ps
CPU time 246.34 seconds
Started Mar 28 01:50:53 PM PDT 24
Finished Mar 28 01:55:00 PM PDT 24
Peak memory 241296 kb
Host smart-cdf1569d-0d31-4ab9-b883-ba2c1053e7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871064873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2871064873 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.637008604
Short name T438
Test name
Test status
Simulation time 7485299565 ps
CPU time 602.68 seconds
Started Mar 28 01:50:52 PM PDT 24
Finished Mar 28 02:00:55 PM PDT 24
Peak memory 239380 kb
Host smart-1964e5cd-d506-4bec-91f4-bd0e7f0dd4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637008604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.637008604 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.599833839
Short name T782
Test name
Test status
Simulation time 3993797828 ps
CPU time 28.15 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 01:51:22 PM PDT 24
Peak memory 221028 kb
Host smart-0afdbb8e-e111-4d56-bb80-89ab5032b226
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=599833839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.599833839 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.10297728
Short name T622
Test name
Test status
Simulation time 169904147 ps
CPU time 4.9 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 01:50:59 PM PDT 24
Peak memory 216972 kb
Host smart-2c180561-69e4-4b70-9159-ca265f510814
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=10297728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.10297728 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2675126264
Short name T344
Test name
Test status
Simulation time 1461456880 ps
CPU time 15.84 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 01:51:10 PM PDT 24
Peak memory 217176 kb
Host smart-29004670-2f2a-40e9-9af5-efc18d81e0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675126264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2675126264 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.544374161
Short name T973
Test name
Test status
Simulation time 27172708256 ps
CPU time 289.93 seconds
Started Mar 28 01:50:52 PM PDT 24
Finished Mar 28 01:55:42 PM PDT 24
Peak memory 243332 kb
Host smart-981cab18-d183-44a3-9412-da12e9dd39c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544374161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.544374161 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.3282611093
Short name T716
Test name
Test status
Simulation time 1463527158 ps
CPU time 43.04 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 01:51:37 PM PDT 24
Peak memory 240576 kb
Host smart-3eea8986-067c-4bf4-9149-c753a67d8510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282611093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3282611093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.235979950
Short name T909
Test name
Test status
Simulation time 187273656 ps
CPU time 1.52 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 01:50:57 PM PDT 24
Peak memory 207136 kb
Host smart-bd41c238-e8d2-4cbd-9d86-fc16d7a1c50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235979950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.235979950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.3194927014
Short name T52
Test name
Test status
Simulation time 33742745 ps
CPU time 1.28 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 01:50:55 PM PDT 24
Peak memory 216048 kb
Host smart-dccb1263-f0db-45d0-a8e4-d82523a9c73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194927014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3194927014 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.3000578133
Short name T754
Test name
Test status
Simulation time 121999188712 ps
CPU time 510.29 seconds
Started Mar 28 01:50:49 PM PDT 24
Finished Mar 28 01:59:20 PM PDT 24
Peak memory 267220 kb
Host smart-2f6d4b4c-7dda-403f-a152-2d0b85c8d63f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000578133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.3000578133 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.2144402768
Short name T539
Test name
Test status
Simulation time 38097875558 ps
CPU time 265.48 seconds
Started Mar 28 01:50:53 PM PDT 24
Finished Mar 28 01:55:19 PM PDT 24
Peak memory 243448 kb
Host smart-b8d470df-37f8-49e2-a420-32bffacd3aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144402768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2144402768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.377645679
Short name T1027
Test name
Test status
Simulation time 45012188852 ps
CPU time 234.69 seconds
Started Mar 28 01:50:49 PM PDT 24
Finished Mar 28 01:54:45 PM PDT 24
Peak memory 235896 kb
Host smart-b7ed97b0-f436-48a9-a119-2c4397bcaad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377645679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.377645679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.1023542471
Short name T180
Test name
Test status
Simulation time 933407136 ps
CPU time 48.4 seconds
Started Mar 28 01:50:59 PM PDT 24
Finished Mar 28 01:51:47 PM PDT 24
Peak memory 224216 kb
Host smart-5951e0c4-3dbf-4ebb-b092-cd6ea0458b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023542471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1023542471 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.3740502139
Short name T112
Test name
Test status
Simulation time 20714007808 ps
CPU time 553.89 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 02:00:08 PM PDT 24
Peak memory 282124 kb
Host smart-fac7278c-a73e-4928-9eee-9a960a7bda80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740502139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.3740502139 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.1948926468
Short name T862
Test name
Test status
Simulation time 111459763 ps
CPU time 4.37 seconds
Started Mar 28 01:50:53 PM PDT 24
Finished Mar 28 01:50:58 PM PDT 24
Peak memory 216136 kb
Host smart-5391143f-1bd7-45d2-b587-876f5bd144e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948926468 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.1948926468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.2211568366
Short name T1063
Test name
Test status
Simulation time 990810719 ps
CPU time 4.44 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 01:50:59 PM PDT 24
Peak memory 216184 kb
Host smart-7d9f3991-38ef-4b5b-97d2-2b314dd277fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211568366 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.2211568366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.2951761503
Short name T282
Test name
Test status
Simulation time 77341165872 ps
CPU time 1594.16 seconds
Started Mar 28 01:50:53 PM PDT 24
Finished Mar 28 02:17:28 PM PDT 24
Peak memory 386956 kb
Host smart-1caec499-1e77-46b7-ae2e-9b7a1ec5285e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2951761503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.2951761503 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.3858592810
Short name T381
Test name
Test status
Simulation time 684136387501 ps
CPU time 2050.29 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 02:25:06 PM PDT 24
Peak memory 377348 kb
Host smart-769eb1bd-3ccb-43e6-9627-c16d19add1bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3858592810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.3858592810 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.3463088850
Short name T885
Test name
Test status
Simulation time 62391069575 ps
CPU time 1312.18 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 02:12:47 PM PDT 24
Peak memory 332956 kb
Host smart-03b613ea-c3f2-413a-9c19-918164c88a1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3463088850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.3463088850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.1032109285
Short name T783
Test name
Test status
Simulation time 396668807662 ps
CPU time 1012.89 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 02:07:47 PM PDT 24
Peak memory 290836 kb
Host smart-0befb4a7-835c-45f7-af15-b117756e2d74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1032109285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.1032109285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.2097715172
Short name T666
Test name
Test status
Simulation time 1067279515511 ps
CPU time 5654.54 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 03:25:10 PM PDT 24
Peak memory 648372 kb
Host smart-7705fb87-c0ce-48ab-adfa-f6074835e446
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2097715172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.2097715172 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.1619672394
Short name T612
Test name
Test status
Simulation time 43133695782 ps
CPU time 3368.54 seconds
Started Mar 28 01:50:53 PM PDT 24
Finished Mar 28 02:47:02 PM PDT 24
Peak memory 559032 kb
Host smart-6e950294-0da2-4c57-a6b0-c8331cea452a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1619672394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.1619672394 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.703993439
Short name T676
Test name
Test status
Simulation time 47597118 ps
CPU time 0.77 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:51:06 PM PDT 24
Peak memory 205596 kb
Host smart-94765ba1-d776-4241-8e93-3579271023d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703993439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.703993439 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.3177736353
Short name T1081
Test name
Test status
Simulation time 58098872769 ps
CPU time 145 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 01:53:21 PM PDT 24
Peak memory 233008 kb
Host smart-a6a70b75-9744-4639-ab17-781ade49041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177736353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3177736353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.3433788157
Short name T790
Test name
Test status
Simulation time 1661841903 ps
CPU time 19.96 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 01:51:15 PM PDT 24
Peak memory 220688 kb
Host smart-49ad34eb-865c-4215-b12a-9727f5e3c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433788157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.3433788157 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.3405928836
Short name T463
Test name
Test status
Simulation time 106256313073 ps
CPU time 716.14 seconds
Started Mar 28 01:50:53 PM PDT 24
Finished Mar 28 02:02:50 PM PDT 24
Peak memory 232452 kb
Host smart-4999d586-cd08-4491-8461-a0bd23e78b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405928836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3405928836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2051447125
Short name T640
Test name
Test status
Simulation time 4447797738 ps
CPU time 29.23 seconds
Started Mar 28 01:50:46 PM PDT 24
Finished Mar 28 01:51:16 PM PDT 24
Peak memory 224104 kb
Host smart-ca364ec0-d082-4d0a-b085-753d17882cad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2051447125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2051447125 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1860061772
Short name T735
Test name
Test status
Simulation time 1402288065 ps
CPU time 3.62 seconds
Started Mar 28 01:51:03 PM PDT 24
Finished Mar 28 01:51:07 PM PDT 24
Peak memory 216952 kb
Host smart-8ed8c1a8-2a13-44a3-9526-90bc900df946
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1860061772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1860061772 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.1736865508
Short name T486
Test name
Test status
Simulation time 155239740928 ps
CPU time 117.29 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 01:53:07 PM PDT 24
Peak memory 216136 kb
Host smart-ee8da133-4174-4a4b-9cf6-42bd6df534f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736865508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1736865508 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.817670281
Short name T243
Test name
Test status
Simulation time 10655655918 ps
CPU time 199.17 seconds
Started Mar 28 01:50:46 PM PDT 24
Finished Mar 28 01:54:05 PM PDT 24
Peak memory 239548 kb
Host smart-2d2044a7-6ca0-46dd-9550-252fb4fed854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817670281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.817670281 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.4210608863
Short name T30
Test name
Test status
Simulation time 306730544 ps
CPU time 11.1 seconds
Started Mar 28 01:50:45 PM PDT 24
Finished Mar 28 01:50:57 PM PDT 24
Peak memory 224320 kb
Host smart-6b389811-cb4f-4997-a978-0625935be581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210608863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.4210608863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.3746257581
Short name T380
Test name
Test status
Simulation time 1401107164 ps
CPU time 1.35 seconds
Started Mar 28 01:50:52 PM PDT 24
Finished Mar 28 01:50:54 PM PDT 24
Peak memory 206956 kb
Host smart-f694bac5-8aa1-4920-8bc8-a4fdfbf046d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746257581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.3746257581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.2347025730
Short name T49
Test name
Test status
Simulation time 2718096753 ps
CPU time 9.6 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:51:15 PM PDT 24
Peak memory 224340 kb
Host smart-bc0e59e6-6dfd-457c-b682-3d85c0d8a816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347025730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2347025730 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.2459505788
Short name T814
Test name
Test status
Simulation time 60758701990 ps
CPU time 828.64 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 02:04:44 PM PDT 24
Peak memory 304440 kb
Host smart-4ec3f73e-ec4c-415d-9ab2-8e362cb03ca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459505788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.2459505788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.775038685
Short name T995
Test name
Test status
Simulation time 9691606812 ps
CPU time 226.41 seconds
Started Mar 28 01:50:47 PM PDT 24
Finished Mar 28 01:54:34 PM PDT 24
Peak memory 241020 kb
Host smart-17a9ff76-339b-49c4-9786-ce6ae2a93977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775038685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.775038685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.4188096501
Short name T708
Test name
Test status
Simulation time 10521648035 ps
CPU time 136.81 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 01:53:11 PM PDT 24
Peak memory 240496 kb
Host smart-9bd99a48-b2d0-4d4c-bac7-7d6fa0056292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188096501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.4188096501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.3886193141
Short name T451
Test name
Test status
Simulation time 479999653 ps
CPU time 8.27 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 01:51:02 PM PDT 24
Peak memory 219616 kb
Host smart-063114a9-9721-476b-983f-2d10af3cdd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886193141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3886193141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.1279689527
Short name T421
Test name
Test status
Simulation time 3240278948 ps
CPU time 19.96 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 01:51:28 PM PDT 24
Peak memory 217756 kb
Host smart-13f838d0-deec-4577-9672-acd1ec3dc694
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1279689527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1279689527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.4098628687
Short name T262
Test name
Test status
Simulation time 746123255 ps
CPU time 4.19 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 01:50:59 PM PDT 24
Peak memory 216072 kb
Host smart-652007fe-2b58-4860-86fb-c27f3c2f2321
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098628687 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.4098628687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3222630805
Short name T833
Test name
Test status
Simulation time 252322421 ps
CPU time 4.66 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 01:50:59 PM PDT 24
Peak memory 216176 kb
Host smart-f26e25aa-2cd1-400f-9e62-4d63520b5fd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222630805 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3222630805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.924834563
Short name T588
Test name
Test status
Simulation time 19198461473 ps
CPU time 1639.58 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 02:18:15 PM PDT 24
Peak memory 396052 kb
Host smart-db349d27-3f39-4f61-8168-7aae623d5f26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=924834563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.924834563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.760931337
Short name T800
Test name
Test status
Simulation time 131204235377 ps
CPU time 1682.5 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 02:18:57 PM PDT 24
Peak memory 377108 kb
Host smart-1dbeb484-d780-433a-a58f-39d6f451aa11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=760931337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.760931337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.1632456305
Short name T356
Test name
Test status
Simulation time 262609054562 ps
CPU time 1371.89 seconds
Started Mar 28 01:50:54 PM PDT 24
Finished Mar 28 02:13:46 PM PDT 24
Peak memory 344616 kb
Host smart-de07c5b3-522a-432e-ab1d-ebc02ad425c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1632456305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.1632456305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.2435480284
Short name T12
Test name
Test status
Simulation time 22868827709 ps
CPU time 798.69 seconds
Started Mar 28 01:50:55 PM PDT 24
Finished Mar 28 02:04:13 PM PDT 24
Peak memory 297540 kb
Host smart-cbea81df-1ecc-4c52-a1e6-d055faa9a214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2435480284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2435480284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.265862797
Short name T231
Test name
Test status
Simulation time 294742359989 ps
CPU time 5153.72 seconds
Started Mar 28 01:50:56 PM PDT 24
Finished Mar 28 03:16:51 PM PDT 24
Peak memory 649752 kb
Host smart-f30d6644-bf03-4e25-b894-8c487bcb242b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=265862797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.265862797 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.844846820
Short name T544
Test name
Test status
Simulation time 44663501163 ps
CPU time 3340.44 seconds
Started Mar 28 01:50:53 PM PDT 24
Finished Mar 28 02:46:34 PM PDT 24
Peak memory 545828 kb
Host smart-32de52da-4b2a-479d-b209-e6aa5552afb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=844846820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.844846820 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.1967820164
Short name T815
Test name
Test status
Simulation time 88522838 ps
CPU time 0.8 seconds
Started Mar 28 01:51:04 PM PDT 24
Finished Mar 28 01:51:05 PM PDT 24
Peak memory 205604 kb
Host smart-670fbfb6-2e0f-49fa-9680-a73203bd1a39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967820164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1967820164 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.406249505
Short name T704
Test name
Test status
Simulation time 16797999123 ps
CPU time 170.58 seconds
Started Mar 28 01:51:01 PM PDT 24
Finished Mar 28 01:53:51 PM PDT 24
Peak memory 236208 kb
Host smart-5cd5951d-9286-49cb-a665-eb86614aef82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406249505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.406249505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.308743225
Short name T840
Test name
Test status
Simulation time 4865883005 ps
CPU time 37.12 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 01:51:44 PM PDT 24
Peak memory 224316 kb
Host smart-fd797048-ad8f-484a-bfab-9996c43c4ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308743225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.308743225 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.3497369774
Short name T976
Test name
Test status
Simulation time 8792537384 ps
CPU time 131.52 seconds
Started Mar 28 01:51:03 PM PDT 24
Finished Mar 28 01:53:14 PM PDT 24
Peak memory 224384 kb
Host smart-f991099c-32d9-4c5b-ba4d-0120f03b8d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497369774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3497369774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.48562679
Short name T632
Test name
Test status
Simulation time 691436896 ps
CPU time 19.4 seconds
Started Mar 28 01:51:01 PM PDT 24
Finished Mar 28 01:51:21 PM PDT 24
Peak memory 224148 kb
Host smart-0809d45e-b81d-48ac-abc3-c9df0f9f8f53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=48562679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.48562679 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.3799389101
Short name T195
Test name
Test status
Simulation time 96929918 ps
CPU time 7.08 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:51:12 PM PDT 24
Peak memory 219440 kb
Host smart-83c7b2b2-d35a-422f-8c65-8a5169a7a511
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3799389101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3799389101 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3469324429
Short name T908
Test name
Test status
Simulation time 10651494692 ps
CPU time 34.8 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 01:51:41 PM PDT 24
Peak memory 216208 kb
Host smart-9375d4c7-6243-44ce-86b0-ddc85e97fc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469324429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3469324429 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.2024602487
Short name T1050
Test name
Test status
Simulation time 16883326895 ps
CPU time 138.95 seconds
Started Mar 28 01:51:01 PM PDT 24
Finished Mar 28 01:53:20 PM PDT 24
Peak memory 236188 kb
Host smart-f6bcd1ca-24fe-445b-9822-ee8f13759166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024602487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2024602487 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.3419499290
Short name T154
Test name
Test status
Simulation time 43503205592 ps
CPU time 358.16 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 01:57:06 PM PDT 24
Peak memory 265276 kb
Host smart-9fb5fa4b-350d-4566-bf0f-d8b299e7f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419499290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3419499290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.265254769
Short name T529
Test name
Test status
Simulation time 518461763 ps
CPU time 3.1 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 01:51:09 PM PDT 24
Peak memory 207468 kb
Host smart-35d71501-6450-4054-b7be-61ee902cc7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265254769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.265254769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1301356558
Short name T841
Test name
Test status
Simulation time 131858454 ps
CPU time 1.31 seconds
Started Mar 28 01:51:09 PM PDT 24
Finished Mar 28 01:51:10 PM PDT 24
Peak memory 216052 kb
Host smart-8396ca9b-d4a7-4c95-836f-04df29090f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301356558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1301356558 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.711032603
Short name T323
Test name
Test status
Simulation time 132003298156 ps
CPU time 3038.22 seconds
Started Mar 28 01:51:01 PM PDT 24
Finished Mar 28 02:41:40 PM PDT 24
Peak memory 478676 kb
Host smart-989b8c7b-c8e9-45ab-af54-d1a70b27c3ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711032603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and
_output.711032603 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.2160043139
Short name T757
Test name
Test status
Simulation time 8282537565 ps
CPU time 262.9 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:55:28 PM PDT 24
Peak memory 243052 kb
Host smart-6bf323e5-07bd-432d-949d-6c2feaeba2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160043139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2160043139 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.3605375257
Short name T468
Test name
Test status
Simulation time 19457790514 ps
CPU time 437.98 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 01:58:25 PM PDT 24
Peak memory 252172 kb
Host smart-1166570b-bd92-4468-a482-e88c9b46ac35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605375257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3605375257 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.209155820
Short name T887
Test name
Test status
Simulation time 3826966466 ps
CPU time 21.63 seconds
Started Mar 28 01:51:03 PM PDT 24
Finished Mar 28 01:51:25 PM PDT 24
Peak memory 218832 kb
Host smart-360725d9-d7b4-4c37-84d7-98eef6a32ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209155820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.209155820 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.1543644296
Short name T642
Test name
Test status
Simulation time 61635799220 ps
CPU time 1466.95 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 02:15:35 PM PDT 24
Peak memory 354216 kb
Host smart-252707e2-2f0e-4789-9ecc-49973fc86e08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1543644296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1543644296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.1753109636
Short name T111
Test name
Test status
Simulation time 340713893618 ps
CPU time 1479.56 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 02:15:45 PM PDT 24
Peak memory 306308 kb
Host smart-140d078d-d742-45fd-9dae-4dc5edbd5f8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1753109636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.1753109636 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.2382428737
Short name T781
Test name
Test status
Simulation time 517268796 ps
CPU time 4.81 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 01:51:11 PM PDT 24
Peak memory 216112 kb
Host smart-1ebd6e41-bcc7-4e40-b033-6d9f8b999672
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382428737 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.2382428737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2683630548
Short name T431
Test name
Test status
Simulation time 254762135 ps
CPU time 3.87 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:51:09 PM PDT 24
Peak memory 209184 kb
Host smart-47176673-3cd4-4a86-a40d-a1283103603d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683630548 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2683630548 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.590969227
Short name T1011
Test name
Test status
Simulation time 97030128566 ps
CPU time 1897.08 seconds
Started Mar 28 01:50:59 PM PDT 24
Finished Mar 28 02:22:36 PM PDT 24
Peak memory 388172 kb
Host smart-6bcbc05b-290b-4da7-953b-a700bb1ee28b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=590969227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.590969227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.2101056953
Short name T613
Test name
Test status
Simulation time 64240835034 ps
CPU time 1701.73 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 02:19:30 PM PDT 24
Peak memory 377704 kb
Host smart-95fcc041-d30c-4137-adfc-f0426c4c08c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2101056953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.2101056953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.1745528095
Short name T648
Test name
Test status
Simulation time 27690613439 ps
CPU time 1133.97 seconds
Started Mar 28 01:51:03 PM PDT 24
Finished Mar 28 02:09:57 PM PDT 24
Peak memory 339884 kb
Host smart-829e9731-f991-47f4-bd25-a11350051582
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1745528095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.1745528095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.3502347471
Short name T928
Test name
Test status
Simulation time 282915821550 ps
CPU time 899.31 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 02:06:06 PM PDT 24
Peak memory 295432 kb
Host smart-2d8febac-ba1f-49f5-95f0-b9c4c10c30e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3502347471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.3502347471 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.3250222335
Short name T204
Test name
Test status
Simulation time 945335629500 ps
CPU time 5746.01 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 03:26:53 PM PDT 24
Peak memory 645916 kb
Host smart-f9a82992-7297-4aed-b1e2-92b3a23251be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3250222335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.3250222335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.2857009582
Short name T803
Test name
Test status
Simulation time 214432080607 ps
CPU time 4605.41 seconds
Started Mar 28 01:51:09 PM PDT 24
Finished Mar 28 03:07:55 PM PDT 24
Peak memory 553404 kb
Host smart-e8b551cb-f209-4e7b-8456-37228504e061
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2857009582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.2857009582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3517533332
Short name T543
Test name
Test status
Simulation time 49363187 ps
CPU time 0.82 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 01:51:11 PM PDT 24
Peak memory 205564 kb
Host smart-6aee07fb-3563-4ccc-8b47-6397f58c71b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517533332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3517533332 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.3065404873
Short name T316
Test name
Test status
Simulation time 860532992 ps
CPU time 29.43 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 01:51:36 PM PDT 24
Peak memory 220772 kb
Host smart-79c2c334-87c4-4908-8a31-180b561357ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065404873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3065404873 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.1067989718
Short name T436
Test name
Test status
Simulation time 23283208150 ps
CPU time 222.41 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:54:48 PM PDT 24
Peak memory 240048 kb
Host smart-eec3a5e4-fa67-4422-8ae2-ee828b690794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067989718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1067989718 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.2596774961
Short name T624
Test name
Test status
Simulation time 7889958322 ps
CPU time 220.94 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:54:46 PM PDT 24
Peak memory 226672 kb
Host smart-1fdc42ea-55fc-4fe4-b4e4-9caf6ff2e017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596774961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2596774961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2398891585
Short name T475
Test name
Test status
Simulation time 1828238167 ps
CPU time 12.98 seconds
Started Mar 28 01:51:04 PM PDT 24
Finished Mar 28 01:51:17 PM PDT 24
Peak memory 215980 kb
Host smart-92a28ddf-6cdd-450f-a288-dfa03a9e8844
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2398891585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2398891585 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.4057757387
Short name T732
Test name
Test status
Simulation time 1085158316 ps
CPU time 29.99 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:51:35 PM PDT 24
Peak memory 224112 kb
Host smart-bd45d52e-07cc-4879-991f-b05cd618b0a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4057757387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.4057757387 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.170492401
Short name T26
Test name
Test status
Simulation time 11219891852 ps
CPU time 51.46 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 01:51:59 PM PDT 24
Peak memory 216188 kb
Host smart-3a4e15fe-3b3d-4987-81d7-f2433f240aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170492401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.170492401 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.3957218669
Short name T283
Test name
Test status
Simulation time 10209215233 ps
CPU time 152.99 seconds
Started Mar 28 01:51:23 PM PDT 24
Finished Mar 28 01:53:56 PM PDT 24
Peak memory 234300 kb
Host smart-c300564b-c51f-4cee-a1b2-71f26391f175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957218669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3957218669 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.157256813
Short name T525
Test name
Test status
Simulation time 18424746512 ps
CPU time 390.53 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:57:36 PM PDT 24
Peak memory 257076 kb
Host smart-c7b81af3-f1a1-46d7-9437-f9543d5d1c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157256813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.157256813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.3398344329
Short name T1052
Test name
Test status
Simulation time 619737273 ps
CPU time 3.41 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 01:51:11 PM PDT 24
Peak memory 207628 kb
Host smart-1154e262-a9d0-4f6e-bd82-6378d6e86679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398344329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3398344329 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.129211494
Short name T1055
Test name
Test status
Simulation time 73070843 ps
CPU time 1.2 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 01:51:07 PM PDT 24
Peak memory 215992 kb
Host smart-86abd27f-1f1f-4649-ad1e-28ffa51f87d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129211494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.129211494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.3443776567
Short name T369
Test name
Test status
Simulation time 827231304495 ps
CPU time 2282.47 seconds
Started Mar 28 01:51:09 PM PDT 24
Finished Mar 28 02:29:12 PM PDT 24
Peak memory 426204 kb
Host smart-672ad2ad-8b29-4a24-8a15-2e76f656759a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443776567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.3443776567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.3296842096
Short name T660
Test name
Test status
Simulation time 6584208015 ps
CPU time 99.63 seconds
Started Mar 28 01:51:05 PM PDT 24
Finished Mar 28 01:52:45 PM PDT 24
Peak memory 232452 kb
Host smart-e7e01c5d-d720-4a82-ba55-6da0c465469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296842096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3296842096 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.3802314240
Short name T1084
Test name
Test status
Simulation time 4574381902 ps
CPU time 338 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 01:56:44 PM PDT 24
Peak memory 248468 kb
Host smart-b1cd0ac0-fc5a-4ae7-8b48-a91ed3dee6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802314240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3802314240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.93264828
Short name T237
Test name
Test status
Simulation time 862911763 ps
CPU time 35.88 seconds
Started Mar 28 01:51:02 PM PDT 24
Finished Mar 28 01:51:38 PM PDT 24
Peak memory 219656 kb
Host smart-b8c995d9-e328-42ee-8d79-76f92a0e04a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93264828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.93264828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.245515646
Short name T300
Test name
Test status
Simulation time 39336569029 ps
CPU time 762.74 seconds
Started Mar 28 01:51:07 PM PDT 24
Finished Mar 28 02:03:50 PM PDT 24
Peak memory 316496 kb
Host smart-24136651-3988-4061-afe5-572fd6d5c14f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=245515646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.245515646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.79750360
Short name T1054
Test name
Test status
Simulation time 131510947 ps
CPU time 4.28 seconds
Started Mar 28 01:51:06 PM PDT 24
Finished Mar 28 01:51:10 PM PDT 24
Peak memory 215980 kb
Host smart-f8fe8b65-4459-472f-9afc-bd6a27fda707
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79750360 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.kmac_test_vectors_kmac.79750360 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2026821525
Short name T913
Test name
Test status
Simulation time 69038047 ps
CPU time 3.94 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 01:51:12 PM PDT 24
Peak memory 216044 kb
Host smart-e20801cd-a7da-40c2-992d-ac69c2d678a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026821525 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2026821525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.4096863229
Short name T1004
Test name
Test status
Simulation time 133110054724 ps
CPU time 1747.47 seconds
Started Mar 28 01:51:03 PM PDT 24
Finished Mar 28 02:20:11 PM PDT 24
Peak memory 379392 kb
Host smart-bd53e46c-74ce-44c5-adb7-4e79584a38ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4096863229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.4096863229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.183803488
Short name T382
Test name
Test status
Simulation time 36161126747 ps
CPU time 1580.73 seconds
Started Mar 28 01:51:04 PM PDT 24
Finished Mar 28 02:17:25 PM PDT 24
Peak memory 388888 kb
Host smart-c896c880-6d90-4a50-a19e-b75da9f5772d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=183803488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.183803488 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.2355427528
Short name T1002
Test name
Test status
Simulation time 14368633075 ps
CPU time 1237.9 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 02:11:46 PM PDT 24
Peak memory 335804 kb
Host smart-7d878578-3d8b-4065-a9c3-4c2f3d66f7a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2355427528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2355427528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.2521846146
Short name T828
Test name
Test status
Simulation time 203858911017 ps
CPU time 1028.05 seconds
Started Mar 28 01:51:04 PM PDT 24
Finished Mar 28 02:08:12 PM PDT 24
Peak memory 295628 kb
Host smart-090f3622-dd29-4297-b7e6-79c031bd461a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2521846146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.2521846146 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.733360260
Short name T557
Test name
Test status
Simulation time 721906598081 ps
CPU time 4968.82 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 03:13:57 PM PDT 24
Peak memory 658024 kb
Host smart-e9dcf052-1c57-4b24-bcdf-8ff3f4a4d333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=733360260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.733360260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.2820366648
Short name T1013
Test name
Test status
Simulation time 151337735026 ps
CPU time 3867.96 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 02:55:37 PM PDT 24
Peak memory 561284 kb
Host smart-90975898-cf28-4491-a6cb-509e58db74da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2820366648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.2820366648 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.778743421
Short name T223
Test name
Test status
Simulation time 20944816 ps
CPU time 0.88 seconds
Started Mar 28 01:51:02 PM PDT 24
Finished Mar 28 01:51:03 PM PDT 24
Peak memory 205572 kb
Host smart-83796367-0c78-4538-914e-1f2edfb04274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778743421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.778743421 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.1525014627
Short name T419
Test name
Test status
Simulation time 8602486283 ps
CPU time 204.85 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 01:54:35 PM PDT 24
Peak memory 240844 kb
Host smart-91b636a6-6785-4cc3-b7ee-01702511ca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525014627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1525014627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.4026843653
Short name T189
Test name
Test status
Simulation time 15783634637 ps
CPU time 253.11 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 01:55:23 PM PDT 24
Peak memory 241288 kb
Host smart-6e61f4ab-0c99-4b21-8e25-7c39418b2353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026843653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.4026843653 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.1747799362
Short name T963
Test name
Test status
Simulation time 2823018926 ps
CPU time 123.33 seconds
Started Mar 28 01:51:07 PM PDT 24
Finished Mar 28 01:53:11 PM PDT 24
Peak memory 223028 kb
Host smart-58cd06a4-b753-47f5-bc19-8cef6ded15f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747799362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1747799362 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.2174748738
Short name T819
Test name
Test status
Simulation time 645729577 ps
CPU time 11.64 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 01:51:22 PM PDT 24
Peak memory 222924 kb
Host smart-3bdca18d-dc8a-4d3c-abc6-f9dfc305aac2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2174748738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2174748738 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.715582819
Short name T768
Test name
Test status
Simulation time 1011102368 ps
CPU time 20.33 seconds
Started Mar 28 01:51:03 PM PDT 24
Finished Mar 28 01:51:24 PM PDT 24
Peak memory 224100 kb
Host smart-fbf222a5-06e8-466a-b3ee-44a246b6bf68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=715582819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.715582819 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.2934227337
Short name T150
Test name
Test status
Simulation time 1247284097 ps
CPU time 10.76 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:51:30 PM PDT 24
Peak memory 216116 kb
Host smart-606f1892-cbe8-4f20-9663-9c54ff312b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934227337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2934227337 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.2215351920
Short name T151
Test name
Test status
Simulation time 6662337141 ps
CPU time 62.9 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:52:22 PM PDT 24
Peak memory 226376 kb
Host smart-695688b5-80be-45ef-8ab2-5c925f58df72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215351920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2215351920 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.521678037
Short name T550
Test name
Test status
Simulation time 4137085660 ps
CPU time 39.49 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 01:51:50 PM PDT 24
Peak memory 239424 kb
Host smart-f1fc28d2-7298-40c5-8658-f3fab615c11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521678037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.521678037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.1509116147
Short name T567
Test name
Test status
Simulation time 850803751 ps
CPU time 2.71 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:51:22 PM PDT 24
Peak memory 207668 kb
Host smart-931191a6-821d-42df-885f-e0bd373ad139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509116147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1509116147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.436429029
Short name T82
Test name
Test status
Simulation time 55055305 ps
CPU time 1.18 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:51:20 PM PDT 24
Peak memory 215988 kb
Host smart-861b46a3-7641-47d8-a896-bdccfdeda9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436429029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.436429029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.2723408897
Short name T713
Test name
Test status
Simulation time 90398104938 ps
CPU time 2603.13 seconds
Started Mar 28 01:51:09 PM PDT 24
Finished Mar 28 02:34:32 PM PDT 24
Peak memory 472020 kb
Host smart-15b22035-0fc0-4561-aa35-e6d067f404c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723408897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.2723408897 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.2493223588
Short name T804
Test name
Test status
Simulation time 3490848493 ps
CPU time 84.36 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 01:52:34 PM PDT 24
Peak memory 228488 kb
Host smart-daa2cd93-0a30-4cfd-a8b1-0756578807ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493223588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2493223588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.1473002066
Short name T342
Test name
Test status
Simulation time 46568569205 ps
CPU time 203.16 seconds
Started Mar 28 01:51:08 PM PDT 24
Finished Mar 28 01:54:32 PM PDT 24
Peak memory 236568 kb
Host smart-e19ea04f-9409-4b34-baff-5e8caa2cf8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473002066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1473002066 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.2821788892
Short name T352
Test name
Test status
Simulation time 5694050254 ps
CPU time 14.3 seconds
Started Mar 28 01:51:09 PM PDT 24
Finished Mar 28 01:51:23 PM PDT 24
Peak memory 219660 kb
Host smart-886e80dc-e89d-461a-a9b6-41ba3a7cfe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821788892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2821788892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.1579242975
Short name T755
Test name
Test status
Simulation time 31223244903 ps
CPU time 1139.96 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 02:10:10 PM PDT 24
Peak memory 369212 kb
Host smart-656efe45-9861-4df6-a10a-fb8dcd34bc90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1579242975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1579242975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.4266224710
Short name T115
Test name
Test status
Simulation time 150157310869 ps
CPU time 718.96 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 02:03:18 PM PDT 24
Peak memory 297720 kb
Host smart-d7da3ed1-0a9a-4cbb-ba08-c3779faa2038
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266224710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.4266224710 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.2722297542
Short name T445
Test name
Test status
Simulation time 932208992 ps
CPU time 4.97 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:51:24 PM PDT 24
Peak memory 216160 kb
Host smart-3f19a15d-8a78-423a-8f52-c4bfebb334b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722297542 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.2722297542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.1579290388
Short name T915
Test name
Test status
Simulation time 168941356 ps
CPU time 4.68 seconds
Started Mar 28 01:51:19 PM PDT 24
Finished Mar 28 01:51:24 PM PDT 24
Peak memory 216124 kb
Host smart-283dfdfc-9d69-40ae-9f8f-ffb9a65c8a76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579290388 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.1579290388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.4143399592
Short name T220
Test name
Test status
Simulation time 371076887254 ps
CPU time 1759.92 seconds
Started Mar 28 01:51:09 PM PDT 24
Finished Mar 28 02:20:29 PM PDT 24
Peak memory 378752 kb
Host smart-f0af81fc-9c29-4a39-b06d-2e7e1938fe87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4143399592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.4143399592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.934950518
Short name T969
Test name
Test status
Simulation time 36553462284 ps
CPU time 1493.47 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 02:16:03 PM PDT 24
Peak memory 378072 kb
Host smart-769a8e59-5aa6-4581-906b-7c045da13ecf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=934950518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.934950518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.2999028926
Short name T182
Test name
Test status
Simulation time 92483787513 ps
CPU time 1407.12 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 02:14:37 PM PDT 24
Peak memory 331892 kb
Host smart-1f7e67a4-f448-4df9-a026-9d3bd6a32fdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2999028926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.2999028926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.3516336758
Short name T714
Test name
Test status
Simulation time 135296648326 ps
CPU time 914.6 seconds
Started Mar 28 01:51:07 PM PDT 24
Finished Mar 28 02:06:22 PM PDT 24
Peak memory 301900 kb
Host smart-e5d64b4f-aef1-4940-b369-d319ecbc7b87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3516336758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.3516336758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.382260418
Short name T202
Test name
Test status
Simulation time 211965076598 ps
CPU time 4057.59 seconds
Started Mar 28 01:51:10 PM PDT 24
Finished Mar 28 02:58:48 PM PDT 24
Peak memory 651992 kb
Host smart-42ec4dd0-65bd-4f02-8ded-b86d9526be32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=382260418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.382260418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.372626267
Short name T349
Test name
Test status
Simulation time 254538164041 ps
CPU time 3555.67 seconds
Started Mar 28 01:51:13 PM PDT 24
Finished Mar 28 02:50:29 PM PDT 24
Peak memory 561608 kb
Host smart-9da64af9-b582-4bc0-8b03-160ad699e574
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=372626267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.372626267 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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