Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100401937	1			T1	10315		T2	268		T3	222299
all_values[1]	100401937	1			T1	10315		T2	268		T3	222299
all_values[2]	100401937	1			T1	10315		T2	268		T3	222299

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

510326

1

T1

531

T2

203

T3

21

auto[1]

300695485

1

T1

30414

T2

601

T3

666876

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299676888

1

T1

30687

T2

753

T3

665139

auto[1]

1528923

1

T1

258

T2

51

T3

1758

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	144038	1			T1	134		T2	181		T3	3
all_values[0]	auto[0]	auto[1]	2036	1			T2	16		T3	4		T12	6
all_values[0]	auto[1]	auto[0]	99748258	1			T1	10095		T2	70		T3	221710
all_values[0]	auto[1]	auto[1]	507605	1			T1	86		T2	1		T3	582
all_values[1]	auto[0]	auto[0]	165082	1			T3	6		T12	2483		T14	49
all_values[1]	auto[0]	auto[1]	1590	1			T3	5		T12	3		T14	1
all_values[1]	auto[1]	auto[0]	99727214	1			T1	10229		T2	251		T3	221707
all_values[1]	auto[1]	auto[1]	508051	1			T1	86		T2	17		T3	581
all_values[2]	auto[0]	auto[0]	195924	1			T1	393		T2	4		T3	1
all_values[2]	auto[0]	auto[1]	1656	1			T1	4		T2	2		T3	2
all_values[2]	auto[1]	auto[0]	99696372	1			T1	9836		T2	247		T3	221712
all_values[2]	auto[1]	auto[1]	507985	1			T1	82		T2	15		T3	584