Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
305628 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
388532 |
1 |
|
|
T1 |
126 |
|
T2 |
16 |
|
T3 |
778 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174132 |
1 |
|
|
T1 |
35 |
|
T2 |
4 |
|
T3 |
194 |
lower_val |
171984 |
1 |
|
|
T1 |
32 |
|
T2 |
6 |
|
T3 |
196 |
zero_val |
1846 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345976 |
1 |
|
|
T1 |
54 |
|
T2 |
14 |
|
T3 |
394 |
lower_val |
348178 |
1 |
|
|
T1 |
74 |
|
T2 |
4 |
|
T3 |
386 |
zero_val |
6 |
1 |
|
|
T171 |
2 |
|
T172 |
2 |
|
T173 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
38169 |
1 |
|
|
T12 |
23 |
|
T16 |
67 |
|
T26 |
10 |
higher_val |
higher_val |
auto[1] |
48758 |
1 |
|
|
T1 |
16 |
|
T2 |
1 |
|
T3 |
94 |
higher_val |
lower_val |
auto[0] |
38407 |
1 |
|
|
T12 |
17 |
|
T16 |
69 |
|
T17 |
2 |
higher_val |
lower_val |
auto[1] |
48795 |
1 |
|
|
T1 |
19 |
|
T2 |
3 |
|
T3 |
100 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T171 |
2 |
|
T173 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
37606 |
1 |
|
|
T4 |
1 |
|
T12 |
19 |
|
T16 |
54 |
lower_val |
higher_val |
auto[1] |
48123 |
1 |
|
|
T1 |
15 |
|
T2 |
5 |
|
T3 |
93 |
lower_val |
lower_val |
auto[0] |
37960 |
1 |
|
|
T12 |
21 |
|
T14 |
1 |
|
T16 |
58 |
lower_val |
lower_val |
auto[1] |
48293 |
1 |
|
|
T1 |
17 |
|
T2 |
1 |
|
T3 |
103 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T173 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T172 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
657 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
274 |
1 |
|
|
T15 |
5 |
|
T81 |
3 |
|
T30 |
1 |
zero_val |
lower_val |
auto[0] |
673 |
1 |
|
|
T1 |
1 |
|
T14 |
1 |
|
T15 |
1 |
zero_val |
lower_val |
auto[1] |
242 |
1 |
|
|
T12 |
1 |
|
T15 |
3 |
|
T81 |
1 |