Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10268	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9202	1			T3	17		T12	1		T15	38
len_5001_7500	14909	1			T3	17		T12	11		T15	36
len_2501_5000	9354	1			T3	17		T12	3		T15	36
len_1025_2500	5406	1			T3	10		T15	22		T16	20
len_769_1024	6427	1			T1	19		T3	2		T12	7
len_513_768	6712	1			T1	15		T3	2		T12	7
len_257_512	21007	1			T1	8		T3	2		T12	12
len_0_256	256570	1			T1	17		T2	9		T3	290
len_keccak_block_sizes[72]	721	1			T3	2		T15	3		T16	2
len_keccak_block_sizes[104]	627	1			T3	2		T15	3		T195	3
len_keccak_block_sizes[136]	519	1			T3	2		T15	3		T195	3
len_keccak_block_sizes[144]	419	1			T3	2		T15	3		T195	3
len_keccak_block_sizes[168]	311	1			T14	1		T15	3		T195	3
len_1	771	1			T3	2		T12	1		T13	2
len_0	1204	1			T3	2		T12	3		T13	4