Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100401937	1			T1	10315		T2	268		T3	222299
all_pins[1]	100401937	1			T1	10315		T2	268		T3	222299
all_pins[2]	100401937	1			T1	10315		T2	268		T3	222299

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300316062	1			T1	30607		T2	803		T3	666315
values[0x1]	889749	1			T1	338		T2	1		T3	582
transitions[0x0=>0x1]	887348	1			T1	338		T2	1		T3	582
transitions[0x1=>0x0]	887367	1			T1	338		T2	1		T3	582

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99894332	1			T1	10229		T2	267		T3	221717
all_pins[0]	values[0x1]	507605	1			T1	86		T2	1		T3	582
all_pins[0]	transitions[0x0=>0x1]	507593	1			T1	86		T2	1		T3	582
all_pins[0]	transitions[0x1=>0x0]	71	1			T49	3		T51	4		T181	3
all_pins[1]	values[0x0]	100401854	1			T1	10315		T2	268		T3	222299
all_pins[1]	values[0x1]	83	1			T49	3		T51	4		T181	3
all_pins[1]	transitions[0x0=>0x1]	71	1			T49	3		T51	4		T181	3
all_pins[1]	transitions[0x1=>0x0]	382049	1			T1	252		T27	3465		T28	21052
all_pins[2]	values[0x0]	100019876	1			T1	10063		T2	268		T3	222299
all_pins[2]	values[0x1]	382061	1			T1	252		T27	3465		T28	21052
all_pins[2]	transitions[0x0=>0x1]	379684	1			T1	252		T27	3450		T28	20913
all_pins[2]	transitions[0x1=>0x0]	505247	1			T1	86		T2	1		T3	582