Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	713	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5745	1			T1	4		T12	7		T14	13
len_601_800	13059	1			T1	22		T12	18		T14	29
len_401_600	8615	1			T1	13		T12	9		T14	16
len_201_400	16671	1			T1	8		T12	8		T14	6
len_65_200	73466	1			T1	4		T12	19		T13	70
len_min_for_xof_require_squeeze	998	1			T13	1		T15	10		T195	9
len_keccak_block_sizes[72]	749	1			T13	1		T15	5		T195	9
len_keccak_block_sizes[104]	754	1			T13	1		T15	5		T195	9
len_keccak_block_sizes[136]	761	1			T13	1		T15	5		T195	9
len_keccak_block_sizes[144]	286	1			T15	5		T81	5		T77	5
len_keccak_block_sizes[168]	294	1			T15	5		T81	5		T77	5
len_datapath_width	14120	1			T2	3		T12	6		T13	4
len_2_63	213498	1			T1	3		T2	6		T3	390
len_1	46	1			T13	2		T197	2		T46	1