Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101760698	1			T1	290		T2	102		T3	276
all_values[1]	101760698	1			T1	290		T2	102		T3	276
all_values[2]	101760698	1			T1	290		T2	102		T3	276

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636093

1

T1

12

T2

8

T3

6

auto[1]

304646001

1

T1

858

T2

298

T3

822

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303740595

1

T1

834

T2

306

T3

792

auto[1]

1541499

1

T1

36

T3

36

T13

669

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	219073	1			T2	1		T13	222		T14	5
all_values[0]	auto[0]	auto[1]	2192	1			T13	2		T14	6		T16	2
all_values[0]	auto[1]	auto[0]	101027792	1			T1	278		T2	101		T3	264
all_values[0]	auto[1]	auto[1]	511641	1			T1	12		T3	12		T13	221
all_values[1]	auto[0]	auto[0]	246234	1			T1	9		T2	3		T13	222
all_values[1]	auto[0]	auto[1]	1727	1			T1	3		T13	2		T16	4
all_values[1]	auto[1]	auto[0]	101000631	1			T1	269		T2	99		T3	264
all_values[1]	auto[1]	auto[1]	512106	1			T1	9		T3	12		T13	221
all_values[2]	auto[0]	auto[0]	165321	1			T2	4		T3	5		T13	587
all_values[2]	auto[0]	auto[1]	1546	1			T3	1		T13	6		T14	4
all_values[2]	auto[1]	auto[0]	101081544	1			T1	278		T2	98		T3	259
all_values[2]	auto[1]	auto[1]	512287	1			T1	12		T3	11		T13	217