Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
386878 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
2 | 
 | 
T3 | 
2 | 
| auto[1] | 
312882 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
200 | 
 | 
T3 | 
16 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
175477 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
46 | 
 | 
T3 | 
3 | 
| lower_val | 
173278 | 
1 | 
 | 
 | 
T2 | 
38 | 
 | 
T3 | 
8 | 
 | 
T13 | 
68 | 
| zero_val | 
1916 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
350488 | 
1 | 
 | 
 | 
T1 | 
14 | 
 | 
T2 | 
118 | 
 | 
T3 | 
6 | 
| lower_val | 
349262 | 
1 | 
 | 
 | 
T1 | 
4 | 
 | 
T2 | 
84 | 
 | 
T3 | 
12 | 
| zero_val | 
10 | 
1 | 
 | 
 | 
T93 | 
2 | 
 | 
T157 | 
2 | 
 | 
T158 | 
2 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
18 | 
4 | 
14 | 
77.78  | 
4 | 
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| [zero_val] | 
[zero_val] | 
* | 
-- | 
-- | 
2 | 
 | 
Uncovered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| [higher_val , lower_val] | 
[zero_val] | 
[auto[0]] | 
-- | 
-- | 
2 | 
 | 
Covered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
higher_val | 
auto[0] | 
48661 | 
1 | 
 | 
 | 
T13 | 
39 | 
 | 
T14 | 
82 | 
 | 
T17 | 
5 | 
| higher_val | 
higher_val | 
auto[1] | 
38941 | 
1 | 
 | 
 | 
T1 | 
4 | 
 | 
T2 | 
21 | 
 | 
T16 | 
107 | 
| higher_val | 
lower_val | 
auto[0] | 
48729 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T13 | 
57 | 
 | 
T14 | 
78 | 
| higher_val | 
lower_val | 
auto[1] | 
39142 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
24 | 
 | 
T3 | 
3 | 
| higher_val | 
zero_val | 
auto[1] | 
4 | 
1 | 
 | 
 | 
T157 | 
1 | 
 | 
T158 | 
1 | 
 | 
T159 | 
2 | 
| lower_val | 
higher_val | 
auto[0] | 
48093 | 
1 | 
 | 
 | 
T13 | 
31 | 
 | 
T14 | 
88 | 
 | 
T15 | 
5 | 
| lower_val | 
higher_val | 
auto[1] | 
38724 | 
1 | 
 | 
 | 
T2 | 
24 | 
 | 
T3 | 
3 | 
 | 
T16 | 
82 | 
| lower_val | 
lower_val | 
auto[0] | 
47668 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T13 | 
37 | 
 | 
T14 | 
67 | 
| lower_val | 
lower_val | 
auto[1] | 
38790 | 
1 | 
 | 
 | 
T2 | 
14 | 
 | 
T3 | 
4 | 
 | 
T16 | 
88 | 
| lower_val | 
zero_val | 
auto[1] | 
3 | 
1 | 
 | 
 | 
T93 | 
1 | 
 | 
T160 | 
2 | 
 | 
- | 
- | 
| zero_val | 
higher_val | 
auto[0] | 
715 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T13 | 
1 | 
 | 
T14 | 
1 | 
| zero_val | 
higher_val | 
auto[1] | 
228 | 
1 | 
 | 
 | 
T16 | 
1 | 
 | 
T65 | 
1 | 
 | 
T52 | 
2 | 
| zero_val | 
lower_val | 
auto[0] | 
732 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 | 
T15 | 
1 | 
| zero_val | 
lower_val | 
auto[1] | 
241 | 
1 | 
 | 
 | 
T16 | 
1 | 
 | 
T65 | 
1 | 
 | 
T93 | 
2 |