Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101760698	1			T1	290		T2	102		T3	276
all_pins[1]	101760698	1			T1	290		T2	102		T3	276
all_pins[2]	101760698	1			T1	290		T2	102		T3	276

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	304408777	1			T1	858		T2	306		T3	816
values[0x1]	873317	1			T1	12		T3	12		T13	221
transitions[0x0=>0x1]	871091	1			T1	12		T3	12		T13	221
transitions[0x1=>0x0]	871120	1			T1	12		T3	12		T13	221

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101249057	1			T1	278		T2	102		T3	264
all_pins[0]	values[0x1]	511641	1			T1	12		T3	12		T13	221
all_pins[0]	transitions[0x0=>0x1]	511624	1			T1	12		T3	12		T13	221
all_pins[0]	transitions[0x1=>0x0]	76	1			T41	4		T175	5		T176	3
all_pins[1]	values[0x0]	101760605	1			T1	290		T2	102		T3	276
all_pins[1]	values[0x1]	93	1			T41	4		T175	5		T176	3
all_pins[1]	transitions[0x0=>0x1]	77	1			T41	4		T175	5		T176	3
all_pins[1]	transitions[0x1=>0x0]	361567	1			T32	246		T24	576		T33	444
all_pins[2]	values[0x0]	101399115	1			T1	290		T2	102		T3	276
all_pins[2]	values[0x1]	361583	1			T32	246		T24	576		T33	444
all_pins[2]	transitions[0x0=>0x1]	359390	1			T32	245		T24	576		T33	444
all_pins[2]	transitions[0x1=>0x0]	509477	1			T1	12		T3	12		T13	221