Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99217343	1			T1	208765		T2	220667		T3	8077
all_values[1]	99217343	1			T1	208765		T2	220667		T3	8077
all_values[2]	99217343	1			T1	208765		T2	220667		T3	8077

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

528788

1

T1

10

T2

10

T3

193

auto[1]

297123241

1

T1

626285

T2

661991

T3

24038

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296125425

1

T1

624657

T2

660276

T3

23985

auto[1]

1526604

1

T1

1638

T2

1725

T3

246

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	164814	1			T2	1		T18	5		T19	1
all_values[0]	auto[0]	auto[1]	2058	1			T2	2		T18	6		T19	2
all_values[0]	auto[1]	auto[0]	98543661	1			T1	208219		T2	220091		T3	7995
all_values[0]	auto[1]	auto[1]	506810	1			T1	546		T2	573		T3	82
all_values[1]	auto[0]	auto[0]	181037	1			T1	2		T2	4		T3	191
all_values[1]	auto[0]	auto[1]	1669	1			T1	1		T2	3		T3	2
all_values[1]	auto[1]	auto[0]	98527438	1			T1	208217		T2	220088		T3	7804
all_values[1]	auto[1]	auto[1]	507199	1			T1	545		T2	572		T3	80
all_values[2]	auto[0]	auto[0]	177690	1			T1	5		T13	5		T15	7732
all_values[2]	auto[0]	auto[1]	1520	1			T1	2		T13	2		T15	8
all_values[2]	auto[1]	auto[0]	98530785	1			T1	208214		T2	220092		T3	7995
all_values[2]	auto[1]	auto[1]	507348	1			T1	544		T2	575		T3	82