Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99217343	1			T1	208765		T2	220667		T3	8077
all_pins[1]	99217343	1			T1	208765		T2	220667		T3	8077
all_pins[2]	99217343	1			T1	208765		T2	220667		T3	8077

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296848712	1			T1	625749		T2	661428		T3	24149
values[0x1]	803317	1			T1	546		T2	573		T3	82
transitions[0x0=>0x1]	801486	1			T1	546		T2	573		T3	82
transitions[0x1=>0x0]	801506	1			T1	546		T2	573		T3	82

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98710533	1			T1	208219		T2	220094		T3	7995
all_pins[0]	values[0x1]	506810	1			T1	546		T2	573		T3	82
all_pins[0]	transitions[0x0=>0x1]	506800	1			T1	546		T2	573		T3	82
all_pins[0]	transitions[0x1=>0x0]	57	1			T158	2		T85	3		T176	4
all_pins[1]	values[0x0]	99217276	1			T1	208765		T2	220667		T3	8077
all_pins[1]	values[0x1]	67	1			T158	2		T85	3		T176	4
all_pins[1]	transitions[0x0=>0x1]	52	1			T158	2		T85	3		T176	4
all_pins[1]	transitions[0x1=>0x0]	296425	1			T14	1680		T27	16141		T28	2669
all_pins[2]	values[0x0]	98920903	1			T1	208765		T2	220667		T3	8077
all_pins[2]	values[0x1]	296440	1			T14	1680		T27	16141		T28	2669
all_pins[2]	transitions[0x0=>0x1]	294634	1			T14	1680		T27	16037		T28	2653
all_pins[2]	transitions[0x1=>0x0]	505024	1			T1	546		T2	573		T3	82