Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	649	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5280	1			T3	6		T14	20		T15	24
len_601_800	12100	1			T3	26		T14	56		T15	66
len_401_600	7991	1			T3	12		T14	27		T15	54
len_201_400	16347	1			T3	5		T14	16		T15	18
len_65_200	73828	1			T3	1		T14	5		T15	14
len_min_for_xof_require_squeeze	1007	1			T18	9		T39	9		T62	9
len_keccak_block_sizes[72]	750	1			T18	9		T39	9		T62	9
len_keccak_block_sizes[104]	744	1			T18	9		T39	9		T62	9
len_keccak_block_sizes[136]	759	1			T18	9		T39	9		T62	9
len_keccak_block_sizes[144]	282	1			T66	5		T193	1		T92	2
len_keccak_block_sizes[168]	276	1			T66	5		T92	2		T194	5
len_datapath_width	14056	1			T15	3		T18	9		T39	9
len_2_63	214608	1			T1	374		T2	390		T3	38
len_1	59	1			T100	1		T92	1		T195	1