Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100743314	1			T1	771		T2	2364		T3	454269
all_values[1]	100743314	1			T1	771		T2	2364		T3	454269
all_values[2]	100743314	1			T1	771		T2	2364		T3	454269

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

538409

1

T1

388

T2

14

T3

10

auto[1]

301691533

1

T1

1925

T2

7078

T3

136279

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300689229

1

T1

2301

T2

7029

T3

135263

auto[1]

1540713

1

T1

12

T2

63

T3

10173

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	161947	1			T2	12		T3	1		T12	927
all_values[0]	auto[0]	auto[1]	2031	1			T2	2		T3	2		T12	14
all_values[0]	auto[1]	auto[0]	100067796	1			T1	767		T2	2331		T3	450877
all_values[0]	auto[1]	auto[1]	511540	1			T1	4		T2	19		T3	3389
all_values[1]	auto[0]	auto[0]	175194	1			T3	4		T12	959		T13	10
all_values[1]	auto[0]	auto[1]	1586	1			T3	3		T12	13		T13	4
all_values[1]	auto[1]	auto[0]	100054549	1			T1	767		T2	2343		T3	450874
all_values[1]	auto[1]	auto[1]	511985	1			T1	4		T2	21		T3	3388
all_values[2]	auto[0]	auto[0]	195977	1			T1	385		T12	5746		T14	629
all_values[2]	auto[0]	auto[1]	1674	1			T1	3		T12	34		T14	2
all_values[2]	auto[1]	auto[0]	100033766	1			T1	382		T2	2343		T3	450878
all_values[2]	auto[1]	auto[1]	511897	1			T1	1		T2	21		T3	3391