Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
373992 |
1 |
|
|
T1 |
16 |
|
T2 |
32 |
|
T3 |
4530 |
auto[1] |
324552 |
1 |
|
|
T12 |
402 |
|
T25 |
414 |
|
T36 |
206 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175232 |
1 |
|
|
T1 |
4 |
|
T3 |
1194 |
|
T12 |
201 |
lower_val |
172480 |
1 |
|
|
T1 |
5 |
|
T2 |
13 |
|
T3 |
1106 |
zero_val |
1817 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
349886 |
1 |
|
|
T1 |
6 |
|
T2 |
18 |
|
T3 |
2318 |
lower_val |
348648 |
1 |
|
|
T1 |
10 |
|
T2 |
14 |
|
T3 |
2212 |
zero_val |
10 |
1 |
|
|
T149 |
2 |
|
T150 |
2 |
|
T151 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47156 |
1 |
|
|
T1 |
1 |
|
T3 |
613 |
|
T12 |
40 |
higher_val |
higher_val |
auto[1] |
40616 |
1 |
|
|
T12 |
63 |
|
T25 |
56 |
|
T36 |
37 |
higher_val |
lower_val |
auto[0] |
46827 |
1 |
|
|
T1 |
3 |
|
T3 |
581 |
|
T12 |
44 |
higher_val |
lower_val |
auto[1] |
40628 |
1 |
|
|
T12 |
54 |
|
T25 |
53 |
|
T36 |
22 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T151 |
1 |
|
T152 |
2 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T150 |
2 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
46163 |
1 |
|
|
T1 |
2 |
|
T2 |
8 |
|
T3 |
546 |
lower_val |
higher_val |
auto[1] |
40319 |
1 |
|
|
T12 |
52 |
|
T25 |
54 |
|
T36 |
25 |
lower_val |
lower_val |
auto[0] |
45916 |
1 |
|
|
T1 |
3 |
|
T2 |
5 |
|
T3 |
560 |
lower_val |
lower_val |
auto[1] |
40081 |
1 |
|
|
T12 |
46 |
|
T25 |
54 |
|
T36 |
23 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T149 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
715 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T12 |
2 |
zero_val |
higher_val |
auto[1] |
211 |
1 |
|
|
T12 |
3 |
|
T25 |
2 |
|
T27 |
2 |
zero_val |
lower_val |
auto[0] |
671 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T12 |
3 |
zero_val |
lower_val |
auto[1] |
220 |
1 |
|
|
T12 |
3 |
|
T25 |
2 |
|
T36 |
1 |