Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100743314	1			T1	771		T2	2364		T3	454269
all_pins[1]	100743314	1			T1	771		T2	2364		T3	454269
all_pins[2]	100743314	1			T1	771		T2	2364		T3	454269

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301492774	1			T1	2309		T2	7073		T3	135941
values[0x1]	737168	1			T1	4		T2	19		T3	3389
transitions[0x0=>0x1]	735809	1			T1	4		T2	19		T3	3389
transitions[0x1=>0x0]	735831	1			T1	4		T2	19		T3	3389

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100231774	1			T1	767		T2	2345		T3	450880
all_pins[0]	values[0x1]	511540	1			T1	4		T2	19		T3	3389
all_pins[0]	transitions[0x0=>0x1]	511525	1			T1	4		T2	19		T3	3389
all_pins[0]	transitions[0x1=>0x0]	95	1			T38	3		T163	2		T46	8
all_pins[1]	values[0x0]	100743204	1			T1	771		T2	2364		T3	454269
all_pins[1]	values[0x1]	110	1			T38	3		T163	2		T46	8
all_pins[1]	transitions[0x0=>0x1]	95	1			T38	3		T163	2		T46	8
all_pins[1]	transitions[0x1=>0x0]	225503	1			T12	4829		T14	133		T25	5856
all_pins[2]	values[0x0]	100517796	1			T1	771		T2	2364		T3	454269
all_pins[2]	values[0x1]	225518	1			T12	4829		T14	133		T25	5856
all_pins[2]	transitions[0x0=>0x1]	224189	1			T12	4798		T14	133		T25	5817
all_pins[2]	transitions[0x1=>0x0]	510233	1			T1	4		T2	19		T3	3389