Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	680	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5579	1			T2	1		T12	50		T14	7
len_601_800	12826	1			T1	2		T2	4		T12	79
len_401_600	8579	1			T2	4		T12	63		T14	15
len_201_400	16587	1			T1	1		T2	3		T3	251
len_65_200	74539	1			T1	1		T2	2		T3	680
len_min_for_xof_require_squeeze	1009	1			T3	10		T16	10		T25	1
len_keccak_block_sizes[72]	778	1			T3	5		T12	1		T16	5
len_keccak_block_sizes[104]	762	1			T3	5		T16	5		T36	1
len_keccak_block_sizes[136]	752	1			T3	5		T16	5		T25	1
len_keccak_block_sizes[144]	279	1			T3	5		T16	5		T25	1
len_keccak_block_sizes[168]	286	1			T3	5		T16	5		T87	2
len_datapath_width	14141	1			T3	5		T12	10		T13	3
len_2_63	215012	1			T1	3		T3	1329		T12	89
len_1	60	1			T39	1		T127	1		T178	1