Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10933617 |
1 |
|
|
T1 |
632 |
|
T2 |
2601 |
|
T3 |
47900 |
auto[1] |
26034151 |
1 |
|
|
T1 |
1028 |
|
T2 |
3920 |
|
T3 |
141800 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36846989 |
1 |
|
|
T1 |
1658 |
|
T2 |
6507 |
|
T3 |
188764 |
triple_byte_access |
39915 |
1 |
|
|
T2 |
4 |
|
T3 |
310 |
|
T12 |
94 |
halfword_access |
40744 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T3 |
316 |
byte_access |
40120 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T3 |
310 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10812838 |
1 |
|
|
T1 |
630 |
|
T2 |
2587 |
|
T3 |
46964 |
auto[0] |
triple_byte_access |
39915 |
1 |
|
|
T2 |
4 |
|
T3 |
310 |
|
T12 |
94 |
auto[0] |
halfword_access |
40744 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T3 |
316 |
auto[0] |
byte_access |
40120 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T3 |
310 |
auto[1] |
word_access |
26034151 |
1 |
|
|
T1 |
1028 |
|
T2 |
3920 |
|
T3 |
141800 |