Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100858002	1			T1	806		T2	449825		T3	10571
all_values[1]	100858002	1			T1	806		T2	449825		T3	10571
all_values[2]	100858002	1			T1	806		T2	449825		T3	10571

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

527951

1

T2

6

T3

80

T12

3

auto[1]

302046055

1

T1

2418

T2

134946

T3

31633

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301043565

1

T1

2079

T2

133925

T3

31431

auto[1]

1530441

1

T1

339

T2

10221

T3

282

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	182389	1			T2	1		T3	78		T12	1
all_values[0]	auto[0]	auto[1]	2086	1			T2	2		T3	2		T12	2
all_values[0]	auto[1]	auto[0]	100165466	1			T1	693		T2	446417		T3	10399
all_values[0]	auto[1]	auto[1]	508061	1			T1	113		T2	3405		T3	92
all_values[1]	auto[0]	auto[0]	162125	1			T2	1		T14	5		T4	1
all_values[1]	auto[0]	auto[1]	1624	1			T2	2		T14	1		T17	5
all_values[1]	auto[1]	auto[0]	100185730	1			T1	693		T2	446417		T3	10477
all_values[1]	auto[1]	auto[1]	508523	1			T1	113		T2	3405		T3	94
all_values[2]	auto[0]	auto[0]	178117	1			T13	2		T15	2		T16	130
all_values[2]	auto[0]	auto[1]	1610	1			T13	1		T15	1		T16	1
all_values[2]	auto[1]	auto[0]	100169738	1			T1	693		T2	446418		T3	10477
all_values[2]	auto[1]	auto[1]	508537	1			T1	113		T2	3407		T3	94