Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100858002	1			T1	806		T2	449825		T3	10571
all_pins[1]	100858002	1			T1	806		T2	449825		T3	10571
all_pins[2]	100858002	1			T1	806		T2	449825		T3	10571

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301768493	1			T1	2305		T2	134607		T3	31621
values[0x1]	805513	1			T1	113		T2	3405		T3	92
transitions[0x0=>0x1]	803737	1			T1	113		T2	3405		T3	92
transitions[0x1=>0x0]	803757	1			T1	113		T2	3405		T3	92

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100349941	1			T1	693		T2	446420		T3	10479
all_pins[0]	values[0x1]	508061	1			T1	113		T2	3405		T3	92
all_pins[0]	transitions[0x0=>0x1]	508053	1			T1	113		T2	3405		T3	92
all_pins[0]	transitions[0x1=>0x0]	58	1			T150	2		T151	2		T152	2
all_pins[1]	values[0x0]	100857936	1			T1	806		T2	449825		T3	10571
all_pins[1]	values[0x1]	66	1			T150	2		T151	2		T152	2
all_pins[1]	transitions[0x0=>0x1]	54	1			T150	2		T151	2		T152	2
all_pins[1]	transitions[0x1=>0x0]	297374	1			T16	226		T22	342		T27	9702
all_pins[2]	values[0x0]	100560616	1			T1	806		T2	449825		T3	10571
all_pins[2]	values[0x1]	297386	1			T16	226		T22	342		T27	9702
all_pins[2]	transitions[0x0=>0x1]	295630	1			T16	226		T22	342		T27	9639
all_pins[2]	transitions[0x1=>0x0]	506325	1			T1	113		T2	3405		T3	92