Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	655	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5593	1			T3	13		T14	31		T16	13
len_601_800	12551	1			T3	26		T14	51		T16	39
len_401_600	8365	1			T3	12		T14	45		T16	15
len_201_400	16550	1			T2	251		T3	6		T14	18
len_65_200	73417	1			T1	28		T2	680		T3	6
len_min_for_xof_require_squeeze	995	1			T2	10		T18	1		T64	9
len_keccak_block_sizes[72]	748	1			T1	1		T2	5		T14	1
len_keccak_block_sizes[104]	755	1			T1	3		T2	5		T18	1
len_keccak_block_sizes[136]	749	1			T2	5		T64	9		T164	5
len_keccak_block_sizes[144]	277	1			T2	5		T164	5		T165	1
len_keccak_block_sizes[168]	280	1			T2	5		T164	5		T166	5
len_datapath_width	14154	1			T1	5		T2	5		T13	246
len_2_63	214616	1			T1	42		T2	1329		T3	1
len_1	45	1			T1	1		T28	1		T167	1