Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 278 1 T96 4 T97 7 T98 7
all_values[1] 278 1 T96 4 T97 7 T98 7
all_values[2] 278 1 T96 4 T97 7 T98 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 470 1 T96 7 T97 14 T98 14
auto[1] 364 1 T96 5 T97 7 T98 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 402 1 T96 5 T97 6 T98 8
auto[1] 432 1 T96 7 T97 15 T98 13


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 514 1 T96 7 T97 9 T98 12
auto[1] 320 1 T96 5 T97 12 T98 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 64 1 T97 1 T143 1 T126 2
all_values[0] auto[0] auto[0] auto[1] 34 1 T96 2 T97 2 T98 3
all_values[0] auto[0] auto[1] auto[0] 55 1 T97 2 T143 1 T144 1
all_values[0] auto[0] auto[1] auto[1] 19 1 T145 1 T146 3 T147 3
all_values[0] auto[1] auto[0] auto[1] 64 1 T96 2 T98 3 T143 1
all_values[0] auto[1] auto[1] auto[1] 42 1 T97 2 T98 1 T148 2
all_values[1] auto[0] auto[0] auto[0] 98 1 T98 4 T143 2 T126 4
all_values[1] auto[0] auto[1] auto[0] 81 1 T96 3 T97 2 T98 1
all_values[1] auto[1] auto[0] auto[1] 63 1 T96 1 T97 5 T98 2
all_values[1] auto[1] auto[1] auto[1] 36 1 T149 2 T148 1 T145 1
all_values[2] auto[0] auto[0] auto[0] 58 1 T97 1 T98 1 T144 1
all_values[2] auto[0] auto[0] auto[1] 26 1 T97 1 T126 3 T144 1
all_values[2] auto[0] auto[1] auto[0] 46 1 T96 2 T98 2 T145 1
all_values[2] auto[0] auto[1] auto[1] 33 1 T98 1 T143 2 T126 1
all_values[2] auto[1] auto[0] auto[1] 63 1 T96 2 T97 4 T98 1
all_values[2] auto[1] auto[1] auto[1] 52 1 T97 1 T98 2 T143 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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