Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100157864	1			T1	11690		T2	213101		T3	9580
all_values[1]	100157864	1			T1	11690		T2	213101		T3	9580
all_values[2]	100157864	1			T1	11690		T2	213101		T3	9580

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

536207

1

T1

71

T2

3

T3

866

auto[1]

299937385

1

T1

34999

T2

639300

T3

27874

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298932543

1

T1

34677

T2

637653

T3

28437

auto[1]

1541049

1

T1

393

T2

1650

T3

303

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	169882	1			T2	1		T3	429		T4	5
all_values[0]	auto[0]	auto[1]	2207	1			T2	2		T3	4		T16	6
all_values[0]	auto[1]	auto[0]	99474299	1			T1	11559		T2	212550		T3	9050
all_values[0]	auto[1]	auto[1]	511476	1			T1	131		T2	548		T3	97
all_values[1]	auto[0]	auto[0]	174595	1			T13	7		T14	2		T16	1
all_values[1]	auto[0]	auto[1]	1707	1			T13	1		T14	1		T16	2
all_values[1]	auto[1]	auto[0]	99469586	1			T1	11559		T2	212551		T3	9479
all_values[1]	auto[1]	auto[1]	511976	1			T1	131		T2	550		T3	101
all_values[2]	auto[0]	auto[0]	186161	1			T1	70		T3	429		T13	7
all_values[2]	auto[0]	auto[1]	1655	1			T1	1		T3	4		T13	1
all_values[2]	auto[1]	auto[0]	99458020	1			T1	11489		T2	212551		T3	9050
all_values[2]	auto[1]	auto[1]	512028	1			T1	130		T2	550		T3	97