Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100157864	1			T1	11690		T2	213101		T3	9580
all_pins[1]	100157864	1			T1	11690		T2	213101		T3	9580
all_pins[2]	100157864	1			T1	11690		T2	213101		T3	9580

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299595413	1			T1	34939		T2	638755		T3	28643
values[0x1]	878179	1			T1	131		T2	548		T3	97
transitions[0x0=>0x1]	875884	1			T1	131		T2	548		T3	97
transitions[0x1=>0x0]	875907	1			T1	131		T2	548		T3	97

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99646388	1			T1	11559		T2	212553		T3	9483
all_pins[0]	values[0x1]	511476	1			T1	131		T2	548		T3	97
all_pins[0]	transitions[0x0=>0x1]	511460	1			T1	131		T2	548		T3	97
all_pins[0]	transitions[0x1=>0x0]	60	1			T77	4		T158	2		T159	3
all_pins[1]	values[0x0]	100157788	1			T1	11690		T2	213101		T3	9580
all_pins[1]	values[0x1]	76	1			T77	4		T158	2		T159	3
all_pins[1]	transitions[0x0=>0x1]	62	1			T77	4		T158	2		T159	3
all_pins[1]	transitions[0x1=>0x0]	366613	1			T18	4581		T30	606		T26	7125
all_pins[2]	values[0x0]	99791237	1			T1	11690		T2	213101		T3	9580
all_pins[2]	values[0x1]	366627	1			T18	4581		T30	606		T26	7125
all_pins[2]	transitions[0x0=>0x1]	364362	1			T18	4554		T30	605		T26	7086
all_pins[2]	transitions[0x1=>0x0]	509234	1			T1	131		T2	548		T3	97