Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	702	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5715	1			T1	13		T3	14		T15	17
len_601_800	12978	1			T1	36		T3	20		T15	37
len_401_600	8561	1			T1	23		T3	12		T15	22
len_201_400	16646	1			T1	10		T3	11		T14	251
len_65_200	74114	1			T1	3		T3	2		T14	680
len_min_for_xof_require_squeeze	1003	1			T14	10		T18	1		T84	9
len_keccak_block_sizes[72]	764	1			T14	5		T23	1		T84	9
len_keccak_block_sizes[104]	763	1			T14	5		T18	1		T84	9
len_keccak_block_sizes[136]	756	1			T14	5		T84	9		T169	9
len_keccak_block_sizes[144]	283	1			T14	5		T65	5		T170	2
len_keccak_block_sizes[168]	274	1			T14	5		T61	1		T65	5
len_datapath_width	14281	1			T13	3		T14	5		T15	1
len_2_63	216165	1			T1	37		T2	374		T3	5
len_1	51	1			T19	2		T170	2		T171	3