Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10998020 |
1 |
|
|
T1 |
16515 |
|
T2 |
2992 |
|
T3 |
10466 |
auto[1] |
26158988 |
1 |
|
|
T1 |
24432 |
|
T2 |
18700 |
|
T3 |
15724 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
37036662 |
1 |
|
|
T1 |
40875 |
|
T2 |
21692 |
|
T3 |
26141 |
triple_byte_access |
40034 |
1 |
|
|
T1 |
19 |
|
T3 |
23 |
|
T14 |
310 |
halfword_access |
40399 |
1 |
|
|
T1 |
20 |
|
T3 |
12 |
|
T14 |
316 |
byte_access |
39913 |
1 |
|
|
T1 |
33 |
|
T3 |
14 |
|
T14 |
310 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10877674 |
1 |
|
|
T1 |
16443 |
|
T2 |
2992 |
|
T3 |
10417 |
auto[0] |
triple_byte_access |
40034 |
1 |
|
|
T1 |
19 |
|
T3 |
23 |
|
T14 |
310 |
auto[0] |
halfword_access |
40399 |
1 |
|
|
T1 |
20 |
|
T3 |
12 |
|
T14 |
316 |
auto[0] |
byte_access |
39913 |
1 |
|
|
T1 |
33 |
|
T3 |
14 |
|
T14 |
310 |
auto[1] |
word_access |
26158988 |
1 |
|
|
T1 |
24432 |
|
T2 |
18700 |
|
T3 |
15724 |