Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101413178	1			T1	27892		T2	164677		T3	221686
all_values[1]	101413178	1			T1	27892		T2	164677		T3	221686
all_values[2]	101413178	1			T1	27892		T2	164677		T3	221686

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577912

1

T1

717

T2

13

T3

3

auto[1]

303661622

1

T1

82959

T2

494018

T3

665055

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302710137

1

T1

82863

T2

492615

T3

663318

auto[1]

1529397

1

T1

813

T2

1416

T3

1740

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	185272	1			T1	237		T2	1		T12	4
all_values[0]	auto[0]	auto[1]	2133	1			T1	2		T2	2		T12	2
all_values[0]	auto[1]	auto[0]	100718107	1			T1	27384		T2	164204		T3	221106
all_values[0]	auto[1]	auto[1]	507666	1			T1	269		T2	470		T3	580
all_values[1]	auto[0]	auto[0]	192732	1			T1	237		T2	4		T4	195
all_values[1]	auto[0]	auto[1]	1543	1			T1	2		T2	3		T4	1
all_values[1]	auto[1]	auto[0]	100710647	1			T1	27384		T2	164201		T3	221106
all_values[1]	auto[1]	auto[1]	508256	1			T1	269		T2	469		T3	580
all_values[2]	auto[0]	auto[0]	194592	1			T1	237		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	1640	1			T1	2		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	100708787	1			T1	27384		T2	164204		T3	221104
all_values[2]	auto[1]	auto[1]	508159	1			T1	269		T2	470		T3	579