Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
360566 | 
1 | 
 | 
 | 
T1 | 
372 | 
 | 
T2 | 
620 | 
 | 
T3 | 
780 | 
| auto[1] | 
333174 | 
1 | 
 | 
 | 
T4 | 
36 | 
 | 
T15 | 
30 | 
 | 
T17 | 
490 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
174378 | 
1 | 
 | 
 | 
T1 | 
84 | 
 | 
T2 | 
149 | 
 | 
T3 | 
182 | 
| lower_val | 
171755 | 
1 | 
 | 
 | 
T1 | 
87 | 
 | 
T2 | 
160 | 
 | 
T3 | 
210 | 
| zero_val | 
1851 | 
1 | 
 | 
 | 
T1 | 
3 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
346460 | 
1 | 
 | 
 | 
T1 | 
196 | 
 | 
T2 | 
306 | 
 | 
T3 | 
422 | 
| lower_val | 
347274 | 
1 | 
 | 
 | 
T1 | 
176 | 
 | 
T2 | 
314 | 
 | 
T3 | 
358 | 
| zero_val | 
6 | 
1 | 
 | 
 | 
T133 | 
2 | 
 | 
T134 | 
2 | 
 | 
T135 | 
2 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
18 | 
4 | 
14 | 
77.78  | 
4 | 
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| [zero_val] | 
[zero_val] | 
* | 
-- | 
-- | 
2 | 
 | 
Uncovered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| [higher_val , lower_val] | 
[zero_val] | 
[auto[0]] | 
-- | 
-- | 
2 | 
 | 
Covered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
higher_val | 
auto[0] | 
45112 | 
1 | 
 | 
 | 
T1 | 
44 | 
 | 
T2 | 
66 | 
 | 
T3 | 
96 | 
| higher_val | 
higher_val | 
auto[1] | 
42090 | 
1 | 
 | 
 | 
T4 | 
5 | 
 | 
T15 | 
3 | 
 | 
T17 | 
49 | 
| higher_val | 
lower_val | 
auto[0] | 
45509 | 
1 | 
 | 
 | 
T1 | 
40 | 
 | 
T2 | 
83 | 
 | 
T3 | 
86 | 
| higher_val | 
lower_val | 
auto[1] | 
41665 | 
1 | 
 | 
 | 
T4 | 
3 | 
 | 
T15 | 
3 | 
 | 
T17 | 
73 | 
| higher_val | 
zero_val | 
auto[1] | 
2 | 
1 | 
 | 
 | 
T133 | 
1 | 
 | 
T135 | 
1 | 
 | 
- | 
- | 
| lower_val | 
higher_val | 
auto[0] | 
44542 | 
1 | 
 | 
 | 
T1 | 
40 | 
 | 
T2 | 
83 | 
 | 
T3 | 
116 | 
| lower_val | 
higher_val | 
auto[1] | 
41161 | 
1 | 
 | 
 | 
T4 | 
6 | 
 | 
T15 | 
7 | 
 | 
T17 | 
65 | 
| lower_val | 
lower_val | 
auto[0] | 
44954 | 
1 | 
 | 
 | 
T1 | 
47 | 
 | 
T2 | 
77 | 
 | 
T3 | 
94 | 
| lower_val | 
lower_val | 
auto[1] | 
41097 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T15 | 
5 | 
 | 
T17 | 
62 | 
| lower_val | 
zero_val | 
auto[1] | 
1 | 
1 | 
 | 
 | 
T133 | 
1 | 
 | 
- | 
- | 
 | 
- | 
- | 
| zero_val | 
higher_val | 
auto[0] | 
669 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T12 | 
1 | 
 | 
T14 | 
1 | 
| zero_val | 
higher_val | 
auto[1] | 
225 | 
1 | 
 | 
 | 
T17 | 
1 | 
 | 
T43 | 
1 | 
 | 
T136 | 
1 | 
| zero_val | 
lower_val | 
auto[0] | 
711 | 
1 | 
 | 
 | 
T1 | 
3 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
| zero_val | 
lower_val | 
auto[1] | 
246 | 
1 | 
 | 
 | 
T17 | 
3 | 
 | 
T43 | 
1 | 
 | 
T136 | 
3 |