Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10355	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9007	1			T2	24		T3	17		T14	31
len_5001_7500	14537	1			T2	24		T3	17		T14	84
len_2501_5000	9236	1			T2	24		T3	17		T14	19
len_1025_2500	5404	1			T2	14		T3	10		T14	8
len_769_1024	6398	1			T1	52		T2	2		T3	2
len_513_768	6728	1			T1	39		T2	3		T3	2
len_257_512	21164	1			T1	41		T2	2		T3	2
len_0_256	257101	1			T1	54		T2	211		T3	290
len_keccak_block_sizes[72]	732	1			T2	2		T3	2		T16	2
len_keccak_block_sizes[104]	621	1			T2	2		T3	2		T16	2
len_keccak_block_sizes[136]	514	1			T1	1		T3	2		T16	2
len_keccak_block_sizes[144]	424	1			T1	1		T3	2		T16	2
len_keccak_block_sizes[168]	325	1			T41	3		T42	3		T43	3
len_1	749	1			T2	2		T3	2		T16	2
len_0	1177	1			T2	2		T3	2		T14	5