Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101413178	1			T1	27892		T2	164677		T3	221686
all_pins[1]	101413178	1			T1	27892		T2	164677		T3	221686
all_pins[2]	101413178	1			T1	27892		T2	164677		T3	221686

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	303458786	1			T1	83407		T2	493561		T3	664478
values[0x1]	780748	1			T1	269		T2	470		T3	580
transitions[0x0=>0x1]	779117	1			T1	269		T2	470		T3	580
transitions[0x1=>0x0]	779147	1			T1	269		T2	470		T3	580

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100905512	1			T1	27623		T2	164207		T3	221106
all_pins[0]	values[0x1]	507666	1			T1	269		T2	470		T3	580
all_pins[0]	transitions[0x0=>0x1]	507649	1			T1	269		T2	470		T3	580
all_pins[0]	transitions[0x1=>0x0]	76	1			T47	2		T69	2		T151	8
all_pins[1]	values[0x0]	101413085	1			T1	27892		T2	164677		T3	221686
all_pins[1]	values[0x1]	93	1			T47	2		T69	2		T151	8
all_pins[1]	transitions[0x0=>0x1]	79	1			T47	2		T69	2		T151	8
all_pins[1]	transitions[0x1=>0x0]	272975	1			T40	1		T46	1236		T25	6570
all_pins[2]	values[0x0]	101140189	1			T1	27892		T2	164677		T3	221686
all_pins[2]	values[0x1]	272989	1			T40	1		T46	1236		T25	6570
all_pins[2]	transitions[0x0=>0x1]	271389	1			T40	1		T46	1236		T25	6525
all_pins[2]	transitions[0x1=>0x0]	506096	1			T1	269		T2	470		T3	580