Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	676	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5547	1			T1	25		T14	33		T4	1
len_601_800	12621	1			T1	75		T14	48		T4	2
len_401_600	8277	1			T1	32		T14	37		T4	2
len_201_400	16593	1			T1	29		T14	21		T4	1
len_65_200	73479	1			T1	12		T14	11		T15	8
len_min_for_xof_require_squeeze	1001	1			T41	9		T42	9		T43	9
len_keccak_block_sizes[72]	749	1			T14	1		T41	9		T42	9
len_keccak_block_sizes[104]	745	1			T41	9		T42	9		T43	9
len_keccak_block_sizes[136]	750	1			T14	1		T41	9		T42	9
len_keccak_block_sizes[144]	293	1			T165	5		T166	5		T74	5
len_keccak_block_sizes[168]	282	1			T121	1		T165	5		T166	5
len_datapath_width	14102	1			T1	1		T12	3		T14	1
len_2_63	214346	1			T1	7		T2	310		T3	390
len_1	56	1			T167	1		T29	1		T49	1