Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100841753	1			T1	3061		T2	575693		T3	25486
all_values[1]	100841753	1			T1	3061		T2	575693		T3	25486
all_values[2]	100841753	1			T1	3061		T2	575693		T3	25486

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

558479

1

T1

24

T2

7

T3

159

auto[1]

301966780

1

T1

9159

T2

172707

T3

76299

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300988314

1

T1

8319

T2

171657

T3

75663

auto[1]

1536945

1

T1

864

T2

10509

T3

795

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	180474	1			T2	3		T3	51		T12	1
all_values[0]	auto[0]	auto[1]	2042	1			T2	4		T3	2		T12	2
all_values[0]	auto[1]	auto[0]	100148964	1			T1	2773		T2	572187		T3	25170
all_values[0]	auto[1]	auto[1]	510273	1			T1	288		T2	3499		T3	263
all_values[1]	auto[0]	auto[0]	167820	1			T1	11		T3	51		T12	1
all_values[1]	auto[0]	auto[1]	1592	1			T1	1		T3	2		T12	2
all_values[1]	auto[1]	auto[0]	100161618	1			T1	2762		T2	572190		T3	25170
all_values[1]	auto[1]	auto[1]	510723	1			T1	287		T2	3503		T3	263
all_values[2]	auto[0]	auto[0]	204828	1			T1	11		T3	51		T12	4
all_values[2]	auto[0]	auto[1]	1723	1			T1	1		T3	2		T12	3
all_values[2]	auto[1]	auto[0]	100124610	1			T1	2762		T2	572190		T3	25170
all_values[2]	auto[1]	auto[1]	510592	1			T1	287		T2	3503		T3	263