Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
320770 |
1 |
|
|
T1 |
376 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
375030 |
1 |
|
|
T2 |
4672 |
|
T3 |
342 |
|
T12 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174393 |
1 |
|
|
T1 |
103 |
|
T2 |
1217 |
|
T3 |
80 |
lower_val |
171857 |
1 |
|
|
T1 |
92 |
|
T2 |
1130 |
|
T3 |
94 |
zero_val |
1886 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347048 |
1 |
|
|
T1 |
180 |
|
T2 |
2326 |
|
T3 |
164 |
lower_val |
348740 |
1 |
|
|
T1 |
196 |
|
T2 |
2348 |
|
T3 |
180 |
zero_val |
12 |
1 |
|
|
T58 |
2 |
|
T158 |
2 |
|
T159 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40079 |
1 |
|
|
T1 |
47 |
|
T13 |
99 |
|
T14 |
114 |
higher_val |
higher_val |
auto[1] |
46928 |
1 |
|
|
T2 |
607 |
|
T3 |
35 |
|
T12 |
86 |
higher_val |
lower_val |
auto[0] |
39997 |
1 |
|
|
T1 |
56 |
|
T3 |
1 |
|
T13 |
79 |
higher_val |
lower_val |
auto[1] |
47388 |
1 |
|
|
T2 |
610 |
|
T3 |
44 |
|
T12 |
89 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T160 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
39285 |
1 |
|
|
T1 |
42 |
|
T2 |
1 |
|
T13 |
98 |
lower_val |
higher_val |
auto[1] |
46289 |
1 |
|
|
T2 |
571 |
|
T3 |
55 |
|
T12 |
80 |
lower_val |
lower_val |
auto[0] |
39793 |
1 |
|
|
T1 |
50 |
|
T12 |
1 |
|
T13 |
92 |
lower_val |
lower_val |
auto[1] |
46484 |
1 |
|
|
T2 |
558 |
|
T3 |
39 |
|
T12 |
99 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T158 |
1 |
|
T159 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
4 |
1 |
|
|
T58 |
2 |
|
T160 |
1 |
|
T161 |
1 |
zero_val |
higher_val |
auto[0] |
658 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
237 |
1 |
|
|
T86 |
1 |
|
T162 |
3 |
|
T27 |
2 |
zero_val |
lower_val |
auto[0] |
741 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
250 |
1 |
|
|
T86 |
1 |
|
T163 |
4 |
|
T162 |
3 |