Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100841753	1			T1	3061		T2	575693		T3	25486
all_pins[1]	100841753	1			T1	3061		T2	575693		T3	25486
all_pins[2]	100841753	1			T1	3061		T2	575693		T3	25486

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301680614	1			T1	8888		T2	172358		T3	76195
values[0x1]	844645	1			T1	295		T2	3499		T3	263
transitions[0x0=>0x1]	842606	1			T1	295		T2	3499		T3	263
transitions[0x1=>0x0]	842624	1			T1	295		T2	3499		T3	263

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100331480	1			T1	2773		T2	572194		T3	25223
all_pins[0]	values[0x1]	510273	1			T1	288		T2	3499		T3	263
all_pins[0]	transitions[0x0=>0x1]	510258	1			T1	288		T2	3499		T3	263
all_pins[0]	transitions[0x1=>0x0]	66	1			T1	7		T49	2		T50	6
all_pins[1]	values[0x0]	100841672	1			T1	3054		T2	575693		T3	25486
all_pins[1]	values[0x1]	81	1			T1	7		T49	2		T50	6
all_pins[1]	transitions[0x0=>0x1]	71	1			T1	7		T49	2		T50	6
all_pins[1]	transitions[0x1=>0x0]	334281	1			T22	835		T26	3134		T32	2090
all_pins[2]	values[0x0]	100507462	1			T1	3061		T2	575693		T3	25486
all_pins[2]	values[0x1]	334291	1			T22	835		T26	3134		T32	2090
all_pins[2]	transitions[0x0=>0x1]	332277	1			T22	835		T26	3111		T32	2089
all_pins[2]	transitions[0x1=>0x0]	508277	1			T1	288		T2	3499		T3	263