Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101384659	1			T1	458744		T2	463310		T3	224307
all_values[1]	101384659	1			T1	458744		T2	463310		T3	224307
all_values[2]	101384659	1			T1	458744		T2	463310		T3	224307

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

515320

1

T1

20

T2

27

T3

6

auto[1]

303638657

1

T1

137621

T2

138990

T3

672915

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302613864

1

T1

136615

T2

137966

T3

671130

auto[1]

1540113

1

T1

10080

T2

10266

T3

1791

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	162099	1			T1	1		T3	1		T12	413
all_values[0]	auto[0]	auto[1]	2135	1			T1	2		T3	2		T12	6
all_values[0]	auto[1]	auto[0]	100709189	1			T1	455383		T2	459888		T3	223709
all_values[0]	auto[1]	auto[1]	511236	1			T1	3358		T2	3422		T3	595
all_values[1]	auto[0]	auto[0]	161947	1			T2	16		T12	213		T15	1
all_values[1]	auto[0]	auto[1]	1550	1			T2	8		T12	4		T15	2
all_values[1]	auto[1]	auto[0]	100709341	1			T1	455384		T2	459872		T3	223710
all_values[1]	auto[1]	auto[1]	511821	1			T1	3360		T2	3414		T3	597
all_values[2]	auto[0]	auto[0]	186024	1			T1	11		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	1565	1			T1	6		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	100685264	1			T1	455373		T2	459886		T3	223709
all_values[2]	auto[1]	auto[1]	511806	1			T1	3354		T2	3421		T3	595